ARM: tegra: error check Tegra210 XUSB padctl waits
Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
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break;
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}
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if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
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debug(" timeout\n");
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return -ETIMEDOUT;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
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break;
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}
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
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debug(" timeout\n");
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return -ETIMEDOUT;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
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break;
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}
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if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
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debug(" timeout\n");
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return -ETIMEDOUT;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
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break;
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}
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if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
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debug(" timeout\n");
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return -ETIMEDOUT;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
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break;
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}
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if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
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debug(" timeout\n");
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return -ETIMEDOUT;
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}
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debug(" done\n");
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value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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