Exynos5422/5800: set cpu id to 0x5422
The proper CPU ID for those Exynos variants is 0x5422, but before the 0x5800 was set. This commit fix this back. Changes: - set cpu id to 0x5422 instead of 0x5800 - remove macro proid_is_exynos5800() - add macro proid_is_exynos5422() - change the calls to proid_is_exynos5800() with new macro Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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d64c8adedc
@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
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div = PLL_DIV_1024;
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else if (proid_is_exynos4412())
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div = PLL_DIV_65535;
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else if (proid_is_exynos5250() || proid_is_exynos5420()
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|| proid_is_exynos5800())
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else if (proid_is_exynos5250() || proid_is_exynos5420() ||
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proid_is_exynos5422())
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div = PLL_DIV_65536;
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else
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return 0;
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@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
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int i;
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struct clk_bit_info *info;
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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info = exynos542x_bit_info;
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else
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info = exynos5_bit_info;
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@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
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unsigned long clock_get_periph_rate(int peripheral)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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return exynos542x_get_periph_rate(peripheral);
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return exynos5_get_periph_rate(peripheral);
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} else {
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@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void)
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unsigned long get_pll_clk(int pllreg)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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return exynos542x_get_pll_clk(pllreg);
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return exynos5_get_pll_clk(pllreg);
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} else if (cpu_is_exynos4()) {
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@ -1692,7 +1692,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
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div -= 1;
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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exynos5420_set_mmc_clk(dev_index, div);
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else
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exynos5_set_mmc_clk(dev_index, div);
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@ -1708,7 +1708,7 @@ unsigned long get_lcd_clk(void)
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} else if (cpu_is_exynos5()) {
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if (proid_is_exynos5420())
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return exynos5420_get_lcd_clk();
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else if (proid_is_exynos5800())
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else if (proid_is_exynos5422())
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return exynos5800_get_lcd_clk();
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else
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return exynos5_get_lcd_clk();
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@ -1740,7 +1740,7 @@ void set_mipi_clk(void)
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int set_spi_clk(int periph_id, unsigned int rate)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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return exynos5420_set_spi_clk(periph_id, rate);
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return exynos5_set_spi_clk(periph_id, rate);
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}
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@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
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void system_clock_init(void)
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{
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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exynos5420_system_clock_init();
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else
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exynos5250_system_clock_init();
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@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void)
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CACHE_TAG_RAM_LATENCY_2_CYCLES |
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CACHE_DATA_RAM_LATENCY_2_CYCLES;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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if (proid_is_exynos5420() || proid_is_exynos5422()) {
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val |= CACHE_ECC_AND_PARITY |
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CACHE_TAG_RAM_LATENCY_3_CYCLES |
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CACHE_DATA_RAM_LATENCY_3_CYCLES;
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@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void)
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{
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uint32_t val;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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if (proid_is_exynos5420() || proid_is_exynos5422()) {
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mrc_l2_aux_ctlr(val);
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val |= CACHE_ENABLE_FORCE_L2_LOGIC |
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CACHE_DISABLE_CLEAN_EVICT;
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@ -237,7 +237,7 @@ static inline void s5p_set_cpu_id(void)
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* Exynos5800 is a variant of Exynos5420
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* and has product id 0x5422
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*/
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s5p_cpu_id = 0x5800;
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s5p_cpu_id = 0x5422;
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break;
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}
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}
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@ -267,7 +267,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
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IS_EXYNOS_TYPE(exynos4412, 0x4412)
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IS_EXYNOS_TYPE(exynos5250, 0x5250)
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IS_EXYNOS_TYPE(exynos5420, 0x5420)
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IS_EXYNOS_TYPE(exynos5800, 0x5800)
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IS_EXYNOS_TYPE(exynos5422, 0x5422)
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#define SAMSUNG_BASE(device, base) \
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static inline unsigned int __attribute__((no_instrument_function)) \
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@ -278,7 +278,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
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return EXYNOS4X12_##base; \
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return EXYNOS4_##base; \
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} else if (cpu_is_exynos5()) { \
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if (proid_is_exynos5420() || proid_is_exynos5800()) \
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if (proid_is_exynos5420() || proid_is_exynos5422()) \
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return EXYNOS5420_##base; \
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return EXYNOS5_##base; \
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} \
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@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
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static inline struct gpio_info *get_gpio_data(void)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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return exynos5420_gpio_data;
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else
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return exynos5_gpio_data;
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@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void)
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static inline unsigned int get_bank_num(void)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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return EXYNOS5420_GPIO_NUM_PARTS;
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else
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return EXYNOS5_GPIO_NUM_PARTS;
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@ -858,7 +858,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
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int exynos_pinmux_config(int peripheral, int flags)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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return exynos5420_pinmux_config(peripheral, flags);
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else if (proid_is_exynos5250())
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return exynos5_pinmux_config(peripheral, flags);
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@ -125,7 +125,7 @@ static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
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void set_usbdrd_phy_ctrl(unsigned int enable)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420() || proid_is_exynos5800())
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if (proid_is_exynos5420() || proid_is_exynos5422())
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exynos5420_set_usbdev_phy_ctrl(enable);
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else
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exynos5_set_usbdrd_phy_ctrl(enable);
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