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nios2: zap nios2-generic board dir

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As we use device tree to control u-boot now, the generic
board can be removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
This commit is contained in:
Thomas Chou 2015-10-23 14:55:36 +08:00
parent 7cacb64a35
commit 6168dc6a7a
10 changed files with 23 additions and 257 deletions
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16
arch/nios2/Kconfig
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@ -4,15 +4,11 @@ menu "Nios II architecture"
config SYS_ARCH
default "nios2"
choice
prompt "Target select"
optional
config TARGET_NIOS2_GENERIC
bool "Support nios2-generic"
endchoice
source "board/altera/nios2-generic/Kconfig"
config SYS_CONFIG_NAME
string "Board header file"
help
This option should contain the base name of board header file.
The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
should be included from include/config.h.
endmenu

33
board/altera/common/cfide.c
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@ -1,33 +0,0 @@
/*
* Altera CF drvier
*
* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE)
/* ide_set_reset for Altera CF interface */
#define ALTERA_CF_CTL_STATUS 0
#define ALTERA_CF_IDE_CTL 4
#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1)
#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2)
#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4)
#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK (0x8)
#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1)
void ide_set_reset(int idereset)
{
int i;
writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
ALTERA_CF_CTL_STATUS_POWER_MSK,
CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
/* wait 500 ms for power to stabilize */
for (i = 0; i < 500; i++)
udelay(1000);
}
#endif

12
board/altera/nios2-generic/Kconfig
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@ -1,12 +0,0 @@
if TARGET_NIOS2_GENERIC
config SYS_BOARD
default "nios2-generic"
config SYS_VENDOR
default "altera"
config SYS_CONFIG_NAME
default "nios2-generic"
endif

6
board/altera/nios2-generic/MAINTAINERS
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@ -1,6 +0,0 @@
NIOS2-GENERIC BOARD
M: Scott McNutt <smcnutt@psyent.com>
S: Maintained
F: board/altera/nios2-generic/
F: include/configs/nios2-generic.h
F: configs/nios2-generic_defconfig

10
board/altera/nios2-generic/Makefile
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@ -1,10 +0,0 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := nios2-generic.o
obj-$(CONFIG_CMD_IDE) += ../common/cfide.o

12
board/altera/nios2-generic/config.mk
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@ -1,12 +0,0 @@
#
# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

89
board/altera/nios2-generic/custom_fpga.h
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@ -1,89 +0,0 @@
/*
* This header is generated by sopc2dts
* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CUSTOM_FPGA_H_
#define _CUSTOM_FPGA_H_
/* generated from qsys_ghrd_3c120.sopcinfo */
/* Dumping slaves of cpu.data_master */
/* cpu.jtag_debug_module is a altera_nios2_qsys */
#define CONFIG_SYS_CLK_FREQ 125000000
#define CONFIG_SYS_DCACHE_SIZE 32768
#define CONFIG_SYS_DCACHELINE_SIZE 32
#define CONFIG_SYS_ICACHELINE_SIZE 32
#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020
#define CONFIG_SYS_ICACHE_SIZE 32768
#define CONFIG_SYS_RESET_ADDR 0xc2800000
#define IO_REGION_BASE 0xE0000000
/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */
/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */
/* ddr2_bot.s1 is a altmemddr2 */
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */
/* Dumping slaves of pb_cpu_to_io.m0 */
/* timer_1ms.s1 is a altera_avalon_timer */
#define CONFIG_SYS_TIMER_IRQ 11
#define CONFIG_SYS_TIMER_FREQ 125000000
#define CONFIG_SYS_TIMER_BASE 0xE8400000
/* sysid.control_slave is a altera_avalon_sysid_qsys */
#define CONFIG_SYS_SYSID_BASE 0xE8004D40
/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50
/* tse_mac.control_port is a triple_speed_ethernet */
#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048
#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800
#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400
#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048
#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000
#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000
#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000
#define CONFIG_ALTERA_TSE
#define CONFIG_MII
#define CONFIG_CMD_MII
#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18
#define CONFIG_SYS_ALTERA_TSE_FLAGS 1
/* uart.s1 is a altera_avalon_uart */
#define CONFIG_SYS_UART_BAUD 115200
#define CONFIG_SYS_UART_BASE 0xE8004C80
#define CONFIG_SYS_UART_FREQ 62500000
/* user_led_pio_8out.s1 is a altera_avalon_pio */
#define USER_LED_PIO_8OUT_BASE 0xE8004CC0
/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */
#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0
#define USER_DIPSW_PIO_8IN_IRQ 8
/* user_pb_pio_4in.s1 is a altera_avalon_pio */
#define USER_PB_PIO_4IN_BASE 0xE8004D00
#define USER_PB_PIO_4IN_IRQ 9
/* cfi_flash_64m.uas is a altera_generic_tristate_controller */
#define CFI_FLASH_64M_BASE 0xE0000000
/* ext_flash.s1 is a altera_avalon_cfi_flash */
#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
#endif /* _CUSTOM_FPGA_H_ */

76
board/altera/nios2-generic/nios2-generic.c
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@ -1,76 +0,0 @@
/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#if defined(CONFIG_CFI_FLASH_MTD)
#include <mtd/cfi_flash.h>
#endif
#include <asm/io.h>
#include <asm/gpio.h>
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
defined(CONFIG_CFI_FLASH_MTD)
static void __early_flash_cmd_reset(void)
{
/* reset flash before we read env */
writeb(AMD_CMD_RESET, CONFIG_ENV_ADDR);
writeb(FLASH_CMD_RESET, CONFIG_ENV_ADDR);
}
void early_flash_cmd_reset(void)
__attribute__((weak,alias("__early_flash_cmd_reset")));
#endif
int board_early_init_f(void)
{
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
defined(CONFIG_CFI_FLASH_MTD)
early_flash_cmd_reset();
#endif
return 0;
}
int checkboard(void)
{
#ifdef CONFIG_ALTERA_SYSID
display_sysid();
#endif
printf("BOARD: %s\n", CONFIG_BOARD_NAME);
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_DRIVER_DM9000
rc += dm9000_initialize(bis);
#endif
#ifdef CONFIG_ALTERA_TSE
rc += altera_tse_initialize(0,
CONFIG_SYS_ALTERA_TSE_MAC_BASE,
CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE,
#if defined(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE) && \
(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE > 0)
CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE,
CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE);
#else
0,
0);
#endif
#endif
#ifdef CONFIG_ETHOC
rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
#endif
return rc;
}
#endif

2
configs/nios2-generic_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_NIOS2=y
CONFIG_SYS_CONFIG_NAME="nios2-generic"
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_NIOS2_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y

24
include/configs/nios2-generic.h
View File

@ -12,12 +12,8 @@
/*
* BOARD/CPU
*/
#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
#define CONFIG_BOARD_EARLY_INIT_F /* enable early board-spec. init */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_NIOS_SYSID_BASE CONFIG_SYS_SYSID_BASE
/*
* SERIAL
@ -25,6 +21,18 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
/*
* CFI Flash
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
/*
* BOOTP options
*/
@ -49,11 +57,9 @@
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \
CONFIG_SYS_MONITOR_LEN) | \
CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_ADDR 0xe2840000
/*
* MEMORY ORGANIZATION
@ -61,6 +67,8 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \