This patch adds uart support for MediaTek MT7620 and earlier SoCs.
The UART used by MT7620 is incompatible with the ns16550a driver.
All registers of this UART have different addresses. A special 16-bit
register for Divisor Latch is used to set the baudrate instead of the
original two 8-bit registers (DLL and DLM).
The driver supports of-platdata which is useful for tiny SPL.
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
In case the clock framework is enabled, enable the SPI controller clock
and obtain max frequency from the clock framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
The CSPI/ECSPI register bits do not differ between newer SoCs, instead
of having multiple copies of the same thing for each iMX SoC, define
the bits in the driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Add ECSPI clock entries to iMX8MN clock driver. Only make those entries
available in case SPI support in U-Boot is enabled at all to conserve
space, esp. in SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Now that header files no longer include common.h it must be included
first.
Otherwise the build fails with errors like
include/asm/arch/clock.h:43:1: error: unknown type name 'u32'
u32 imx_get_uartclk(void);
Fixes: c3dc39a2f8 ("arm: Don't include common.h in header files")
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Simon Glass <sjg@chromium.org>
When doing DDR scrub, the DDR may enter into self refresh if the
selfref_en is enabled before DDR scrub. This will cause scrub
can't complete that SBRSTAT.scrub_done won't be set.
Since the selfref_en can be programmed during the course of
normal operation, move it after DDR scrub
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Take into account all RGMII interface types. Depending on it
the RGMII PHY's timings are setup.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
clk_set_rate() returns the set rate in case of success and a
negative number in case of failure. Consider failure only the
negative numbers.
Fixes: 3ef64444de ("dm: net: macb: Implement link speed change callback")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Different implementation of USER IO register needs different
mapping for bit fields of this register. Add implementation
for this and, since clken is part of USER IO and it needs to
be activated based on per SoC capabilities, add caps in
macb_config where clken specific information needs to be filled.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Use dev_read_prop instead of using the fdt_read_property which
reads from the GD struct's fdt.
This way the node is accessed via the device config instead of the
global struct, which makes code more portable and GD independent.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
There is no need to define the same macros in drivers.
All macros have been added by commit 17a42abb40 ("mmc: Define timing
macro's").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
A sporadic condition occurs when the "bad packet" error is triggered
repeatedly, which results in "bad packet" messages scrolling on the
console during transfer. To avoid triggering this, reset the internal
RXFC count on the first occurance of the "bad packet", which forces
the code to re-read the RX packet count from the MAC, and prevents
any additional "bad packet" messages if there are no more packets in
the MAC. Also print better debug information if this condition occurs.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Tom Rini <trini@konsulko.com>
Implement programming MAC address to the hardware also for device model
configuration.
Fixes: b565b18a29 ("board: ge: bx50v3: Enable DM for PCI and ethernet")
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
The timer being used by this driver may have already been used by first
stage bootloader (e.g. ATF/preloader), and it's settings may differ from
what this driver is going to use.
This may cause issues, such as inaccurate timer frequency due to
incorrect clock divider.
This patch adds the initialization code to avoid them.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
If no GPIO controller is found, the return value should not depend on a
random value on the stack. Initialize variable ret.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write()
and mw_eeprom_read() have incorrect loop conditions:
while (len <= 2) {
CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Avoid calling free(addr) twice if the device for ucode is not found.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Freeing a buffer before calling hang() is superfluous. Removing the call
reduces the SPL size.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Calling calloc() for 0 members does not make any sense.
Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally
unreasonable.
The current code will lead to a NULL dereference in bcm6348_iudma_enable().
The assignments for ch_priv->busy_desc are obviously swapped.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This adds basic register access and child regulator binding
for the Monolithic MP5416 Power Management IC which integrates
four DC/DC switching converters and five LDO regulators.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.
However, currently the patch supports only the booting from
memory-mapped SPI flash.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
AST2600 has 8 watchdog timers including 8 sets of
32-bit decrement counters, based on 1MHz clock.
A 64-bit reset mask is also supported to specify
which controllers should be reset by the WDT reset.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
This patch adds the clock control driver
for the AST2600 SoC.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Add Cortina Access parallel Nand support for CAxxxx SOCs
Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
CC: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
The driver only needs to retrieve the pin for the ACPI info. The driver
itself works without depending on GPIO.
Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
- Select TIMER_EARLY to avoid infinite recursion for Trace.
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).
So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.
This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.
This also avoids pin re-muxing to same type that is for example from
command line device is asked to re-probe/select (mmc dev x) we return
early with success in this case as the pin is already muxed.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid
name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h
to LPDDR4_BIT_MASK().
Remove superfluous parantheses.
Remove superfluous comparison to 0.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
log.h and dm/devres.h are U-Boot includes. So placing them
behind #ifndef __UBOOT__ does not make any sense.
Fixes: f7ae49fc4f ("common: Drop log.h from common header")
Fixes: 61b29b8268 ("dm: core: Require users of devres to include the header")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
U-Boot DM model probe only single device at a time
which is enabled and configured using device tree
or platform data method.
PL011 UART IP is SBSA compliant and firmware does the
serial port set-up, initialization and let the kernel use
UART port for sending and receiving characters.
Normally software talk to one serial port time but some
LayerScape platform require all the UART devices enabled
in Linux for various use case.
Adding support to probe all enabled serial devices like SBSA
compliant PL011 UART ports probe and initialization by firmware.
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Support a common method to probe all devices associated with uclass.
This includes data structures and code for finding the first device and
looping for remaining devices associated with uclasses (groups of devices
with the same purpose, e.g. all SERIAL ports will be in the same uclass).
An example is SBSA compliant PL011 UART IP, where firmware does the serial
port initialization and prepare uart device to let the kernel use it for
sending and reveiving the characters.SERIAL uclass will use this function
to initialize PL011 UART ports.
The feature is enabled with CONFIG_DM.
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
power/regulator will not be built if just CONFIG_SPL_DM_REGULATOR is
enabled. It needs CONFIG_SPL_POWER_SUPPORT to be enabled as well.
For example, if we just need a GPIO regulator in SPL:
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
Will not suffice, since the entire regulator build for SPL depends on
CONFIG_SPL_POWER_SUPPORT. Elaborate that information in the Kconfig
dependency.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
During build of simple panel driver backlight is needed so let's enable
it:
aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_set_backlight':
u-boot/drivers/video/simple_panel.c:43: undefined reference to `backlight_set_brightness'
aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_enable_backlight':
u-boot/drivers/video/simple_panel.c:28: undefined reference to `backlight_enable'
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
write_mbr_partition() function name is a bit misleading, so rename it to
write_mbr_sector(). This is a preparation for adding code for writing a
complete MBR partition layout.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Add a return value to bb_miiphy_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a return value to xen_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a return value to pci_init and use it directly in the post-relocation
init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a return value to pci_ep_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Something was wrong in the merge process into the mainline.
Some added patches access driver structure fields and functions that
have been modified by previous patches.
The patch renames:
- dev_get_platdata to dev_get_plat
- dev_get_uclass_platdata to dev_get_uclass_plat
- ofdata_to_platdata to of_to_plat
- plat_data_alloc_size to plat_auto
- priv_auto_alloc_size to priv_auto
- video_uc_platdata to video_uc_plat
Signed-off-by: Dario Binacchi <dariobin@libero.it>
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Change 'clksel' callback function to allow the code to return a
status.
This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
in Intel SoC FPGA. This patch does not change functionality.
When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
related register is secure register which is required to be written
via SMC/PCSI call. It is possible that U-Boot fail to write the
register if there is unexpected error between U-Boot and ATF.
As a result, there maybe signal integrity on MMC connection due to
clock. So, the code should reports error to user when 'clksel' fail.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
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Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
Change pr_* to dev_ or log_ macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change pr_* to dev_ or log_ macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change pr_* to dev_ or log_ macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change pr_* to dev_ or log_ macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug/pr_* to log_* or dev_* macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug/pr_debug to log_debug or dev_dbg macro and
define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change pr_debug to log_debug or dev_dbg macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug to dev_dbg macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Change debug to dev_dbg macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug to dev_dbg macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug and pr_ macro to dev macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug and pr_ macro to dev macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug and pr_ macro to dev macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug and pr_err to dev macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug and pr_err to dev macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Define LOG_CATEGORY, use dev_ macro when it is possible.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Define LOG_CATEGORY, use dev_ macro when it is possible
and migrate other trace to log_ macro.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Define LOG_CATEGORY, change debug to dev_dbg and remove "%s:" __func__
header as it is managed by dev macro (dev->name is displayed)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Define LOG_CATEGORY and remove unneeded pr_fmt macro with the dev
macro as dev->name is displayed and CONFIG_LOGF_FUNC can be
activated for log macro.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug to dev_dbg macro and define LOG_CATEGORY.
Remove dev->name as it is already displayed by dev macro.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change debug to log macro and define LOG_CATEGORY.
Remove "%s:" with __func__ as it is managed by log macro
(CONFIG_LOGF_FUNC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Remove unused function in exynos_dw_mmc.c.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ARMv8's generic timer[1] picks up it's graycode from GTC. However,
the frequency of the GTC is supposed to be programmed in CNTFID0[2]
register prior to enabling the GTC in CNTCR[3] register.
In K3 architecture, GTC provides a central time to many parts of the
SoC including graycode to the generic timer in the ARMv8 subsystem.
However, due to the central nature and the need to enable the counter
early in the boot process, the R5 based u-boot enables GTC and
programs it's frequency based on central needs of the system. This
may not be a constant 200MHz based on the system. The bootloader is
supposed to program the FID0 register with the correct frequency it
has sourced for GTC from the central system controller OR from PLLs
as appropriate, and TF-A is supposed[4] to use that as the frequency for
it's local timer.
Currently we are programming just the CNTCR[3] register to enable the
GTC, however we dont let TF-A know the frequency that GTC is actually
running at. A mismatch in programmed frequency and what we program for
generic timer will, as we can imagine, all kind of weird mayhem.
So, program the CNTFID0 register with the clock frequency. Note:
assigned-clock-rates should have set the clock frequency, so the only
operation we need to explicitly do is to retrieve the frequency and
program it in FID0 register.
Since the valid in K3 for GTC clock frequencies are < U32_MAX, we can
just cast the ulong and continue.
[1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary
[2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0
[3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr
[4] 6a22d9ea3c
Signed-off-by: Nishanth Menon <nm@ti.com>
The schedule for deprecating the features of the pre-driver-model puts
2019.17 as the deadline for the video subsystem. Furthermore, the latest
patches applied to the am335x-fb.c module have decreased the amount of
code shared with the pre-driver-model implementation. Splitting the two
implementations into two modules improves the readability of the code
and will make it easier to drop the pre-driver-model code.
I have not created a header file with the data structures and the
constants for accessing the LCD controller registers, but I preferred to
keep them inside the two c modules. This is a code replication until the
pre-driver-model version is dropped.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
The patch configures the display DPLL using the functions provided by
the driver model API for the clock. The device tree contains everything
needed to get the DPLL clock. The round rate function developed for
calculating the DPLL multiplier and divisor and the platform routines
for accessing the DPLL registers are removed from the LCD driver code
because they are implemented inside the DPLL clock driver.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
The previous version of am335x-fb.c contained the functionalities of two
drivers that this patch has split. It was a video type driver that used
the same registration compatible string that now registers a panel type
driver. The proof of this is that two compatible strings were referred
to within the same driver.
There are now two drivers, each with its own compatible string,
functions and API.
Furthermore, the panel driver, in addition to decoding the display
timings, is now also able to manage the backlight.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
