reset: aspeed: Add AST2600 reset support
Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
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@ -81,6 +81,15 @@ config RESET_AST2500
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Say Y if you want to control reset signals of different peripherals
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through System Control Unit (SCU).
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config RESET_AST2600
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bool "Reset controller driver for AST2600 SoCs"
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depends on DM_RESET
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default y if ASPEED_AST2600
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help
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Support for reset controller on AST2600 SoC.
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Say Y if you want to control reset signals of different peripherals
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through System Control Unit (SCU).
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config RESET_ROCKCHIP
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bool "Reset controller driver for Rockchip SoCs"
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depends on DM_RESET && ARCH_ROCKCHIP && CLK
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@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
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obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
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obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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108
drivers/reset/reset-ast2600.c
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108
drivers/reset/reset-ast2600.c
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@ -0,0 +1,108 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020 ASPEED Technology Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <misc.h>
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#include <reset.h>
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#include <reset-uclass.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <asm/arch/scu_ast2600.h>
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struct ast2600_reset_priv {
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struct ast2600_scu *scu;
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};
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static int ast2600_reset_request(struct reset_ctl *reset_ctl)
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{
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
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reset_ctl->dev, reset_ctl->id);
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return 0;
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}
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static int ast2600_reset_free(struct reset_ctl *reset_ctl)
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{
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
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reset_ctl->dev, reset_ctl->id);
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return 0;
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}
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static int ast2600_reset_assert(struct reset_ctl *reset_ctl)
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{
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struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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struct ast2600_scu *scu = priv->scu;
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debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
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if (reset_ctl->id < 32)
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writel(BIT(reset_ctl->id), scu->modrst_ctrl1);
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else
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writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2);
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return 0;
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}
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static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
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{
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struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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struct ast2600_scu *scu = priv->scu;
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debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
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if (reset_ctl->id < 32)
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writel(BIT(reset_ctl->id), scu->modrst_clr1);
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else
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writel(BIT(reset_ctl->id - 32), scu->modrst_clr2);
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return 0;
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}
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static int ast2600_reset_probe(struct udevice *dev)
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{
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int rc;
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struct ast2600_reset_priv *priv = dev_get_priv(dev);
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struct udevice *scu_dev;
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/* get SCU base from clock device */
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rc = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
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if (rc) {
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debug("%s: clock device not found, rc=%d\n", __func__, rc);
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return rc;
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}
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priv->scu = devfdt_get_addr_ptr(scu_dev);
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if (IS_ERR_OR_NULL(priv->scu)) {
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debug("%s: invalid SCU base pointer\n", __func__);
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return PTR_ERR(priv->scu);
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}
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return 0;
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}
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static const struct udevice_id ast2600_reset_ids[] = {
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{ .compatible = "aspeed,ast2600-reset" },
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{ }
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};
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struct reset_ops ast2600_reset_ops = {
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.request = ast2600_reset_request,
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.rfree = ast2600_reset_free,
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.rst_assert = ast2600_reset_assert,
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.rst_deassert = ast2600_reset_deassert,
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};
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U_BOOT_DRIVER(ast2600_reset) = {
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.name = "ast2600_reset",
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.id = UCLASS_RESET,
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.of_match = ast2600_reset_ids,
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.probe = ast2600_reset_probe,
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.ops = &ast2600_reset_ops,
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.priv_auto = sizeof(struct ast2600_reset_priv),
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};
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70
include/dt-bindings/reset/ast2600-reset.h
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70
include/dt-bindings/reset/ast2600-reset.h
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@ -0,0 +1,70 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) ASPEED Technology Inc.
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*/
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#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_
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#define _ABI_MACH_ASPEED_AST2600_RESET_H_
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#define ASPEED_RESET_FSI (59)
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#define ASPEED_RESET_RESERVED58 (58)
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#define ASPEED_RESET_RESERVED57 (57)
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#define ASPEED_RESET_SD (56)
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#define ASPEED_RESET_ADC (55)
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#define ASPEED_RESET_JTAG_MASTER2 (54)
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#define ASPEED_RESET_MAC4 (53)
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#define ASPEED_RESET_MAC3 (52)
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#define ASPEED_RESET_RESERVE51 (51)
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#define ASPEED_RESET_RESERVE50 (50)
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#define ASPEED_RESET_RESERVE49 (49)
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#define ASPEED_RESET_RESERVE48 (48)
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#define ASPEED_RESET_RESERVE47 (47)
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#define ASPEED_RESET_RESERVE46 (46)
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#define ASPEED_RESET_I3C5 (45)
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#define ASPEED_RESET_I3C4 (44)
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#define ASPEED_RESET_I3C3 (43)
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#define ASPEED_RESET_I3C2 (42)
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#define ASPEED_RESET_I3C1 (41)
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#define ASPEED_RESET_I3C0 (40)
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#define ASPEED_RESET_I3C_DMA (39)
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#define ASPEED_RESET_RESERVED38 (38)
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#define ASPEED_RESET_PWM (37)
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#define ASPEED_RESET_PECI (36)
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#define ASPEED_RESET_MII (35)
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#define ASPEED_RESET_I2C (34)
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#define ASPEED_RESET_RESERVED33 (33)
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#define ASPEED_RESET_LPC_ESPI (32)
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#define ASPEED_RESET_H2X (31)
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#define ASPEED_RESET_GP_MCU (30)
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#define ASPEED_RESET_DP_MCU (29)
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#define ASPEED_RESET_DP (28)
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#define ASPEED_RESET_RC_XDMA (27)
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#define ASPEED_RESET_GRAPHICS (26)
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#define ASPEED_RESET_DEV_XDMA (25)
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#define ASPEED_RESET_DEV_MCTP (24)
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#define ASPEED_RESET_RC_MCTP (23)
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#define ASPEED_RESET_JTAG_MASTER (22)
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#define ASPEED_RESET_PCIE_DEV_OE (21)
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#define ASPEED_RESET_PCIE_DEV_O (20)
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#define ASPEED_RESET_PCIE_RC_OE (19)
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#define ASPEED_RESET_PCIE_RC_O (18)
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#define ASPEED_RESET_RESERVED17 (17)
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#define ASPEED_RESET_EMMC (16)
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#define ASPEED_RESET_UHCI (15)
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#define ASPEED_RESET_EHCI_P1 (14)
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#define ASPEED_RESET_CRT (13)
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#define ASPEED_RESET_MAC2 (12)
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#define ASPEED_RESET_MAC1 (11)
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#define ASPEED_RESET_RESERVED10 (10)
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#define ASPEED_RESET_RVAS (9)
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#define ASPEED_RESET_PCI_VGA (8)
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#define ASPEED_RESET_2D (7)
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#define ASPEED_RESET_VIDEO (6)
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#define ASPEED_RESET_PCI_DP (5)
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#define ASPEED_RESET_HACE (4)
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#define ASPEED_RESET_EHCI_P2 (3)
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#define ASPEED_RESET_RESERVED2 (2)
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#define ASPEED_RESET_AHB (1)
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#define ASPEED_RESET_SDRAM (0)
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#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */
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