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- Enable logging features for stm32mp15 boards

Browse Source 
- Update MAINTAINERS emails for STI and STM32
 - Activate OF_LIVE for ST stm32mp15 boards
 - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
 - Correction in stm32prog command on uart: always flush DFU on start command
 - Update USB-C power detection algorithm on DK boards
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Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
This commit is contained in:
Tom Rini 2021-01-13 15:00:53 -05:00
commit ab1a425524
74 changed files with 847 additions and 724 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/stih410-b2260-u-boot.dtsi
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@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*
*/

2
arch/arm/dts/stih410-b2260.dts
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@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 STMicroelectronics (R&D) Limited.
* Author: Patrice Chotard <patrice.chotard@st.com>
* Author: Patrice Chotard <patrice.chotard@foss.st.com>
*/
/dts-v1/;
#include "stih410.dtsi"

2
arch/arm/dts/stm32429i-eval-u-boot.dtsi
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@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/memory/stm32-sdram.h>

2
arch/arm/dts/stm32f429-disco-u-boot.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/memory/stm32-sdram.h>

2
arch/arm/dts/stm32f469-disco-u-boot.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/memory/stm32-sdram.h>

2
arch/arm/dts/stm32h743i-disco.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2017 - Patrice Chotard <patrice.chotard@st.com>
* Copyright 2017 - Patrice Chotard <patrice.chotard@foss.st.com>
*
*/

25
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View File

@ -72,8 +72,8 @@
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
pinctrl-0 = <&fmc_pins_b>;
pinctrl-1 = <&fmc_sleep_pins_b>;
pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
fmc_pins_b: fmc-0 {
@ -130,6 +130,21 @@
<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
};
};
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
mco2_sleep_pins_a: mco2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
};
};
};
&pmic {
@ -181,7 +196,7 @@
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_MCO2_PLL4P
>;
st,clkdiv = <
@ -195,7 +210,7 @@
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
1 /*MCO2*/
>;
st,pkcs = <
@ -258,7 +273,7 @@
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 1 49 11 11 11 PQR(1,1,1) >;
cfg = < 1 49 5 11 11 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};

3
arch/arm/dts/stm32mp15xx-dhcom.dtsi
View File

@ -58,7 +58,6 @@
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth_ref_clk_sel;
phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
mdio0 {
@ -267,7 +266,7 @@
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
bias-disable;

8
arch/arm/mach-stm32mp/boot_params.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <log.h>
#include <asm/sections.h>
@ -32,15 +34,15 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
*/
void *board_fdt_blob_setup(void)
{
debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb);
log_debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb);
/* use external device tree only if address is valid */
if (nt_fw_dtb >= STM32_DDR_BASE) {
if (fdt_magic(nt_fw_dtb) == FDT_MAGIC)
return (void *)nt_fw_dtb;
debug("%s: DTB not found.\n", __func__);
log_debug("%s: DTB not found.\n", __func__);
}
debug("%s: fall back to builtin DTB, %p\n", __func__, &_end);
log_debug("%s: fall back to builtin DTB, %p\n", __func__, &_end);
return (void *)&_end;
}

38
arch/arm/mach-stm32mp/bsec.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_MISC
#include <common.h>
#include <dm.h>
#include <log.h>
@ -10,6 +12,7 @@
#include <asm/io.h>
#include <asm/arch/bsec.h>
#include <asm/arch/stm32mp1_smc.h>
#include <dm/device_compat.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>
@ -160,7 +163,7 @@ static int bsec_power_safmem(u32 base, bool power)
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
static int bsec_shadow_register(u32 base, u32 otp)
static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
{
u32 val;
int ret;
@ -168,7 +171,8 @@ static int bsec_shadow_register(u32 base, u32 otp)
/* check if shadowing of otp is locked */
if (bsec_read_SR_lock(base, otp))
pr_debug("bsec : OTP %d is locked and refreshed with 0\n", otp);
dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
otp);
/* check if safemem is power up */
val = readl(base + BSEC_OTP_STATUS_OFF);
@ -203,7 +207,7 @@ static int bsec_shadow_register(u32 base, u32 otp)
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
static int bsec_read_shadow(u32 base, u32 *val, u32 otp)
static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
{
*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
@ -217,11 +221,11 @@ static int bsec_read_shadow(u32 base, u32 *val, u32 otp)
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
static int bsec_write_shadow(u32 base, u32 val, u32 otp)
static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
{
/* check if programming of otp is locked */
if (bsec_read_SW_lock(base, otp))
pr_debug("bsec : OTP %d is lock, write will be ignore\n", otp);
dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
@ -236,16 +240,16 @@ static int bsec_write_shadow(u32 base, u32 val, u32 otp)
* after the function the otp data is not refreshed in shadow
* Return: 0 if no error
*/
static int bsec_program_otp(long base, u32 val, u32 otp)
static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
{
u32 ret;
bool power_up = false;
if (bsec_read_SP_lock(base, otp))
pr_debug("bsec : OTP %d locked, prog will be ignore\n", otp);
dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
pr_debug("bsec : Global lock, prog will be ignore\n");
dev_dbg(dev, "Global lock, prog will be ignore\n");
/* check if safemem is power up */
if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
@ -298,21 +302,21 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
plat = dev_get_plat(dev);
/* read current shadow value */
ret = bsec_read_shadow(plat->base, &tmp_data, otp);
ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
if (ret)
return ret;
/* copy otp in shadow */
ret = bsec_shadow_register(plat->base, otp);
ret = bsec_shadow_register(dev, plat->base, otp);
if (ret)
return ret;
ret = bsec_read_shadow(plat->base, val, otp);
ret = bsec_read_shadow(dev, plat->base, val, otp);
if (ret)
return ret;
/* restore shadow value */
ret = bsec_write_shadow(plat->base, tmp_data, otp);
ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
return ret;
}
@ -328,7 +332,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
plat = dev_get_plat(dev);
return bsec_read_shadow(plat->base, val, otp);
return bsec_read_shadow(dev, plat->base, val, otp);
}
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
@ -352,7 +356,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
plat = dev_get_plat(dev);
return bsec_program_otp(plat->base, val, otp);
return bsec_program_otp(dev, plat->base, val, otp);
}
@ -367,7 +371,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
plat = dev_get_plat(dev);
return bsec_write_shadow(plat->base, val, otp);
return bsec_write_shadow(dev, plat->base, val, otp);
}
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
@ -497,7 +501,7 @@ static int stm32mp_bsec_probe(struct udevice *dev)
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
if (!bsec_read_SR_lock(plat->base, otp))
bsec_shadow_register(plat->base, otp);
bsec_shadow_register(dev, plat->base, otp);
}
return 0;
@ -527,7 +531,7 @@ bool bsec_dbgswenable(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stm32mp_bsec), &dev);
if (ret || !dev) {
pr_debug("bsec driver not available\n");
log_debug("bsec driver not available\n");
return false;
}

3
arch/arm/mach-stm32mp/cmd_stm32key.c
View File

@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
#include <console.h>
#include <log.h>
#include <misc.h>
#include <dm/device.h>
#include <dm/uclass.h>
@ -34,7 +35,7 @@ static void fuse_hash_value(u32 addr, bool print)
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
pr_err("Can't find stm32mp_bsec driver\n");
log_err("Can't find stm32mp_bsec driver\n");
return;
}

4
arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
View File

@ -56,7 +56,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
link = LINK_SERIAL;
if (link == LINK_UNDEFINED) {
pr_err("not supported link=%s\n", argv[1]);
log_err("not supported link=%s\n", argv[1]);
return CMD_RET_USAGE;
}
@ -90,7 +90,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
data = (struct stm32prog_data *)malloc(sizeof(*data));
if (!data) {
pr_err("Alloc failed.");
log_err("Alloc failed.");
return CMD_RET_FAILURE;
}
stm32prog_data = data;

112
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
View File

@ -97,28 +97,28 @@ u8 stm32prog_header_check(struct raw_header_s *raw_header,
header->image_length = 0x0;
if (!raw_header || !header) {
pr_debug("%s:no header data\n", __func__);
log_debug("%s:no header data\n", __func__);
return -1;
}
if (raw_header->magic_number !=
(('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
pr_debug("%s:invalid magic number : 0x%x\n",
__func__, raw_header->magic_number);
log_debug("%s:invalid magic number : 0x%x\n",
__func__, raw_header->magic_number);
return -2;
}
/* only header v1.0 supported */
if (raw_header->header_version != 0x00010000) {
pr_debug("%s:invalid header version : 0x%x\n",
__func__, raw_header->header_version);
log_debug("%s:invalid header version : 0x%x\n",
__func__, raw_header->header_version);
return -3;
}
if (raw_header->reserved1 != 0x0 || raw_header->reserved2) {
pr_debug("%s:invalid reserved field\n", __func__);
log_debug("%s:invalid reserved field\n", __func__);
return -4;
}
for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) {
if (raw_header->padding[i] != 0) {
pr_debug("%s:invalid padding field\n", __func__);
log_debug("%s:invalid padding field\n", __func__);
return -5;
}
}
@ -376,7 +376,7 @@ static int parse_flash_layout(struct stm32prog_data *data,
last = start + size;
*last = 0x0; /* force null terminated string */
pr_debug("flash layout =\n%s\n", start);
log_debug("flash layout =\n%s\n", start);
/* calculate expected number of partitions */
part_list_size = 1;
@ -584,11 +584,11 @@ static int init_device(struct stm32prog_data *data,
last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) *
block_dev->blksz;
}
pr_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
block_dev->lba, block_dev->blksz);
pr_debug(" available address = 0x%llx..0x%llx\n",
first_addr, last_addr);
pr_debug(" full_update = %d\n", dev->full_update);
log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
block_dev->lba, block_dev->blksz);
log_debug(" available address = 0x%llx..0x%llx\n",
first_addr, last_addr);
log_debug(" full_update = %d\n", dev->full_update);
break;
case STM32PROG_NOR:
case STM32PROG_NAND:
@ -598,7 +598,7 @@ static int init_device(struct stm32prog_data *data,
return -ENODEV;
}
get_mtd_by_target(mtd_id, dev->target, dev->dev_id);
pr_debug("%s\n", mtd_id);
log_debug("%s\n", mtd_id);
mtdparts_init();
mtd = get_mtd_device_nm(mtd_id);
@ -609,10 +609,10 @@ static int init_device(struct stm32prog_data *data,
first_addr = 0;
last_addr = mtd->size;
dev->erase_size = mtd->erasesize;
pr_debug("MTD device %s: size=%lld erasesize=%d\n",
mtd_id, mtd->size, mtd->erasesize);
pr_debug(" available address = 0x%llx..0x%llx\n",
first_addr, last_addr);
log_debug("MTD device %s: size=%lld erasesize=%d\n",
mtd_id, mtd->size, mtd->erasesize);
log_debug(" available address = 0x%llx..0x%llx\n",
first_addr, last_addr);
dev->mtd = mtd;
break;
case STM32PROG_RAM:
@ -624,13 +624,13 @@ static int init_device(struct stm32prog_data *data,
stm32prog_err("unknown device type = %d", dev->target);
return -ENODEV;
}
pr_debug(" erase size = 0x%x\n", dev->erase_size);
pr_debug(" full_update = %d\n", dev->full_update);
log_debug(" erase size = 0x%x\n", dev->erase_size);
log_debug(" full_update = %d\n", dev->full_update);
/* order partition list in offset order */
list_sort(NULL, &dev->part_list, &part_cmp);
part_id = 1;
pr_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n");
log_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n");
list_for_each_entry(part, &dev->part_list, list) {
if (part->bin_nb > 1) {
if ((dev->target != STM32PROG_NAND &&
@ -650,10 +650,10 @@ static int init_device(struct stm32prog_data *data,
part->size = block_dev->lba * block_dev->blksz;
else
part->size = last_addr;
pr_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n",
part->option, part->id, part->name,
part->part_type, part->bin_nb, part->target,
part->dev_id, part->addr, part->size);
log_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n",
part->option, part->id, part->name,
part->part_type, part->bin_nb, part->target,
part->dev_id, part->addr, part->size);
continue;
}
if (part->part_id < 0) { /* boot hw partition for eMMC */
@ -709,10 +709,10 @@ static int init_device(struct stm32prog_data *data,
part->dev->erase_size);
return -EINVAL;
}
pr_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx",
part->part_id, part->option, part->id, part->name,
part->part_type, part->bin_nb, part->target,
part->dev_id, part->addr, part->size);
log_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx",
part->part_id, part->option, part->id, part->name,
part->part_type, part->bin_nb, part->target,
part->dev_id, part->addr, part->size);
part_addr = 0;
part_size = 0;
@ -726,7 +726,7 @@ static int init_device(struct stm32prog_data *data,
* created for full update
*/
if (dev->full_update || part->part_id < 0) {
pr_debug("\n");
log_debug("\n");
continue;
}
struct disk_partition partinfo;
@ -770,11 +770,11 @@ static int init_device(struct stm32prog_data *data,
/* no partition for this device */
if (!part_found) {
pr_debug("\n");
log_debug("\n");
continue;
}
pr_debug(" %08llx %08llx\n", part_addr, part_size);
log_debug(" %08llx %08llx\n", part_addr, part_size);
if (part->addr != part_addr) {
stm32prog_err("%s (0x%x): Bad address for partition %d (%s) = 0x%llx <> 0x%llx expected",
@ -910,8 +910,8 @@ static int create_gpt_partitions(struct stm32prog_data *data)
continue;
if (offset + 100 > buflen) {
pr_debug("\n%s: buffer too small, %s skippped",
__func__, part->name);
log_debug("\n%s: buffer too small, %s skippped",
__func__, part->name);
continue;
}
@ -959,7 +959,7 @@ static int create_gpt_partitions(struct stm32prog_data *data)
if (offset) {
offset += snprintf(buf + offset, buflen - offset, "\"");
pr_debug("\ncmd: %s\n", buf);
log_debug("\ncmd: %s\n", buf);
if (run_command(buf, 0)) {
stm32prog_err("GPT partitionning fail: %s",
buf);
@ -974,7 +974,7 @@ static int create_gpt_partitions(struct stm32prog_data *data)
#ifdef DEBUG
sprintf(buf, "gpt verify mmc %d", data->dev[i].dev_id);
pr_debug("\ncmd: %s", buf);
log_debug("\ncmd: %s", buf);
if (run_command(buf, 0))
printf("fail !\n");
else
@ -1098,10 +1098,10 @@ static int stm32prog_alt_add(struct stm32prog_data *data,
stm32prog_err("invalid target: %d", part->target);
return ret;
}
pr_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf);
log_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf);
ret = dfu_alt_add(dfu, dfustr, devstr, buf);
pr_debug("dfu_alt_add(%s,%s,%s) result %d\n",
dfustr, devstr, buf, ret);
log_debug("dfu_alt_add(%s,%s,%s) result %d\n",
dfustr, devstr, buf, ret);
return ret;
}
@ -1116,7 +1116,7 @@ static int stm32prog_alt_add_virt(struct dfu_entity *dfu,
sprintf(devstr, "%d", phase);
sprintf(buf, "@%s/0x%02x/1*%dBe", name, phase, size);
ret = dfu_alt_add(dfu, "virt", devstr, buf);
pr_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret);
log_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret);
return ret;
}
@ -1171,7 +1171,7 @@ static int dfu_init_entities(struct stm32prog_data *data)
sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000",
PHASE_FLASHLAYOUT, STM32_DDR_BASE);
ret = dfu_alt_add(dfu, "ram", NULL, buf);
pr_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
}
if (!ret)
@ -1196,7 +1196,7 @@ static int dfu_init_entities(struct stm32prog_data *data)
int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
long *size)
{
pr_debug("%s: %x %lx\n", __func__, offset, *size);
log_debug("%s: %x %lx\n", __func__, offset, *size);
if (!data->otp_part) {
data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE);
@ -1226,7 +1226,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
return -1;
}
pr_debug("%s: %x %lx\n", __func__, offset, *size);
log_debug("%s: %x %lx\n", __func__, offset, *size);
/* alway read for first packet */
if (!offset) {
if (!data->otp_part)
@ -1258,7 +1258,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
memcpy(buffer, (void *)((u32)data->otp_part + offset), *size);
end_otp_read:
pr_debug("%s: result %i\n", __func__, result);
log_debug("%s: result %i\n", __func__, result);
return result;
}
@ -1292,20 +1292,20 @@ int stm32prog_otp_start(struct stm32prog_data *data)
result = 0;
break;
default:
pr_err("%s: OTP incorrect value (err = %ld)\n",
__func__, res.a1);
log_err("%s: OTP incorrect value (err = %ld)\n",
__func__, res.a1);
result = -EINVAL;
break;
}
} else {
pr_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
__func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0);
log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
__func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0);
result = -EINVAL;
}
free(data->otp_part);
data->otp_part = NULL;
pr_debug("%s: result %i\n", __func__, result);
log_debug("%s: result %i\n", __func__, result);
return result;
}
@ -1313,7 +1313,7 @@ int stm32prog_otp_start(struct stm32prog_data *data)
int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
long *size)
{
pr_debug("%s: %x %lx\n", __func__, offset, *size);
log_debug("%s: %x %lx\n", __func__, offset, *size);
if (!offset)
memset(data->pmic_part, 0, PMIC_SIZE);
@ -1338,7 +1338,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
return -EOPNOTSUPP;
}
pr_debug("%s: %x %lx\n", __func__, offset, *size);
log_debug("%s: %x %lx\n", __func__, offset, *size);
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stpmic1_nvm),
&dev);
@ -1373,7 +1373,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
memcpy(buffer, &data->pmic_part[offset], *size);
end_pmic_read:
pr_debug("%s: result %i\n", __func__, result);
log_debug("%s: result %i\n", __func__, result);
return result;
}
@ -1429,7 +1429,7 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part)
if (!fsbl)
return -ENOMEM;
ret = dfu->read_medium(dfu, 0, fsbl, &size);
pr_debug("%s read size=%lx ret=%d\n", __func__, size, ret);
log_debug("%s read size=%lx ret=%d\n", __func__, size, ret);
if (ret)
goto error;
@ -1439,8 +1439,8 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part)
offset += size;
/* write to the next erase block */
ret = dfu->write_medium(dfu, offset, fsbl, &size);
pr_debug("%s copy at ofset=%lx size=%lx ret=%d",
__func__, offset, size, ret);
log_debug("%s copy at ofset=%lx size=%lx ret=%d",
__func__, offset, size, ret);
if (ret)
goto error;
}
@ -1751,6 +1751,6 @@ void dfu_initiated_callback(struct dfu_entity *dfu)
if (dfu->alt == stm32prog_data->cur_part->alt_id) {
dfu->offset = stm32prog_data->offset;
stm32prog_data->dfu_seq = 0;
pr_debug("dfu offset = 0x%llx\n", dfu->offset);
log_debug("dfu offset = 0x%llx\n", dfu->offset);
}
}

2
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
View File

@ -172,7 +172,7 @@ char *stm32prog_get_error(struct stm32prog_data *data);
if (data->phase != PHASE_RESET) { \
sprintf(data->error, args); \
data->phase = PHASE_RESET; \
pr_err("Error: %s\n", data->error); } \
log_err("Error: %s\n", data->error); } \
}
/* Main function */

37
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
View File

@ -159,8 +159,8 @@ static int stm32prog_read(struct stm32prog_data *data, u8 phase, u32 offset,
dfu_entity->offset = offset;
data->offset = offset;
data->read_phase = phase;
pr_debug("\nSTM32 download read %s offset=0x%x\n",
dfu_entity->name, offset);
log_debug("\nSTM32 download read %s offset=0x%x\n",
dfu_entity->name, offset);
ret = dfu_read(dfu_entity, buffer, buffer_size,
dfu_entity->i_blk_seq_num);
if (ret < 0) {
@ -198,7 +198,7 @@ int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
sprintf(alias, "serial%d", link_dev);
path = fdt_get_alias(gd->fdt_blob, alias);
if (!path) {
pr_err("%s alias not found", alias);
log_err("%s alias not found", alias);
return -ENODEV;
}
node = fdt_path_offset(gd->fdt_blob, path);
@ -212,7 +212,7 @@ int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
down_serial_dev = dev;
}
if (!down_serial_dev) {
pr_err("%s = %s device not found", alias, path);
log_err("%s = %s device not found", alias, path);
return -ENODEV;
}
@ -225,11 +225,11 @@ int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
ops = serial_get_ops(down_serial_dev);
if (!ops) {
pr_err("%s = %s missing ops", alias, path);
log_err("%s = %s missing ops", alias, path);
return -ENODEV;
}
if (!ops->setconfig) {
pr_err("%s = %s missing setconfig", alias, path);
log_err("%s = %s missing setconfig", alias, path);
return -ENODEV;
}
@ -397,14 +397,13 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address)
if (!dfu_entity)
return -ENODEV;
if (data->dfu_seq) {
ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq);
data->dfu_seq = 0;
if (ret) {
stm32prog_err("DFU flush failed [%d]", ret);
return ret;
}
ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq);
if (ret) {
stm32prog_err("DFU flush failed [%d]", ret);
return ret;
}
data->dfu_seq = 0;
printf("\n received length = 0x%x\n", data->cursor);
if (data->header.present) {
if (data->cursor !=
@ -815,7 +814,7 @@ static void download_command(struct stm32prog_data *data)
if (data->cursor >
image_header->image_length + BL_HEADER_SIZE) {
pr_err("expected size exceeded\n");
log_err("expected size exceeded\n");
result = ABORT_BYTE;
goto end;
}
@ -859,8 +858,8 @@ static void read_partition_command(struct stm32prog_data *data)
rcv_data = stm32prog_serial_getc();
if (rcv_data != tmp_xor) {
pr_debug("1st checksum received = %x, computed %x\n",
rcv_data, tmp_xor);
log_debug("1st checksum received = %x, computed %x\n",
rcv_data, tmp_xor);
goto error;
}
stm32prog_serial_putc(ACK_BYTE);
@ -872,12 +871,12 @@ static void read_partition_command(struct stm32prog_data *data)
rcv_data = stm32prog_serial_getc();
if ((rcv_data ^ tmp_xor) != 0xFF) {
pr_debug("2nd checksum received = %x, computed %x\n",
rcv_data, tmp_xor);
log_debug("2nd checksum received = %x, computed %x\n",
rcv_data, tmp_xor);
goto error;
}
pr_debug("%s : %x\n", __func__, part_id);
log_debug("%s : %x\n", __func__, part_id);
rcv_data = 0;
switch (part_id) {
case PHASE_OTP:

14
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
View File

@ -47,11 +47,11 @@ static int stm32prog_cmd_write(u64 offset, void *buf, long *len)
int ret;
if (*len < 5) {
pr_err("size not allowed\n");
log_err("size not allowed\n");
return -EINVAL;
}
if (offset) {
pr_err("invalid offset\n");
log_err("invalid offset\n");
return -EINVAL;
}
phase = pt[0];
@ -66,7 +66,7 @@ static int stm32prog_cmd_write(u64 offset, void *buf, long *len)
/* set phase and offset */
ret = stm32prog_set_phase(stm32prog_data, phase, address);
if (ret)
pr_err("failed: %d\n", ret);
log_err("failed: %d\n", ret);
return ret;
}
@ -81,7 +81,7 @@ static int stm32prog_cmd_read(u64 offset, void *buf, long *len)
int length;
if (*len < PHASE_MIN_SIZE) {
pr_err("request exceeds allowed area\n");
log_err("request exceeds allowed area\n");
return -EINVAL;
}
if (offset) {
@ -171,8 +171,8 @@ int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
{
if (dfu->dev_type != DFU_DEV_VIRT) {
*size = 0;
pr_debug("%s, invalid dev_type = %d\n",
__func__, dfu->dev_type);
log_debug("%s, invalid dev_type = %d\n",
__func__, dfu->dev_type);
return -EINVAL;
}
@ -227,6 +227,6 @@ bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
int g_dnl_get_board_bcd_device_number(int gcnum)
{
pr_debug("%s\n", __func__);
log_debug("%s\n", __func__);
return 0x200;
}

18
arch/arm/mach-stm32mp/cpu.c
View File

@ -2,6 +2,9 @@
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
@ -463,8 +466,8 @@ static void setup_boot_mode(void)
struct udevice *dev;
int alias;
pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
__func__, boot_ctx, boot_mode, instance, forced_mode);
log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
__func__, boot_ctx, boot_mode, instance, forced_mode);
switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
case BOOT_SERIAL_UART:
if (instance > ARRAY_SIZE(serial_addr))
@ -510,7 +513,7 @@ static void setup_boot_mode(void)
env_set("boot_instance", "0");
break;
default:
pr_debug("unexpected boot mode = %x\n", boot_mode);
log_debug("unexpected boot mode = %x\n", boot_mode);
break;
}
@ -537,7 +540,7 @@ static void setup_boot_mode(void)
case BOOT_NORMAL:
break;
default:
pr_debug("unexpected forced boot mode = %x\n", forced_mode);
log_debug("unexpected forced boot mode = %x\n", forced_mode);
break;
}
@ -577,14 +580,13 @@ __weak int setup_mac_address(void)
enetaddr[i] = ((uint8_t *)&otp)[i];
if (!is_valid_ethaddr(enetaddr)) {
pr_err("invalid MAC address in OTP %pM\n", enetaddr);
log_err("invalid MAC address in OTP %pM\n", enetaddr);
return -EINVAL;
}
pr_debug("OTP MAC address = %pM\n", enetaddr);
log_debug("OTP MAC address = %pM\n", enetaddr);
ret = eth_env_set_enetaddr("ethaddr", enetaddr);
if (ret)
pr_err("Failed to set mac address %pM from OTP: %d\n",
enetaddr, ret);
log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
#endif
return 0;

8
arch/arm/mach-stm32mp/dram_init.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <dm.h>
#include <image.h>
@ -21,15 +23,15 @@ int dram_init(void)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("RAM init failed: %d\n", ret);
log_debug("RAM init failed: %d\n", ret);
return ret;
}
ret = ram_get_info(dev, &ram);
if (ret) {
debug("Cannot get RAM size: %d\n", ret);
log_debug("Cannot get RAM size: %d\n", ret);
return ret;
}
debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
gd->ram_size = ram.size;

17
arch/arm/mach-stm32mp/fdt.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <fdt_support.h>
#include <log.h>
@ -172,15 +174,15 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
status = (decprot[offset] >> shift) & DECPROT_MASK;
addr = array[i];
debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
if (addr == ETZPC_RESERVED ||
status == DECPROT_NON_SECURED)
continue;
if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
addr, i, status);
log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
addr, i, status);
}
return 0;
@ -194,7 +196,7 @@ static void stm32_fdt_fixup_cpu(void *blob, char *name)
off = fdt_path_offset(blob, "/cpus");
if (off < 0) {
printf("%s: couldn't find /cpus node\n", __func__);
log_warning("%s: couldn't find /cpus node\n", __func__);
return;
}
@ -203,7 +205,8 @@ static void stm32_fdt_fixup_cpu(void *blob, char *name)
reg = fdtdec_get_addr(blob, off, "reg");
if (reg != 0) {
fdt_del_node(blob, off);
printf("FDT: cpu %d node remove for %s\n", reg, name);
log_notice("FDT: cpu %d node remove for %s\n",
reg, name);
/* after delete we can't trust the offsets anymore */
off = -1;
}
@ -216,8 +219,8 @@ static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
const char *string, const char *name)
{
if (fdt_disable_subnode_by_address(fdt, offset, addr))
printf("FDT: %s@%08x node disabled for %s\n",
string, addr, name);
log_notice("FDT: %s@%08x node disabled for %s\n",
string, addr, name);
}
static void stm32_fdt_disable_optee(void *blob)

2
arch/arm/mach-stm32mp/pwr_regulator.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_REGULATOR
#include <common.h>
#include <dm.h>
#include <errno.h>

16
arch/arm/mach-stm32mp/spl.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
@ -80,7 +82,7 @@ void spl_display_print(void)
*/
model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
if (model)
printf("Model: %s\n", model);
log_info("Model: %s\n", model);
}
#endif
@ -98,25 +100,25 @@ void board_init_f(ulong dummy)
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
log_debug("spl_early_init() failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
debug("Clock init failed: %d\n", ret);
log_debug("Clock init failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_RESET, 0, &dev);
if (ret) {
debug("Reset init failed: %d\n", ret);
log_debug("Reset init failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
log_debug("%s: Cannot find pinctrl device\n", __func__);
hang();
}
@ -125,13 +127,13 @@ void board_init_f(ulong dummy)
ret = board_early_init_f();
if (ret) {
debug("board_early_init_f() failed: %d\n", ret);
log_debug("board_early_init_f() failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
log_err("DRAM init failed: %d\n", ret);
hang();
}

8
board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
View File

@ -47,28 +47,28 @@
config-1 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-pdk2_somrev0_boardrev0";
loadables = "uboot";
firmware = "uboot";
fdt = "fdt-1";
};
config-2 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-pdk2_somrev1_boardrev0";
loadables = "uboot";
firmware = "uboot";
fdt = "fdt-1";
};
config-3 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-drc02_somrev0_boardrev0";
loadables = "uboot";
firmware = "uboot";
fdt = "fdt-2";
};
config-4 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-drc02_somrev1_boardrev0";
loadables = "uboot";
firmware = "uboot";
fdt = "fdt-2";
};

2
board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
View File

@ -31,7 +31,7 @@
config-1 {
/* DT+SoM+board model */
description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
loadables = "uboot";
firmware = "uboot";
fdt = "fdt-1";
};

2
board/st/common/MAINTAINERS
View File

@ -1,5 +1,5 @@
ST BOARDS
M: Patrick Delaunay <patrick.delaunay@st.com>
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained

3
board/st/common/stm32mp_dfu.c
View File

@ -8,6 +8,7 @@
#include <dm.h>
#include <dfu.h>
#include <env.h>
#include <log.h>
#include <memalign.h>
#include <misc.h>
#include <mtd.h>
@ -199,7 +200,7 @@ static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
ret = 0;
}
#else
pr_err("PMIC update not supported");
log_err("PMIC update not supported");
ret = -EOPNOTSUPP;
#endif

5
board/st/common/stm32mp_mtdparts.c
View File

@ -8,6 +8,7 @@
#include <dm.h>
#include <env.h>
#include <env_internal.h>
#include <log.h>
#include <mtd.h>
#include <mtd_node.h>
#include <tee.h>
@ -117,7 +118,7 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts)
for (uclass_first_device(UCLASS_MTD, &dev);
dev;
uclass_next_device(&dev)) {
pr_debug("mtd device = %s\n", dev->name);
log_debug("mtd device = %s\n", dev->name);
}
if (nor || nand) {
@ -163,5 +164,5 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts)
mtd_initialized = true;
*mtdids = ids;
*mtdparts = parts;
debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
log_debug("mtdids=%s & mtdparts=%s\n", ids, parts);
}

5
board/st/common/stpmic1.c
View File

@ -3,8 +3,11 @@
* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_BOARD
#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <linux/bitops.h>
@ -202,7 +205,7 @@ void stpmic1_init(u32 voltage_mv)
/* Check if debug is enabled to program PMIC according to the bit */
if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
printf("Keep debug unit ON\n");
log_info("Keep debug unit ON\n");
pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
STPMIC1_MRST_BUCK_DEBUG,

2
board/st/common/stusb160x.c
View File

@ -6,6 +6,8 @@
* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_I2C_GENERIC
#include <common.h>
#include <dm.h>
#include <i2c.h>

2
board/st/stih410-b2260/MAINTAINERS
View File

@ -1,5 +1,5 @@
STIH410-B2260 BOARD
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stih410-b2260/
F: include/configs/stih410-b2260.h

2
board/st/stih410-b2260/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y = board.o

2
board/st/stm32f429-evaluation/MAINTAINERS
View File

@ -1,5 +1,5 @@
STM32F429-EVALUATION BOARD
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32f429-evaluation/
F: include/configs/stm32f429-evaluation.h

2
board/st/stm32f429-evaluation/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32f429-evaluation.o

2
board/st/stm32f469-discovery/MAINTAINERS
View File

@ -1,5 +1,5 @@
STM32F469-DISCOVERY BOARD
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32f469-discovery/
F: include/configs/stm32f469-discovery.h

2
board/st/stm32f469-discovery/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) STMicroelectronics SA 2017
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32f469-discovery.o

2
board/st/stm32h743-disco/MAINTAINERS
View File

@ -1,5 +1,5 @@
STM32H743 DISCOVERY BOARD
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32h743-disco
F: include/configs/stm32h743-disco.h

2
board/st/stm32h743-disco/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32h743-disco.o

2
board/st/stm32h743-eval/MAINTAINERS
View File

@ -1,5 +1,5 @@
STM32H743 EVALUATION BOARD
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32h743-eval
F: include/configs/stm32h743-eval.h

2
board/st/stm32h743-eval/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32h743-eval.o

2
board/st/stm32mp1/MAINTAINERS
View File

@ -1,5 +1,5 @@
STM32MP1 BOARD
M: Patrick Delaunay <patrick.delaunay@st.com>
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained

236
board/st/stm32mp1/stm32mp1.c
View File

@ -2,6 +2,9 @@
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_BOARD
#include <common.h>
#include <adc.h>
#include <bootm.h>
@ -106,12 +109,11 @@ int checkboard(void)
else
mode = "basic";
printf("Board: stm32mp1 in %s mode", mode);
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
&fdt_compat_len);
if (fdt_compat && fdt_compat_len)
printf(" (%s)", fdt_compat);
puts("\n");
log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
fdt_compat && fdt_compat_len ? fdt_compat : "");
/* display the STMicroelectronics board identification */
if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
@ -122,12 +124,12 @@ int checkboard(void)
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
&otp, sizeof(otp));
if (ret > 0 && otp)
printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
otp >> 16,
(otp >> 12) & 0xF,
(otp >> 4) & 0xF,
((otp >> 8) & 0xF) - 1 + 'A',
otp & 0xF);
log_info("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
otp >> 16,
(otp >> 12) & 0xF,
(otp >> 4) & 0xF,
((otp >> 8) & 0xF) - 1 + 'A',
otp & 0xF);
}
return 0;
@ -144,17 +146,16 @@ static void board_key_check(void)
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
debug("%s: no /config node?\n", __func__);
log_debug("no /config node?\n");
return;
}
if (IS_ENABLED(CONFIG_FASTBOOT)) {
if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
&gpio, GPIOD_IS_IN)) {
debug("%s: could not find a /config/st,fastboot-gpios\n",
__func__);
log_debug("could not find a /config/st,fastboot-gpios\n");
} else {
if (dm_gpio_get_value(&gpio)) {
puts("Fastboot key pressed, ");
log_notice("Fastboot key pressed, ");
boot_mode = BOOT_FASTBOOT;
}
@ -164,18 +165,17 @@ static void board_key_check(void)
if (IS_ENABLED(CONFIG_CMD_STM32PROG)) {
if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
&gpio, GPIOD_IS_IN)) {
debug("%s: could not find a /config/st,stm32prog-gpios\n",
__func__);
log_debug("could not find a /config/st,stm32prog-gpios\n");
} else {
if (dm_gpio_get_value(&gpio)) {
puts("STM32Programmer key pressed, ");
log_notice("STM32Programmer key pressed, ");
boot_mode = BOOT_STM32PROG;
}
dm_gpio_free(NULL, &gpio);
}
}
if (boot_mode != BOOT_NORMAL) {
puts("entering download mode...\n");
log_notice("entering download mode...\n");
clrsetbits_le32(TAMP_BOOT_CONTEXT,
TAMP_BOOT_FORCED_MASK,
boot_mode);
@ -198,8 +198,10 @@ int g_dnl_board_usb_cable_connected(void)
ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
DM_DRIVER_GET(dwc2_udc_otg),
&dwc2_udc_otg);
if (!ret)
debug("dwc2_udc_otg init failed\n");
if (ret) {
log_debug("dwc2_udc_otg init failed\n");
return ret;
}
return dwc2_udc_B_session_valid(dwc2_udc_otg);
}
@ -231,13 +233,12 @@ static int get_led(struct udevice **dev, char *led_string)
led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
if (!led_name) {
pr_debug("%s: could not find %s config string\n",
__func__, led_string);
log_debug("could not find %s config string\n", led_string);
return -ENOENT;
}
ret = led_get_by_label(led_name, dev);
if (ret) {
debug("%s: get=%d\n", __func__, ret);
log_debug("get=%d\n", ret);
return ret;
}
@ -288,24 +289,66 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
hang();
}
static int board_check_usb_power(void)
static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV)
{
struct ofnode_phandle_args adc_args;
struct udevice *adc;
ofnode node;
unsigned int raw;
int ret, uV;
int i;
for (i = 0; i < adc_count; i++) {
if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
"#io-channel-cells", 0, i,
&adc_args)) {
log_debug("can't find /config/st,adc_usb_pd\n");
return 0;
}
ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
&adc);
if (ret) {
log_err("Can't get adc device(%d)\n", ret);
return ret;
}
ret = adc_channel_single_shot(adc->name, adc_args.args[0],
&raw);
if (ret) {
log_err("single shot failed for %s[%d]!\n",
adc->name, adc_args.args[0]);
return ret;
}
/* Convert to uV */
if (!adc_raw_to_uV(adc, raw, &uV)) {
if (uV > *max_uV)
*max_uV = uV;
if (uV < *min_uV)
*min_uV = uV;
log_debug("%s[%02d] = %u, %d uV\n",
adc->name, adc_args.args[0], raw, uV);
} else {
log_err("Can't get uV value for %s[%d]\n",
adc->name, adc_args.args[0]);
}
}
return 0;
}
static int board_check_usb_power(void)
{
ofnode node;
int max_uV = 0;
int min_uV = USB_START_HIGH_THRESHOLD_UV;
int ret, uV, adc_count;
int adc_count, ret;
u32 nb_blink;
u8 i;
if (!IS_ENABLED(CONFIG_ADC))
return -ENODEV;
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
debug("%s: no /config node?\n", __func__);
log_debug("no /config node?\n");
return -ENOENT;
}
@ -319,63 +362,38 @@ static int board_check_usb_power(void)
if (adc_count == -ENOENT)
return 0;
pr_err("%s: can't find adc channel (%d)\n", __func__,
adc_count);
log_err("Can't find adc channel (%d)\n", adc_count);
return adc_count;
}
for (i = 0; i < adc_count; i++) {
if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
"#io-channel-cells", 0, i,
&adc_args)) {
pr_debug("%s: can't find /config/st,adc_usb_pd\n",
__func__);
/* perform maximum of 2 ADC measurements to detect power supply current */
for (i = 0; i < 2; i++) {
if (IS_ENABLED(CONFIG_ADC))
ret = adc_measurement(node, adc_count, &min_uV, &max_uV);
else
ret = -ENODEV;
if (ret)
return ret;
/*
* If highest value is inside 1.23 Volts and 2.10 Volts, that means
* board is plugged on an USB-C 3A power supply and boot process can
* continue.
*/
if (max_uV > USB_START_LOW_THRESHOLD_UV &&
max_uV <= USB_START_HIGH_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV)
return 0;
}
ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
&adc);
if (ret) {
pr_err("%s: Can't get adc device(%d)\n", __func__,
ret);
return ret;
}
ret = adc_channel_single_shot(adc->name, adc_args.args[0],
&raw);
if (ret) {
pr_err("%s: single shot failed for %s[%d]!\n",
__func__, adc->name, adc_args.args[0]);
return ret;
}
/* Convert to uV */
if (!adc_raw_to_uV(adc, raw, &uV)) {
if (uV > max_uV)
max_uV = uV;
if (uV < min_uV)
min_uV = uV;
pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
adc->name, adc_args.args[0], raw, uV);
} else {
pr_err("%s: Can't get uV value for %s[%d]\n",
__func__, adc->name, adc_args.args[0]);
if (i == 0) {
log_err("Previous ADC measurements was not the one expected, retry in 20ms\n");
mdelay(20); /* equal to max tPDDebounce duration (min 10ms - max 20ms) */
}
}
/*
* If highest value is inside 1.23 Volts and 2.10 Volts, that means
* board is plugged on an USB-C 3A power supply and boot process can
* continue.
*/
if (max_uV > USB_START_LOW_THRESHOLD_UV &&
max_uV <= USB_START_HIGH_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV)
return 0;
pr_err("****************************************************\n");
log_notice("****************************************************\n");
/*
* If highest and lowest value are either both below
* USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
@ -386,8 +404,8 @@ static int board_check_usb_power(void)
min_uV > USB_LOW_THRESHOLD_UV) ||
(max_uV <= USB_LOW_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV)) {
pr_err("* ERROR USB TYPE-C connection in unattached mode *\n");
pr_err("* Check that USB TYPE-C cable is correctly plugged *\n");
log_notice("* ERROR USB TYPE-C connection in unattached mode *\n");
log_notice("* Check that USB TYPE-C cable is correctly plugged *\n");
/* with 125ms interval, led will blink for 17.02 years ....*/
nb_blink = U32_MAX;
}
@ -395,14 +413,14 @@ static int board_check_usb_power(void)
if (max_uV > USB_LOW_THRESHOLD_UV &&
max_uV <= USB_WARNING_LOW_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV) {
pr_err("* WARNING 500mA power supply detected *\n");
log_notice("* WARNING 500mA power supply detected *\n");
nb_blink = 2;
}
if (max_uV > USB_WARNING_LOW_THRESHOLD_UV &&
max_uV <= USB_START_LOW_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV) {
pr_err("* WARNING 1.5A power supply detected *\n");
log_notice("* WARNING 1.5A power supply detected *\n");
nb_blink = 3;
}
@ -411,14 +429,14 @@ static int board_check_usb_power(void)
* supplies more than 3 Amp, this is not compliant with TypeC specification
*/
if (max_uV > USB_START_HIGH_THRESHOLD_UV) {
pr_err("* USB TYPE-C charger not compliant with *\n");
pr_err("* specification *\n");
pr_err("****************************************************\n\n");
log_notice("* USB TYPE-C charger not compliant with *\n");
log_notice("* specification *\n");
log_notice("****************************************************\n\n");
/* with 125ms interval, led will blink for 17.02 years ....*/
nb_blink = U32_MAX;
} else {
pr_err("* Current too low, use a 3A power supply! *\n");
pr_err("****************************************************\n\n");
log_notice("* Current too low, use a 3A power supply! *\n");
log_notice("****************************************************\n\n");
}
led_error_blink(nb_blink);
@ -471,7 +489,7 @@ static void sysconf_init(void)
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
pr_err("Can't find stm32mp_bsec driver\n");
log_err("Can't find stm32mp_bsec driver\n");
return;
}
@ -494,13 +512,13 @@ static void sysconf_init(void)
syscfg + SYSCFG_IOCTRLSETR);
if (!otp)
pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
log_err("product_below_2v5=0: HSLVEN protected by HW\n");
} else {
if (otp)
pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
log_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
}
} else {
debug("VDD unknown");
log_debug("VDD unknown");
}
}
@ -514,7 +532,7 @@ static void sysconf_init(void)
val & SYSCFG_CMPCR_READY,
1000000);
if (ret) {
pr_err("SYSCFG: I/O compensation failed, timeout.\n");
log_err("SYSCFG: I/O compensation failed, timeout.\n");
led_error_blink(10);
}
@ -533,39 +551,37 @@ static int dk2_i2c1_fix(void)
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
if (!ofnode_valid(node)) {
pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__);
log_debug("no hdmi-transmitter@39 ?\n");
return -ENOENT;
}
if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
&hdmi, GPIOD_IS_OUT)) {
pr_debug("%s: could not find reset-gpios\n",
__func__);
log_debug("could not find reset-gpios\n");
return -ENOENT;
}
node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
if (!ofnode_valid(node)) {
pr_debug("%s: no cs42l51@4a ?\n", __func__);
log_debug("no cs42l51@4a ?\n");
return -ENOENT;
}
if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
&audio, GPIOD_IS_OUT)) {
pr_debug("%s: could not find reset-gpios\n",
__func__);
log_debug("could not find reset-gpios\n");
return -ENOENT;
}
/* before power up, insure that HDMI and AUDIO IC is under reset */
ret = dm_gpio_set_value(&hdmi, 1);
if (ret) {
pr_err("%s: can't set_value for hdmi_nrst gpio", __func__);
log_err("can't set_value for hdmi_nrst gpio");
goto error;
}
ret = dm_gpio_set_value(&audio, 1);
if (ret) {
pr_err("%s: can't set_value for audio_nrst gpio", __func__);
log_err("can't set_value for audio_nrst gpio");
goto error;
}
@ -732,7 +748,7 @@ int board_interface_eth_init(struct udevice *dev,
case PHY_INTERFACE_MODE_MII:
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
log_debug("PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_GMII:
if (eth_clk_sel_reg)
@ -740,7 +756,7 @@ int board_interface_eth_init(struct udevice *dev,
SYSCFG_PMCSETR_ETH_CLK_SEL;
else
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
log_debug("PHY_INTERFACE_MODE_GMII\n");
break;
case PHY_INTERFACE_MODE_RMII:
if (eth_ref_clk_sel_reg)
@ -748,7 +764,7 @@ int board_interface_eth_init(struct udevice *dev,
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
else
value = SYSCFG_PMCSETR_ETH_SEL_RMII;
debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
log_debug("PHY_INTERFACE_MODE_RMII\n");
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
@ -759,11 +775,11 @@ int board_interface_eth_init(struct udevice *dev,
SYSCFG_PMCSETR_ETH_CLK_SEL;
else
value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
log_debug("PHY_INTERFACE_MODE_RGMII\n");
break;
default:
debug("%s: Do not manage %d interface\n",
__func__, interface_type);
log_debug("Do not manage %d interface\n",
interface_type);
/* Do not manage others interfaces */
return -EINVAL;
}
@ -878,14 +894,14 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size)
if (!rproc_is_initialized())
if (rproc_init()) {
printf("Remote Processor %d initialization failed\n",
id);
log_err("Remote Processor %d initialization failed\n",
id);
return;
}
ret = rproc_load(id, fw_image, fw_size);
printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
id, fw_image, fw_size, ret ? " Failed!" : " Success!");
log_err("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
id, fw_image, fw_size, ret ? " Failed!" : " Success!");
if (!ret)
rproc_start(id);

3
configs/stm32mp15_basic_defconfig
View File

@ -21,6 +21,7 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SPL_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
@ -54,8 +55,10 @@ CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y

2
configs/stm32mp15_trusted_defconfig
View File

@ -38,7 +38,9 @@ CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y

2
doc/board/st/stm32mp1.rst
View File

@ -1,5 +1,5 @@
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
.. sectionauthor:: Patrick Delaunay <patrick.delaunay@st.com>
.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
STM32MP15x boards
=================

2
doc/driver-model/bind.rst
View File

@ -1,5 +1,5 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Patrice Chotard <patrice.chotard@st.com>
.. sectionauthor:: Patrice Chotard <patrice.chotard@foss.st.com>
Binding/unbinding a driver
==========================

39
drivers/clk/clk_stm32f.c
View File

@ -4,18 +4,19 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_CLK
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
#include <stm32_rcc.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_pwr.h>
#include <dm/device_compat.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
#include <linux/bitops.h>
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSEON BIT(16)
@ -309,7 +310,7 @@ static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
>> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
break;
default:
pr_err("incorrect PLLSAI output %d\n", output);
log_err("incorrect PLLSAI output %d\n", output);
return -EINVAL;
}
@ -490,7 +491,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
return (sysclk >> stm32_get_apb_shift(regs, APB2));
default:
pr_err("clock index %ld out of range\n", clk->id);
dev_err(clk->dev, "clock index %ld out of range\n", clk->id);
return -EINVAL;
}
}
@ -509,8 +510,9 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
/* Only set_rate for LTDC clock is implemented */
if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
pr_err("set_rate not implemented for clock index %ld\n",
clk->id);
dev_err(clk->dev,
"set_rate not implemented for clock index %ld\n",
clk->id);
return 0;
}
@ -604,8 +606,8 @@ static int stm32_clk_enable(struct clk *clk)
u32 offset = clk->id / 32;
u32 bit_index = clk->id % 32;
debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
__func__, clk->id, offset, bit_index);
dev_dbg(clk->dev, "clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
clk->id, offset, bit_index);
setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
return 0;
@ -618,7 +620,7 @@ static int stm32_clk_probe(struct udevice *dev)
struct clk clk;
int err;
debug("%s\n", __func__);
dev_dbg(dev, "%s\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
fdt_addr_t addr;
@ -652,14 +654,14 @@ static int stm32_clk_probe(struct udevice *dev)
&fixed_clock_dev);
if (err) {
pr_err("Can't find fixed clock (%d)", err);
dev_err(dev, "Can't find fixed clock (%d)", err);
return err;
}
err = clk_request(fixed_clock_dev, &clk);
if (err) {
pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
err);
dev_err(dev, "Can't request %s clk (%d)",
fixed_clock_dev->name, err);
return err;
}
@ -673,8 +675,8 @@ static int stm32_clk_probe(struct udevice *dev)
priv->hse_rate = clk_get_rate(&clk);
if (priv->hse_rate < 1000000) {
pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
priv->hse_rate);
dev_err(dev, "unexpected HSE clock rate = %ld \"n",
priv->hse_rate);
return -EINVAL;
}
@ -684,8 +686,7 @@ static int stm32_clk_probe(struct udevice *dev)
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (err) {
debug("%s: can't find syscon device (%d)\n", __func__,
err);
dev_err(dev, "can't find syscon device (%d)\n", err);
return err;
}
@ -699,10 +700,10 @@ static int stm32_clk_probe(struct udevice *dev)
static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
debug("%s(clk=%p)\n", __func__, clk);
dev_dbg(clk->dev, "clk=%p\n", clk);
if (args->args_count != 2) {
debug("Invaild args_count: %d\n", args->args_count);
dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}

70
drivers/clk/clk_stm32h7.c
View File

@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_CLK
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
@ -11,6 +13,7 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/root.h>
#include <linux/bitops.h>
@ -465,18 +468,18 @@ static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
int ret;
const char *name = pllsrc_name[pllsrc];
debug("%s name %s\n", __func__, name);
log_debug("pllsrc name %s\n", name);
clk.id = 0;
ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
if (ret) {
pr_err("Can't find clk %s (%d)", name, ret);
log_err("Can't find clk %s (%d)", name, ret);
return 0;
}
ret = clk_request(fixed_clock_dev, &clk);
if (ret) {
pr_err("Can't request %s clk (%d)", name, ret);
log_err("Can't request %s clk (%d)", name, ret);
return 0;
}
@ -484,8 +487,7 @@ static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
if (pllsrc == HSI)
divider = stm32_get_HSI_divider(regs);
debug("%s divider %d rate %ld\n", __func__,
divider, clk_get_rate(&clk));
log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk));
return clk_get_rate(&clk) >> divider;
};
@ -516,7 +518,7 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
break;
case RCC_PLLCKSELR_PLLSRC_NO_CLK:
/* shouldn't happen */
pr_err("wrong value for RCC_PLLCKSELR register\n");
log_err("wrong value for RCC_PLLCKSELR register\n");
pllsrc = 0;
break;
}
@ -546,10 +548,10 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
vco = (pllsrc / divm1) * divn1;
rate = (pllsrc * fracn1) / (divm1 * 8192);
debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
__func__, divm1, divn1, divp1, divq1, divr1);
debug("%s fracn1 = %d vco = %ld rate = %ld\n",
__func__, fracn1, vco, rate);
log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
divm1, divn1, divp1, divq1, divr1);
log_debug("fracn1 = %d vco = %ld rate = %ld\n",
fracn1, vco, rate);
switch (output) {
case PLL1_P_CK:
@ -610,7 +612,7 @@ u32 psc = stm32_get_apb_psc(regs, apb);
case 16:
return sysclk / 4;
default:
pr_err("unexpected prescaler value (%d)\n", psc);
log_err("unexpected prescaler value (%d)\n", psc);
return 0;
}
else
@ -623,7 +625,7 @@ u32 psc = stm32_get_apb_psc(regs, apb);
case 16:
return sysclk / psc;
default:
pr_err("unexpected prescaler value (%d)\n", psc);
log_err("unexpected prescaler value (%d)\n", psc);
return 0;
}
};
@ -665,8 +667,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
if (!sysclk)
return sysclk;
debug("%s system clock: source = %d freq = %ld\n",
__func__, source, sysclk);
dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n",
source, sysclk);
d1cfgr = readl(&regs->d1cfgr);
@ -685,8 +687,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
gate_offset = clk_map[clk->id].gate_offset;
debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
__func__, clk->id, gate_offset, sysclk);
dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
clk->id, gate_offset, sysclk);
switch (gate_offset) {
case RCC_AHB3ENR:
@ -704,8 +706,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
sysclk = sysclk / prescaler_table[idx];
}
debug("%s system clock: freq after APB3 prescaler = %ld\n",
__func__, sysclk);
dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n",
sysclk);
return sysclk;
break;
@ -719,8 +721,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)
sysclk = sysclk / prescaler_table[idx];
}
debug("%s system clock: freq after APB4 prescaler = %ld\n",
__func__, sysclk);
dev_dbg(clk->dev,
"system clock: freq after APB4 prescaler = %ld\n",
sysclk);
return sysclk;
break;
@ -741,8 +744,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)
return stm32_get_timer_rate(priv, sysclk, APB1);
}
debug("%s system clock: freq after APB1 prescaler = %ld\n",
__func__, sysclk);
dev_dbg(clk->dev,
"system clock: freq after APB1 prescaler = %ld\n",
sysclk);
return (sysclk / stm32_get_apb_psc(regs, APB1));
break;
@ -758,15 +762,17 @@ static ulong stm32_clk_get_rate(struct clk *clk)
return stm32_get_timer_rate(priv, sysclk, APB2);
}
debug("%s system clock: freq after APB2 prescaler = %ld\n",
__func__, sysclk);
dev_dbg(clk->dev,
"system clock: freq after APB2 prescaler = %ld\n",
sysclk);
return (sysclk / stm32_get_apb_psc(regs, APB2));
break;
default:
pr_err("unexpected gate_offset value (0x%x)\n", gate_offset);
dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n",
gate_offset);
return -EINVAL;
break;
}
@ -783,9 +789,9 @@ static int stm32_clk_enable(struct clk *clk)
gate_offset = clk_map[clk_id].gate_offset;
gate_bit_index = clk_map[clk_id].gate_bit_idx;
debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
__func__, clk->id, gate_offset, gate_bit_index,
clk_map[clk_id].name);
dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
clk->id, gate_offset, gate_bit_index,
clk_map[clk_id].name);
setbits_le32(&regs->cr + (gate_offset / 4), BIT(gate_bit_index));
@ -810,13 +816,13 @@ static int stm32_clk_probe(struct udevice *dev)
"st,syscfg", &syscon);
if (err) {
pr_err("unable to find syscon device\n");
dev_err(dev, "unable to find syscon device\n");
return err;
}
priv->pwr_regmap = syscon_get_regmap(syscon);
if (!priv->pwr_regmap) {
pr_err("unable to find regmap\n");
dev_err(dev, "unable to find regmap\n");
return -ENODEV;
}
@ -829,7 +835,7 @@ static int stm32_clk_of_xlate(struct clk *clk,
struct ofnode_phandle_args *args)
{
if (args->args_count != 1) {
debug("Invaild args_count: %d\n", args->args_count);
dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
@ -852,7 +858,7 @@ static int stm32_clk_of_xlate(struct clk *clk,
clk->id = 0;
}
debug("%s clk->id %ld\n", __func__, clk->id);
dev_dbg(clk->dev, "clk->id %ld\n", clk->id);
return 0;
}

147
drivers/clk/clk_stm32mp1.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_CLK
#include <common.h>
#include <clk-uclass.h>
#include <div64.h>
@ -14,12 +16,13 @@
#include <syscon.h>
#include <time.h>
#include <vsprintf.h>
#include <asm/arch/sys_proto.h>
#include <dm/device_compat.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <asm/arch/sys_proto.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
DECLARE_GLOBAL_DATA_PTR;
@ -781,7 +784,7 @@ static const struct stm32mp1_clk_data stm32mp1_data = {
static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
{
if (idx >= NB_OSC) {
debug("%s: clk id %d not found\n", __func__, idx);
log_debug("clk id %d not found\n", idx);
return 0;
}
@ -799,7 +802,7 @@ static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
}
if (i == nb_clks) {
printf("%s: clk id %d not found\n", __func__, (u32)id);
log_err("clk id %d not found\n", (u32)id);
return -EINVAL;
}
@ -812,8 +815,7 @@ static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
const struct stm32mp1_clk_gate *gate = priv->data->gate;
if (gate[i].sel > _PARENT_SEL_NB) {
printf("%s: parents for clk id %d not found\n",
__func__, i);
log_err("parents for clk id %d not found\n", i);
return -EINVAL;
}
@ -858,17 +860,14 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
if (p < sel[s].nb_parent) {
#ifdef DEBUG
debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
stm32mp1_clk_parent_name[sel[s].parent[p]],
stm32mp1_clk_parent_sel_name[s],
(u32)id);
#endif
log_content("%s clock is the parent %s of clk id %d\n",
stm32mp1_clk_parent_name[sel[s].parent[p]],
stm32mp1_clk_parent_sel_name[s],
(u32)id);
return sel[s].parent[p];
}
pr_err("%s: no parents defined for clk id %d\n",
__func__, (u32)id);
log_err("no parents defined for clk id %d\n", (u32)id);
return -EINVAL;
}
@ -1124,7 +1123,7 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
&dev)) {
if (clk_request(dev, &clk)) {
pr_err("ck_dsi_phy request");
log_err("ck_dsi_phy request");
} else {
clk.id = 0;
clock = clk_get_rate(&clk);
@ -1136,8 +1135,7 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
break;
}
debug("%s(%d) clock = %lx : %ld kHz\n",
__func__, p, clock, clock / 1000);
log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
return clock;
}
@ -1156,7 +1154,7 @@ static int stm32mp1_clk_enable(struct clk *clk)
else
setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
return 0;
}
@ -1177,7 +1175,7 @@ static int stm32mp1_clk_disable(struct clk *clk)
else
clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
return 0;
}
@ -1193,10 +1191,9 @@ static ulong stm32mp1_clk_get_rate(struct clk *clk)
rate = stm32mp1_clk_get(priv, p);
#ifdef DEBUG
debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
__func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
#endif
dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
(u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
return rate;
}
@ -1335,7 +1332,7 @@ static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
if (ret) {
debug("PLL1 OPP configuration not found (%d).\n", ret);
log_debug("PLL1 OPP configuration not found (%d).\n", ret);
return ret;
}
@ -1440,8 +1437,8 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
TIMEOUT_1S);
if (ret)
pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
mask_rdy, address, enable, readl(address));
log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
mask_rdy, address, enable, readl(address));
return ret;
}
@ -1529,8 +1526,8 @@ static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
val & RCC_OCRDYR_HSIDIVRDY,
TIMEOUT_200MS);
if (ret)
pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
address, readl(address));
log_err("HSIDIV failed @ 0x%x: 0x%x\n",
address, readl(address));
return ret;
}
@ -1546,7 +1543,7 @@ static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
break;
if (hsidiv == 4) {
pr_err("clk-hsi frequency invalid");
log_err("clk-hsi frequency invalid");
return -1;
}
@ -1577,8 +1574,8 @@ static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
TIMEOUT_200MS);
if (ret) {
pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
pll_id, pllxcr, readl(pllxcr));
log_err("PLL%d start failed @ 0x%x: 0x%x\n",
pll_id, pllxcr, readl(pllxcr));
return ret;
}
@ -1640,7 +1637,7 @@ static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
debug("invalid refclk = %x\n", (u32)refclk);
log_err("invalid refclk = %x\n", (u32)refclk);
return -EINVAL;
}
if (type == PLL_800 && refclk >= 8000000)
@ -1736,7 +1733,7 @@ static __maybe_unused int pll_set_rate(struct udevice *dev,
divn = (value >> 13) - 1;
if (divn < DIVN_MIN ||
divn > stm32mp1_pll[type].divn_max) {
pr_err("divn invalid = %d", divn);
dev_err(dev, "divn invalid = %d", divn);
return -EINVAL;
}
fracv = value - ((divn + 1) << 13);
@ -1761,8 +1758,8 @@ static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
TIMEOUT_200MS);
if (ret)
pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
clksrc, address, readl(address));
log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
clksrc, address, readl(address));
return ret;
}
@ -1781,7 +1778,7 @@ static void stgen_config(struct stm32mp1_clk_priv *priv)
if (cntfid0 != rate) {
u64 counter;
pr_debug("System Generic Counter (STGEN) update\n");
log_debug("System Generic Counter (STGEN) update\n");
clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
counter = (u64)readl(stgenc + STGENC_CNTCVL);
counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
@ -1807,8 +1804,8 @@ static int set_clkdiv(unsigned int clkdiv, u32 address)
ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
TIMEOUT_200MS);
if (ret)
pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
clkdiv, address, readl(address));
log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
clkdiv, address, readl(address));
return ret;
}
@ -1891,13 +1888,13 @@ static int stm32mp1_clktree(struct udevice *dev)
/* check mandatory field */
ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
if (ret < 0) {
debug("field st,clksrc invalid: error %d\n", ret);
dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
if (ret < 0) {
debug("field st,clkdiv invalid: error %d\n", ret);
dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
@ -1911,11 +1908,11 @@ static int stm32mp1_clktree(struct udevice *dev)
pllcfg_valid[i] = ofnode_valid(node);
pllcsg_set[i] = false;
if (pllcfg_valid[i]) {
debug("DT for PLL %d @ %s\n", i, name);
dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
ret = ofnode_read_u32_array(node, "cfg",
pllcfg[i], PLLCFG_NB);
if (ret < 0) {
debug("field cfg invalid: error %d\n", ret);
dev_dbg(dev, "field cfg invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
@ -1925,30 +1922,30 @@ static int stm32mp1_clktree(struct udevice *dev)
if (!ret) {
pllcsg_set[i] = true;
} else if (ret != -FDT_ERR_NOTFOUND) {
debug("invalid csg node for pll@%d res=%d\n",
i, ret);
dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
i, ret);
return ret;
}
} else if (i == _PLL1) {
/* use OPP for PLL1 for A7 CPU */
debug("DT for PLL %d with OPP\n", i);
dev_dbg(dev, "DT for PLL %d with OPP\n", i);
ret = stm32mp1_pll1_opp(priv,
clksrc[CLKSRC_PLL12],
pllcfg[i],
&pllfracv[i]);
if (ret) {
debug("PLL %d with OPP error = %d\n", i, ret);
dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
return ret;
}
pllcfg_valid[i] = true;
}
}
debug("configuration MCO\n");
dev_dbg(dev, "configuration MCO\n");
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
debug("switch ON osillator\n");
dev_dbg(dev, "switch ON osillator\n");
/*
* switch ON oscillator found in device-tree,
* HSI already ON after bootrom
@ -1986,24 +1983,24 @@ static int stm32mp1_clktree(struct udevice *dev)
stm32mp1_csi_set(rcc, 1);
/* come back to HSI */
debug("come back to HSI\n");
dev_dbg(dev, "come back to HSI\n");
set_clksrc(priv, CLK_MPU_HSI);
set_clksrc(priv, CLK_AXI_HSI);
set_clksrc(priv, CLK_MCU_HSI);
debug("pll stop\n");
dev_dbg(dev, "pll stop\n");
for (i = 0; i < _PLL_NB; i++)
pll_stop(priv, i);
/* configure HSIDIV */
debug("configure HSIDIV\n");
dev_dbg(dev, "configure HSIDIV\n");
if (priv->osc[_HSI]) {
stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
stgen_config(priv);
}
/* select DIV */
debug("select DIV\n");
dev_dbg(dev, "select DIV\n");
/* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
@ -2018,17 +2015,17 @@ static int stm32mp1_clktree(struct udevice *dev)
writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
/* configure PLLs source */
debug("configure PLLs source\n");
dev_dbg(dev, "configure PLLs source\n");
set_clksrc(priv, clksrc[CLKSRC_PLL12]);
set_clksrc(priv, clksrc[CLKSRC_PLL3]);
set_clksrc(priv, clksrc[CLKSRC_PLL4]);
/* configure and start PLLs */
debug("configure PLLs\n");
dev_dbg(dev, "configure PLLs\n");
for (i = 0; i < _PLL_NB; i++) {
if (!pllcfg_valid[i])
continue;
debug("configure PLL %d\n", i);
dev_dbg(dev, "configure PLL %d\n", i);
pll_config(priv, i, pllcfg[i], pllfracv[i]);
if (pllcsg_set[i])
pll_csg(priv, i, pllcsg[i]);
@ -2039,7 +2036,7 @@ static int stm32mp1_clktree(struct udevice *dev)
for (i = 0; i < _PLL_NB; i++) {
if (!pllcfg_valid[i])
continue;
debug("output PLL %d\n", i);
dev_dbg(dev, "output PLL %d\n", i);
pll_output(priv, i, pllcfg[i][PLLCFG_O]);
}
@ -2048,14 +2045,14 @@ static int stm32mp1_clktree(struct udevice *dev)
stm32mp1_lse_wait(rcc);
/* configure with expected clock source */
debug("CLKSRC\n");
dev_dbg(dev, "CLKSRC\n");
set_clksrc(priv, clksrc[CLKSRC_MPU]);
set_clksrc(priv, clksrc[CLKSRC_AXI]);
set_clksrc(priv, clksrc[CLKSRC_MCU]);
set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
/* configure PKCK */
debug("PKCK\n");
dev_dbg(dev, "PKCK\n");
pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
if (pkcs_cell) {
bool ckper_disabled = false;
@ -2081,7 +2078,7 @@ static int stm32mp1_clktree(struct udevice *dev)
/* STGEN clock source can change with CLK_STGEN_XXX */
stgen_config(priv);
debug("oscillator off\n");
dev_dbg(dev, "oscillator off\n");
/* switch OFF HSI if not found in device-tree */
if (!priv->osc[_HSI])
stm32mp1_hsi_set(rcc, 0);
@ -2147,14 +2144,12 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
case DSI_PX:
break;
default:
pr_err("not supported");
dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
return -EINVAL;
}
p = stm32mp1_clk_get_parent(priv, clk->id);
#ifdef DEBUG
debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
#endif
dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
if (p < 0)
return -EINVAL;
@ -2192,7 +2187,7 @@ static void stm32mp1_osc_clk_init(const char *name,
clk.id = 0;
if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
if (clk_request(dev, &clk))
pr_err("%s request", name);
log_err("%s request", name);
else
priv->osc[index] = clk_get_rate(&clk);
}
@ -2214,7 +2209,7 @@ static void stm32mp1_osc_init(struct udevice *dev)
for (i = 0; i < NB_OSC; i++) {
stm32mp1_osc_clk_init(name[i], priv, i);
debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
}
}
@ -2288,11 +2283,11 @@ static int stm32mp1_clk_probe(struct udevice *dev)
if (!(gd->flags & GD_FLG_RELOC))
result = stm32mp1_clktree(dev);
if (result)
printf("clock tree initialization failed (%d)\n", result);
dev_err(dev, "clock tree initialization failed (%d)\n", result);
#endif
#ifndef CONFIG_SPL_BUILD
#if defined(DEBUG)
#if defined(VERBOSE_DEBUG)
/* display debug information for probe after relocation */
if (gd->flags & GD_FLG_RELOC)
stm32mp1_clk_dump(priv);
@ -2306,14 +2301,14 @@ static int stm32mp1_clk_probe(struct udevice *dev)
if (gd->flags & GD_FLG_RELOC) {
char buf[32];
printf("Clocks:\n");
printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
printf("- MCU : %s MHz\n",
strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
printf("- PER : %s MHz\n",
strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
log_info("Clocks:\n");
log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
log_info("- MCU : %s MHz\n",
strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
log_info("- PER : %s MHz\n",
strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#endif

4
drivers/gpio/stm32_gpio.c
View File

@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_GPIO
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -331,7 +333,7 @@ static int gpio_stm32_probe(struct udevice *dev)
dev_err(dev, "failed to enable clock\n");
return ret;
}
debug("clock enabled for device %s\n", dev->name);
dev_dbg(dev, "clock enabled\n");
return 0;
}

2
drivers/hwspinlock/stm32_hwspinlock.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_HWSPINLOCK
#include <common.h>
#include <clk.h>
#include <dm.h>

74
drivers/i2c/stm32f7_i2c.c
View File

@ -3,6 +3,8 @@
* (C) Copyright 2017 STMicroelectronics
*/
#define LOG_CATEGORY UCLASS_I2C
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -11,10 +13,10 @@
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
#include <dm/device.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <dm/device.h>
#include <linux/err.h>
#include <linux/io.h>
@ -346,7 +348,7 @@ static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
*status = readl(&regs->isr);
while (!(*status & flags)) {
if (get_timer(time_start) > CONFIG_SYS_HZ) {
debug("%s: i2c timeout\n", __func__);
log_debug("i2c timeout\n");
return -ETIMEDOUT;
}
@ -369,7 +371,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
return ret;
if (status & STM32_I2C_ISR_BERR) {
debug("%s: Bus error\n", __func__);
log_debug("Bus error\n");
/* Clear BERR flag */
setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
@ -378,7 +380,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
}
if (status & STM32_I2C_ISR_ARLO) {
debug("%s: Arbitration lost\n", __func__);
log_debug("Arbitration lost\n");
/* Clear ARLO flag */
setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
@ -387,7 +389,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
}
if (status & STM32_I2C_ISR_NACKF) {
debug("%s: Receive NACK\n", __func__);
log_debug("Receive NACK\n");
/* Clear NACK flag */
setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
@ -535,8 +537,8 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
if (sdadel_max < 0)
sdadel_max = 0;
debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
sdadel_min, sdadel_max, scldel_min);
log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
sdadel_min, sdadel_max, scldel_min);
/* Compute possible values for PRESC, SCLDEL and SDADEL */
for (p = 0; p < STM32_PRESC_MAX; p++) {
@ -572,7 +574,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
}
if (list_empty(solutions)) {
pr_err("%s: no Prescaler solution\n", __func__);
log_err("no Prescaler solution\n");
ret = -EPERM;
}
@ -656,7 +658,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
}
if (!sol_found) {
pr_err("%s: no solution at all\n", __func__);
log_err("no solution at all\n");
ret = -EPERM;
}
@ -686,23 +688,22 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
specs = get_specs(setup->speed_freq);
if (specs == ERR_PTR(-EINVAL)) {
pr_err("%s: speed out of bound {%d}\n", __func__,
setup->speed_freq);
log_err("speed out of bound {%d}\n",
setup->speed_freq);
return -EINVAL;
}
if (setup->rise_time > specs->rise_max ||
setup->fall_time > specs->fall_max) {
pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
__func__,
setup->rise_time, specs->rise_max,
setup->fall_time, specs->fall_max);
log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
setup->rise_time, specs->rise_max,
setup->fall_time, specs->fall_max);
return -EINVAL;
}
if (setup->dnf > STM32_I2C_DNF_MAX) {
pr_err("%s: DNF out of bound %d/%d\n", __func__,
setup->dnf, STM32_I2C_DNF_MAX);
log_err("DNF out of bound %d/%d\n",
setup->dnf, STM32_I2C_DNF_MAX);
return -EINVAL;
}
@ -715,10 +716,10 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
if (ret)
goto exit;
debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
__func__, output->presc,
output->scldel, output->sdadel,
output->scll, output->sclh);
log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
output->presc,
output->scldel, output->sdadel,
output->scll, output->sclh);
exit:
/* Release list and memory */
@ -751,20 +752,19 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
setup->clock_src = clk_get_rate(&i2c_priv->clk);
if (!setup->clock_src) {
pr_err("%s: clock rate is 0\n", __func__);
log_err("clock rate is 0\n");
return -EINVAL;
}
do {
ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
if (ret) {
debug("%s: failed to compute I2C timings.\n",
__func__);
log_debug("failed to compute I2C timings.\n");
if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
setup->speed_freq =
get_lower_rate(setup->speed_freq);
debug("%s: downgrade I2C Speed Freq to (%i)\n",
__func__, setup->speed_freq);
log_debug("downgrade I2C Speed Freq to (%i)\n",
setup->speed_freq);
} else {
break;
}
@ -772,16 +772,16 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
} while (ret);
if (ret) {
pr_err("%s: impossible to compute I2C timings.\n", __func__);
log_err("impossible to compute I2C timings.\n");
return ret;
}
debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
setup->speed_freq, setup->clock_src);
debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
setup->rise_time, setup->fall_time);
debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
setup->analog_filter ? "On" : "Off", setup->dnf);
log_debug("I2C Freq(%i), Clk Source(%i)\n",
setup->speed_freq, setup->clock_src);
log_debug("I2C Rise(%i) and Fall(%i) Time\n",
setup->rise_time, setup->fall_time);
log_debug("I2C Analog Filter(%s), DNF(%i)\n",
setup->analog_filter ? "On" : "Off", setup->dnf);
i2c_priv->speed = setup->speed_freq;
@ -848,12 +848,12 @@ static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
return 0;
}
static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
if (speed > I2C_SPEED_FAST_PLUS_RATE) {
debug("%s: Speed %d not supported\n", __func__, speed);
dev_dbg(dev, "Speed %d not supported\n", speed);
return -EINVAL;
}

16
drivers/mailbox/stm32-ipcc.c
View File

@ -3,6 +3,8 @@
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_MAILBOX
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -44,11 +46,11 @@ static int stm32_ipcc_request(struct mbox_chan *chan)
{
struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
debug("%s(chan=%p)\n", __func__, chan);
dev_dbg(chan->dev, "chan=%p\n", chan);
if (chan->id >= ipcc->n_chans) {
debug("%s failed to request channel: %ld\n",
__func__, chan->id);
dev_dbg(chan->dev, "failed to request channel: %ld\n",
chan->id);
return -EINVAL;
}
@ -57,7 +59,7 @@ static int stm32_ipcc_request(struct mbox_chan *chan)
static int stm32_ipcc_free(struct mbox_chan *chan)
{
debug("%s(chan=%p)\n", __func__, chan);
dev_dbg(chan->dev, "chan=%p\n", chan);
return 0;
}
@ -66,7 +68,7 @@ static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
{
struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data);
if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
return -EBUSY;
@ -83,7 +85,7 @@ static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
u32 val;
int proc_offset;
debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data);
/* read 'channel occupied' status from other proc */
proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
@ -104,7 +106,7 @@ static int stm32_ipcc_probe(struct udevice *dev)
struct clk clk;
int ret;
debug("%s(dev=%p)\n", __func__, dev);
dev_dbg(dev, "\n");
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)

30
drivers/memory/stm32-fmc2-ebi.c
View File

@ -3,10 +3,13 @@
* Copyright (C) STMicroelectronics 2020
*/
#define LOG_CATEGORY UCLASS_NOP
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <reset.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/iopoll.h>
@ -860,7 +863,7 @@ static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
u32 setup = 0;
if (!prop->set) {
pr_err("property %s is not well defined\n", prop->name);
log_err("property %s is not well defined\n", prop->name);
return -EINVAL;
}
@ -873,8 +876,8 @@ static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
bprop = ofnode_read_bool(node, prop->name);
if (prop->mprop && !bprop) {
pr_err("mandatory property %s not defined in the device tree\n",
prop->name);
log_err("mandatory property %s not defined in the device tree\n",
prop->name);
return -EINVAL;
}
@ -886,8 +889,8 @@ static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
ret = ofnode_read_u32(node, prop->name, &val);
if (prop->mprop && ret) {
pr_err("mandatory property %s not defined in the device tree\n",
prop->name);
log_err("mandatory property %s not defined in the device tree\n",
prop->name);
return ret;
}
@ -949,8 +952,8 @@ static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
if (ret) {
pr_err("property %s could not be set: %d\n",
p->name, ret);
log_err("property %s could not be set: %d\n",
p->name, ret);
return ret;
}
}
@ -971,25 +974,24 @@ static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
dev_for_each_subnode(child, dev) {
ret = ofnode_read_u32(child, "reg", &bank);
if (ret) {
pr_err("could not retrieve reg property: %d\n", ret);
dev_err(dev, "could not retrieve reg property: %d\n", ret);
return ret;
}
if (bank >= FMC2_MAX_BANKS) {
pr_err("invalid reg value: %d\n", bank);
dev_err(dev, "invalid reg value: %d\n", bank);
return -EINVAL;
}
if (ebi->bank_assigned & BIT(bank)) {
pr_err("bank already assigned: %d\n", bank);
dev_err(dev, "bank already assigned: %d\n", bank);
return -EINVAL;
}
if (bank < FMC2_MAX_EBI_CE) {
ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
if (ret) {
pr_err("setup chip select %d failed: %d\n",
bank, ret);
dev_err(dev, "setup chip select %d failed: %d\n", bank, ret);
return ret;
}
}
@ -999,12 +1001,12 @@ static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
}
if (!child_found) {
pr_warn("no subnodes found, disable the driver.\n");
dev_warn(dev, "no subnodes found, disable the driver.\n");
return -ENODEV;
}
if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
pr_err("NWAIT signal connected to EBI and NAND controllers\n");
dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
return -EINVAL;
}

10
drivers/misc/stm32_rcc.c
View File

@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_NOP
#include <common.h>
#include <dm.h>
#include <log.h>
@ -45,14 +47,14 @@ static int stm32_rcc_bind(struct udevice *dev)
(struct stm32_rcc_clk *)dev_get_driver_data(dev);
int ret;
debug("%s(dev=%p)\n", __func__, dev);
dev_dbg(dev, "RCC bind\n");
drv = lists_driver_lookup_name(rcc_clk->drv_name);
if (!drv) {
debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name);
return -ENOENT;
}
ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name,
ret = device_bind_with_driver_data(dev, drv, dev->name,
rcc_clk->soc,
dev_ofnode(dev), &child);
@ -65,7 +67,7 @@ static int stm32_rcc_bind(struct udevice *dev)
return -ENOENT;
}
return device_bind_with_driver_data(dev, drv, "stm32_rcc_reset",
return device_bind_with_driver_data(dev, drv, dev->name,
rcc_clk->soc,
dev_ofnode(dev), &child);
}

84
drivers/mmc/stm32_sdmmc2.c
View File

@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_MMC
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
@ -13,6 +15,7 @@
#include <malloc.h>
#include <asm/bitops.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
@ -200,10 +203,11 @@ struct stm32_sdmmc2_ctx {
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
#define SDMMC_BUSYD0END_TIMEOUT_US 2000000
static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
static void stm32_sdmmc2_start_data(struct udevice *dev,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
{
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 data_ctrl, idmabase0;
/* Configure the SDMMC DPSM (Data Path State Machine) */
@ -241,10 +245,11 @@ static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
}
static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
static void stm32_sdmmc2_start_cmd(struct udevice *dev,
struct mmc_cmd *cmd, u32 cmd_param,
struct stm32_sdmmc2_ctx *ctx)
{
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 timeout = 0;
if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
@ -290,10 +295,11 @@ static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
writel(cmd_param, priv->base + SDMMC_CMD);
}
static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
static int stm32_sdmmc2_end_cmd(struct udevice *dev,
struct mmc_cmd *cmd,
struct stm32_sdmmc2_ctx *ctx)
{
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 mask = SDMMC_STA_CTIMEOUT;
u32 status;
int ret;
@ -311,22 +317,22 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
10000);
if (ret < 0) {
debug("%s: timeout reading SDMMC_STA register\n", __func__);
dev_dbg(dev, "timeout reading SDMMC_STA register\n");
ctx->dpsm_abort = true;
return ret;
}
/* Check status */
if (status & SDMMC_STA_CTIMEOUT) {
debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EILSEQ;
}
@ -350,15 +356,15 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
SDMMC_BUSYD0END_TIMEOUT_US);
if (ret < 0) {
debug("%s: timeout reading SDMMC_STA\n",
__func__);
dev_dbg(dev, "timeout reading SDMMC_STA\n");
ctx->dpsm_abort = true;
return ret;
}
if (status & SDMMC_STA_DTIMEOUT) {
debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
__func__, status);
dev_dbg(dev,
"error SDMMC_STA_DTIMEOUT (0x%x)\n",
status);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
@ -368,11 +374,12 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
return 0;
}
static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
static int stm32_sdmmc2_end_data(struct udevice *dev,
struct mmc_cmd *cmd,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
{
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
u32 status;
@ -394,37 +401,37 @@ static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
if (status & SDMMC_STA_DCRCFAIL) {
debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
status, cmd->cmdidx);
if (readl(priv->base + SDMMC_DCOUNT))
ctx->dpsm_abort = true;
return -EILSEQ;
}
if (status & SDMMC_STA_DTIMEOUT) {
debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
if (status & SDMMC_STA_TXUNDERR) {
debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
if (status & SDMMC_STA_RXOVERR) {
debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
if (status & SDMMC_STA_IDMATE) {
debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
@ -448,19 +455,18 @@ retry_cmd:
if (data) {
ctx.data_length = data->blocks * data->blocksize;
stm32_sdmmc2_start_data(priv, data, &ctx);
stm32_sdmmc2_start_data(dev, data, &ctx);
}
stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
__func__, cmd->cmdidx,
data ? ctx.data_length : 0, (unsigned int)data);
dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
if (data && !ret)
ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
/* Clear flags */
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
@ -478,26 +484,24 @@ retry_cmd:
stop_cmd.cmdarg = 0;
stop_cmd.resp_type = MMC_RSP_R1b;
debug("%s: send STOP command to abort dpsm treatments\n",
__func__);
dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
ctx.data_length = 0;
stm32_sdmmc2_start_cmd(priv, &stop_cmd,
stm32_sdmmc2_start_cmd(dev, &stop_cmd,
SDMMC_CMD_CMDSTOP, &ctx);
stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
}
if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
printf("%s: cmd %d failed, retrying ...\n",
__func__, cmd->cmdidx);
dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
retry--;
goto retry_cmd;
}
debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
return ret;
}
@ -579,8 +583,8 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev)
u32 sys_clock = clk_get_rate(&priv->clk);
u32 clk = 0;
debug("%s: bus_with = %d, clock = %d\n", __func__,
mmc->bus_width, mmc->clock);
dev_dbg(dev, "bus_with = %d, clock = %d\n",
mmc->bus_width, mmc->clock);
if (mmc->clk_disable)
stm32_sdmmc2_pwrcycle(priv);
@ -616,7 +620,7 @@ static int stm32_sdmmc2_getcd(struct udevice *dev)
{
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
debug("stm32_sdmmc2_getcd called\n");
dev_dbg(dev, "%s called\n", __func__);
if (dm_gpio_is_valid(&priv->cd_gpio))
return dm_gpio_get_value(&priv->cd_gpio);

40
drivers/mtd/nand/raw/stm32_fmc2_nand.c
View File

@ -4,12 +4,15 @@
* Author: Christophe Kerello <christophe.kerello@st.com>
*/
#define LOG_CATEGORY UCLASS_MTD
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <nand.h>
#include <reset.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@ -324,7 +327,7 @@ static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
if (ret < 0) {
pr_err("Ham timeout\n");
log_err("Ham timeout\n");
return ret;
}
@ -409,7 +412,7 @@ static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
if (ret < 0) {
pr_err("Bch timeout\n");
log_err("Bch timeout\n");
return ret;
}
@ -457,7 +460,7 @@ static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
if (ret < 0) {
pr_err("Bch timeout\n");
log_err("Bch timeout\n");
return ret;
}
@ -795,26 +798,24 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
nand->ncs /= sizeof(u32);
if (!nand->ncs) {
pr_err("Invalid reg property size\n");
log_err("Invalid reg property size\n");
return -EINVAL;
}
ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
if (ret < 0) {
pr_err("Could not retrieve reg property\n");
log_err("Could not retrieve reg property\n");
return -EINVAL;
}
for (i = 0; i < nand->ncs; i++) {
if (cs[i] >= FMC2_MAX_CE) {
pr_err("Invalid reg value: %d\n",
nand->cs_used[i]);
log_err("Invalid reg value: %d\n", nand->cs_used[i]);
return -EINVAL;
}
if (nfc->cs_assigned & BIT(cs[i])) {
pr_err("Cs already assigned: %d\n",
nand->cs_used[i]);
log_err("Cs already assigned: %d\n", nand->cs_used[i]);
return -EINVAL;
}
@ -837,12 +838,12 @@ static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
nchips++;
if (!nchips) {
pr_err("NAND chip not defined\n");
log_err("NAND chip not defined\n");
return -EINVAL;
}
if (nchips > 1) {
pr_err("Too many NAND chips defined\n");
log_err("Too many NAND chips defined\n");
return -EINVAL;
}
@ -918,24 +919,21 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
addr = dev_read_addr_index(dev, mem_region);
if (addr == FDT_ADDR_T_NONE) {
pr_err("Resource data_base not found for cs%d",
chip_cs);
dev_err(dev, "Resource data_base not found for cs%d", chip_cs);
return ret;
}
nfc->data_base[chip_cs] = addr;
addr = dev_read_addr_index(dev, mem_region + 1);
if (addr == FDT_ADDR_T_NONE) {
pr_err("Resource cmd_base not found for cs%d",
chip_cs);
dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs);
return ret;
}
nfc->cmd_base[chip_cs] = addr;
addr = dev_read_addr_index(dev, mem_region + 2);
if (addr == FDT_ADDR_T_NONE) {
pr_err("Resource addr_base not found for cs%d",
chip_cs);
dev_err(dev, "Resource addr_base not found for cs%d", chip_cs);
return ret;
}
nfc->addr_base[chip_cs] = addr;
@ -985,14 +983,14 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
* ECC sector size = 512
*/
if (chip->ecc.mode != NAND_ECC_HW) {
pr_err("Nand_ecc_mode is not well defined in the DT\n");
dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n");
return -EINVAL;
}
ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
mtd->oobsize - FMC2_BBM_LEN);
if (ret) {
pr_err("No valid ECC settings set\n");
dev_err(dev, "No valid ECC settings set\n");
return ret;
}
@ -1045,6 +1043,6 @@ void board_nand_init(void)
DM_DRIVER_GET(stm32_fmc2_nfc),
&dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
ret);
log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
ret);
}

18
drivers/phy/phy-stm32-usbphyc.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_PHY
#include <common.h>
#include <clk.h>
#include <div64.h>
@ -98,8 +100,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
u32 usbphyc_pll;
if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
pr_debug("%s: input clk freq (%dHz) out of range\n",
__func__, clk_rate);
log_debug("input clk freq (%dHz) out of range\n",
clk_rate);
return -EINVAL;
}
@ -116,8 +118,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
clk_rate, pll_params.ndiv, pll_params.frac);
log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
clk_rate, pll_params.ndiv, pll_params.frac);
return 0;
}
@ -154,7 +156,7 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
true : false;
int ret;
pr_debug("%s phy ID = %lu\n", __func__, phy->id);
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
/* Check if one phy port has already configured the pll */
if (pllen && stm32_usbphyc_is_init(usbphyc))
goto initialized;
@ -200,7 +202,7 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
pr_debug("%s phy ID = %lu\n", __func__, phy->id);
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->init = false;
/* Check if other phy port requires pllen */
@ -239,7 +241,7 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
pr_debug("%s phy ID = %lu\n", __func__, phy->id);
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, true);
if (ret)
@ -262,7 +264,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
pr_debug("%s phy ID = %lu\n", __func__, phy->id);
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->powered = false;
if (stm32_usbphyc_is_powered(usbphyc))

30
drivers/pinctrl/pinctrl_stm32.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_PINCTRL
#include <common.h>
#include <dm.h>
#include <hwspinlock.h>
@ -256,8 +258,8 @@ static int stm32_pinctrl_probe(struct udevice *dev)
/* hwspinlock property is optional, just log the error */
ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
if (ret)
debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
__func__, ret);
dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
ret);
return 0;
}
@ -305,8 +307,7 @@ static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
{
gpio_dsc->port = (port_pin & 0x1F000) >> 12;
gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
gpio_dsc->pin);
log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
return 0;
}
@ -347,9 +348,9 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
else
gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
__func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
gpio_ctl->pupd);
log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
gpio_ctl->pupd);
return 0;
}
@ -373,7 +374,7 @@ static int stm32_pinctrl_config(ofnode node)
if (rv < 0)
return rv;
len = rv / sizeof(pin_mux[0]);
debug("%s: no of pinmux entries= %d\n", __func__, len);
log_debug("No of pinmux entries= %d\n", len);
if (len > MAX_PINS_ONE_IP)
return -EINVAL;
rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
@ -382,7 +383,7 @@ static int stm32_pinctrl_config(ofnode node)
for (i = 0; i < len; i++) {
struct gpio_desc desc;
debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
log_debug("pinmux = %x\n", *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
@ -392,7 +393,7 @@ static int stm32_pinctrl_config(ofnode node)
return rv;
desc.offset = gpio_dsc.pin;
rv = stm32_gpio_config(&desc, &gpio_ctl);
debug("%s: rv = %d\n\n", __func__, rv);
log_debug("rv = %d\n\n", rv);
if (rv)
return rv;
}
@ -408,7 +409,7 @@ static int stm32_pinctrl_bind(struct udevice *dev)
int ret;
dev_for_each_subnode(node, dev) {
debug("%s: bind %s\n", __func__, ofnode_get_name(node));
dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
@ -424,7 +425,7 @@ static int stm32_pinctrl_bind(struct udevice *dev)
if (ret)
return ret;
debug("%s: bind %s\n", __func__, name);
dev_dbg(dev, "bind %s\n", name);
}
return 0;
@ -448,7 +449,7 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev,
if (!list)
return -EINVAL;
debug("%s: periph->name = %s\n", __func__, periph->name);
dev_dbg(dev, "periph->name = %s\n", periph->name);
size /= sizeof(*list);
for (i = 0; i < size; i++) {
@ -456,7 +457,8 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev,
config_node = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(config_node)) {
pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
dev_err(periph,
"prop pinctrl-0 index %d invalid phandle\n", i);
return -EINVAL;
}

2
drivers/power/regulator/stm32-vrefbuf.c
View File

@ -6,6 +6,8 @@
* Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c
*/
#define LOG_CATEGORY UCLASS_REGULATOR
#include <common.h>
#include <clk.h>
#include <dm.h>

10
drivers/ram/stm32_sdram.c
View File

@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -272,7 +274,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (ret) {
dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
dev_dbg(dev, "can't find syscon device (%d)\n", ret);
} else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
@ -281,7 +283,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
/* set memory mapping selection */
clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
} else {
dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
dev_dbg(dev, "cannot find st,mem_remap property\n");
}
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
@ -289,7 +291,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
/* set fmc swapping selection */
clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
} else {
dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
dev_dbg(dev, "cannot find st,swp_fmc property\n");
}
dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
@ -348,7 +350,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
}
params->no_sdram_banks = bank;
debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);
return 0;
}

36
drivers/ram/stm32mp1/stm32mp1_ddr.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <clk.h>
#include <log.h>
@ -311,17 +313,17 @@ static void set_reg(const struct ddr_info *priv,
u32 base_addr = get_base_addr(priv, base);
const struct reg_desc *desc = ddr_registers[type].desc;
debug("init %s\n", ddr_registers[type].name);
log_debug("init %s\n", ddr_registers[type].name);
for (i = 0; i < ddr_registers[type].size; i++) {
ptr = (unsigned int *)(base_addr + desc[i].offset);
if (desc[i].par_offset == INVALID_OFFSET) {
pr_err("invalid parameter offset for %s", desc[i].name);
log_err("invalid parameter offset for %s", desc[i].name);
} else {
value = *((u32 *)((u32)param +
desc[i].par_offset));
writel(value, ptr);
debug("[0x%x] %s= 0x%08x\n",
(u32)ptr, desc[i].name, value);
log_debug("[0x%x] %s= 0x%08x\n",
(u32)ptr, desc[i].name, value);
}
}
}
@ -564,16 +566,16 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
DDRPHYC_PGSR_RVERR |
DDRPHYC_PGSR_RVEIRR),
1000000);
debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
(u32)&phy->pgsr, pgsr, ret);
log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
(u32)&phy->pgsr, pgsr, ret);
}
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
{
pir |= DDRPHYC_PIR_INIT;
writel(pir, &phy->pir);
debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
(u32)&phy->pir, pir, readl(&phy->pir));
log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
(u32)&phy->pir, pir, readl(&phy->pir));
/* need to wait 10 configuration clock before start polling */
udelay(10);
@ -603,7 +605,7 @@ static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
panic("Timeout initialising DRAM : DDR->swstat = %x\n",
swstat);
debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
}
/* wait quasi dynamic register update */
@ -634,7 +636,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode)
if (ret)
panic("Timeout DRAM : DDR->stat = %x\n", stat);
debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
}
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
@ -706,9 +708,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
panic("ddr power init failed\n");
start:
debug("name = %s\n", config->info.name);
debug("speed = %d kHz\n", config->info.speed);
debug("size = 0x%x\n", config->info.size);
log_debug("name = %s\n", config->info.name);
log_debug("speed = %d kHz\n", config->info.speed);
log_debug("size = 0x%x\n", config->info.size);
/*
* 1. Program the DWC_ddr_umctl2 registers
* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
@ -745,8 +747,8 @@ start:
/* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */
clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
debug("[0x%08x] dfimisc = 0x%08x\n",
(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
log_debug("[0x%08x] dfimisc = 0x%08x\n",
(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
set_reg(priv, REG_REG, &config->c_reg);
set_reg(priv, REG_TIMING, &config->c_timing);
@ -809,9 +811,9 @@ start:
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
if (config->p_cal_present) {
debug("DDR DQS training skipped.\n");
log_debug("DDR DQS training skipped.\n");
} else {
debug("DDR DQS training : ");
log_debug("DDR DQS training : ");
/* 8. Disable Auto refresh and power down by setting
* - RFSHCTL3.dis_au_refresh = 1
* - PWRCTL.powerdown_en = 0

4
drivers/ram/stm32mp1/stm32mp1_interactive.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <command.h>
#include <console.h>
@ -404,7 +406,7 @@ bool stm32mp1_ddr_interactive(void *priv,
#endif
}
debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
if (next_step < 0)
return false;

38
drivers/ram/stm32mp1/stm32mp1_ram.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -12,6 +14,7 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include "stm32mp1_ddr.h"
static const char *const clkname[] = {
@ -37,7 +40,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
ret = clk_enable(&clk);
if (ret) {
printf("error for %s : %d\n", clkname[idx], ret);
log_err("error for %s : %d\n", clkname[idx], ret);
return ret;
}
}
@ -45,13 +48,13 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
priv->clk = clk;
ddrphy_clk = clk_get_rate(&priv->clk);
debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
mem_speed, (u32)(ddrphy_clk / 1000));
log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
mem_speed, (u32)(ddrphy_clk / 1000));
/* max 10% frequency delta */
ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
if (ddr_clk > (mem_speed * 100)) {
pr_err("DDR expected freq %d kHz, current is %d kHz\n",
mem_speed, (u32)(ddrphy_clk / 1000));
log_err("DDR expected freq %d kHz, current is %d kHz\n",
mem_speed, (u32)(ddrphy_clk / 1000));
return -EINVAL;
}
@ -118,7 +121,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
config.info.name = ofnode_read_string(node, "st,mem-name");
if (!config.info.name) {
debug("%s: no st,mem-name\n", __func__);
dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
}
printf("RAM: %s\n", config.info.name);
@ -128,12 +131,12 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
(void *)((u32)&config +
param[idx].offset),
param[idx].size);
debug("%s: %s[0x%x] = %d\n", __func__,
param[idx].name, param[idx].size, ret);
dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
param[idx].name, param[idx].size, ret);
if (ret &&
(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
pr_err("%s: Cannot read %s, error=%d\n",
__func__, param[idx].name, ret);
dev_err(dev, "Cannot read %s, error=%d\n",
param[idx].name, ret);
return -EINVAL;
}
if (param[idx].present) {
@ -153,7 +156,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
ret = clk_get_by_name(dev, "axidcg", &axidcg);
if (ret) {
debug("%s: Cannot found axidcg\n", __func__);
dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
return -EINVAL;
}
clk_disable(&axidcg); /* disable clock gating during init */
@ -163,13 +166,13 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
clk_enable(&axidcg); /* enable clock gating */
/* check size */
debug("%s : get_ram_size(%x, %x)\n", __func__,
(u32)priv->info.base, (u32)STM32_DDR_SIZE);
dev_dbg(dev, "get_ram_size(%x, %x)\n",
(u32)priv->info.base, (u32)STM32_DDR_SIZE);
priv->info.size = get_ram_size((long *)priv->info.base,
STM32_DDR_SIZE);
debug("%s : %x\n", __func__, (u32)priv->info.size);
dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
/* check memory access for all memory */
if (config.info.size != priv->info.size) {
@ -186,12 +189,11 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
struct regmap *map;
int ret;
debug("STM32MP1 DDR probe\n");
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), &map);
if (ret)
return ret;
return log_ret(ret);
priv->ctl = regmap_get_range(map, 0);
priv->phy = regmap_get_range(map, 1);
@ -203,7 +205,9 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
#if !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
priv->info.size = 0;
return stm32mp1_ddr_setup(dev);
ret = stm32mp1_ddr_setup(dev);
return log_ret(ret);
#else
ofnode node = stm32mp1_ddr_get_ofnode(dev);
priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);

19
drivers/ram/stm32mp1/stm32mp1_tests.c
View File

@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <console.h>
#include <init.h>
@ -197,8 +200,8 @@ static u32 databus(u32 *address)
/* Read it back (immediately is okay for this test). */
read_value = readl(address);
debug("%x: %x <=> %x\n",
(u32)address, read_value, pattern);
log_debug("%x: %x <=> %x\n",
(u32)address, read_value, pattern);
if (read_value != pattern)
return pattern;
@ -252,8 +255,8 @@ static u32 *addressbus(u32 *address, u32 nb_bytes)
for (offset = 1; (offset & mask) != 0; offset <<= 1) {
read_value = readl(&address[offset]);
debug("%x: %x <=> %x\n",
(u32)&address[offset], read_value, pattern);
log_debug("%x: %x <=> %x\n",
(u32)&address[offset], read_value, pattern);
if (read_value != pattern)
return &address[offset];
}
@ -363,8 +366,8 @@ static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl,
data = readl(addr + 4 * i);
if (~(1 << i) != data) {
error |= 1 << i;
debug("%x: error %x expected %x => error:%x\n",
addr + 4 * i, data, ~(1 << i), error);
log_debug("%x: error %x expected %x => error:%x\n",
addr + 4 * i, data, ~(1 << i), error);
}
}
if (test_loop_end(&loop, nb_loop, 1000))
@ -403,8 +406,8 @@ static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl,
data = readl(addr + 4 * i);
if ((1 << i) != data) {
error |= 1 << i;
debug("%x: error %x expected %x => error:%x\n",
addr + 4 * i, data, (1 << i), error);
log_debug("%x: error %x expected %x => error:%x\n",
addr + 4 * i, data, (1 << i), error);
}
}
if (test_loop_end(&loop, nb_loop, 1000))

124
drivers/ram/stm32mp1/stm32mp1_tuning.c
View File

@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <console.h>
#include <clk.h>
@ -227,8 +230,7 @@ static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
& DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
__func__, addr, readl(addr), index);
log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index);
return index;
}
@ -470,13 +472,13 @@ static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
for (bit_i = 0; bit_i < 8; bit_i++) {
set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
index = DQ_unit_index(phy, byte, bit_i);
pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
byte, bit_i, deskew_delay[byte][bit_i],
index, index - 3);
log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
byte, bit_i, deskew_delay[byte][bit_i],
index, index - 3);
printf("Byte %d, bit %d, DQ delay = %d",
byte, bit_i, deskew_delay[byte][bit_i]);
if (deskew_non_converge[byte][bit_i] == 1)
pr_debug(" - not converged : still more skew");
log_debug(" - not converged : still more skew");
printf("\n");
}
}
@ -536,7 +538,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
/* Config the BIST block */
config_BIST(ctl, phy);
pr_debug("BIST Config done.\n");
log_debug("BIST Config done.\n");
/* Train each byte */
for (datx8 = 0; datx8 < nb_bytes; datx8++) {
@ -545,9 +547,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
datx8 + 1, nb_bytes, error);
return TEST_FAILED;
}
pr_debug("\n======================\n");
pr_debug("Start deskew byte %d .\n", datx8);
pr_debug("======================\n");
log_debug("\n======================\n");
log_debug("Start deskew byte %d .\n", datx8);
log_debug("======================\n");
/* Enable Byte (DXNGCR, bit DXEN) */
setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
@ -584,7 +586,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* Else, look for Pass init condition
*/
if (!success) {
pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
log_debug("Fail at init condtion. Let's look for a good init condition.\n");
success = 0; /* init */
/* Make sure we start with a PASS condition before
* looking for a fail condition.
@ -592,7 +594,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
/* escape if we find a PASS */
pr_debug("increase Phase idx\n");
log_debug("increase Phase idx\n");
while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
DQS_phase_delay(phy, datx8, phase_idx);
BIST_test(phy, datx8, &result);
@ -618,7 +620,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* we have hold violation, lets try reduce DQS_unit
* Delay
*/
pr_debug("Still fail. Try decrease DQS Unit delay\n");
log_debug("Still fail. Try decrease DQS Unit delay\n");
phase_idx = 0;
dqs_unit_delay_index = 0;
@ -665,9 +667,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
return TEST_FAILED;
}
pr_debug("there is a pass region for phase idx %d\n",
phase_idx);
pr_debug("Step1: Find the first failing condition\n");
log_debug("there is a pass region for phase idx %d\n",
phase_idx);
log_debug("Step1: Find the first failing condition\n");
/* Look for the first failing condition by PHASE stepping.
* This part of the algo can finish without converging.
*/
@ -692,9 +694,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* stepping (minimal delay)
*/
if (!success) {
pr_debug("Fail region (PHASE) found phase idx %d\n",
phase_idx);
pr_debug("Let's look for first success by DQS Unit steps\n");
log_debug("Fail region (PHASE) found phase idx %d\n",
phase_idx);
log_debug("Let's look for first success by DQS Unit steps\n");
/* This part, the algo always converge */
phase_idx--;
@ -721,7 +723,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
/*+1 to get back to current condition */
last_right_ok.unit = dqs_unit_delay_index + 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
pr_debug("Found %d\n", dqs_unit_delay_index);
log_debug("Found %d\n", dqs_unit_delay_index);
} else {
/* the last OK condition is then with the
* previous phase_idx.
@ -735,8 +737,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
last_right_ok.unit = 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
pr_debug("Not Found : try previous phase %d\n",
phase_idx - 1);
log_debug("Not Found : try previous phase %d\n",
phase_idx - 1);
DQS_phase_delay(phy, datx8, phase_idx - 1);
dqs_unit_delay_index = 0;
@ -749,8 +751,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
BIST_test(phy, datx8, &result);
success = result.test_result;
dqs_unit_delay_index++;
pr_debug("dqs_unit_delay_index = %d, result = %d\n",
dqs_unit_delay_index, success);
log_debug("dqs_unit_delay_index = %d, result = %d\n",
dqs_unit_delay_index, success);
}
if (!success) {
@ -758,7 +760,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
dqs_unit_delay_index - 1;
} else {
last_right_ok.unit = 0;
pr_debug("ERROR: failed region not FOUND");
log_debug("ERROR: failed region not FOUND");
}
}
} else {
@ -775,7 +777,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
last_right_ok.phase = MAX_DQS_PHASE_IDX;
last_right_ok.unit = MAX_DQS_UNIT_IDX;
last_right_ok.bits_delay = 0xFFFFFFFF;
pr_debug("Can't find the a fail condition\n");
log_debug("Can't find the a fail condition\n");
}
/* step 2:
@ -787,9 +789,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
printf("Byte %d, DQS unit = %d, phase = %d\n",
datx8, last_right_ok.unit, last_right_ok.phase);
pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
last_right_ok.unit, last_right_ok.phase,
last_right_ok.bits_delay);
log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
last_right_ok.unit, last_right_ok.phase,
last_right_ok.bits_delay);
/* Restore the last_right_ok condtion. */
DQS_unit_delay(phy, datx8, last_right_ok.unit);
@ -812,7 +814,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
datx8 + 1, nb_bytes, error);
return error;
}
pr_debug("deskewing bit %d:\n", bit_i);
log_debug("deskewing bit %d:\n", bit_i);
success = 1; /* init */
/* Set all DQDLYn to maximum value.
* Only bit_i will be down-delayed
@ -855,10 +857,10 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* at one bit.
*/
fail_found = 1;
pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
bit_i, bit_i_delay_index + 1,
datx8, bit_i,
deskew_delay[datx8][bit_i]);
log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
bit_i, bit_i_delay_index + 1,
datx8, bit_i,
deskew_delay[datx8][bit_i]);
} else {
/* if we can find a success condition by
* back-delaying this bit, just set the delay
@ -870,20 +872,20 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* in the report.
*/
deskew_non_converge[datx8][bit_i] = 1;
pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
bit_i, datx8, bit_i,
deskew_delay[datx8][bit_i]);
log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
bit_i, datx8, bit_i,
deskew_delay[datx8][bit_i]);
}
}
pr_debug("**********byte %d tuning complete************\n",
datx8);
log_debug("**********byte %d tuning complete************\n",
datx8);
/* If we can't find any failure by back delaying DQ lines,
* hold the default values
*/
if (!fail_found) {
for (bit_i = 0; bit_i < 8; bit_i++)
deskew_delay[datx8][bit_i] = 0;
pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
}
apply_deskew_results(phy, datx8, deskew_delay,
@ -986,7 +988,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
dqs_unit_delay_index_pass = dqs_unit_delay_index;
success = 0;
pr_debug("STEP0: Find Init delay\n");
log_debug("STEP0: Find Init delay\n");
/* STEP0: Find Init delay: a delay that put the system
* in a "Pass" condition then (TODO) update
* dqs_unit_delay_index_pass & phase_idx_pass
@ -1035,7 +1037,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
log_debug("STEP1: Find LEFT PHASE DQS Bound\n");
/* STEP1: Find LEFT PHASE DQS Bound */
while ((phase_idx >= 0) &&
(phase_idx <= MAX_DQS_PHASE_IDX) &&
@ -1069,7 +1071,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
pr_debug("STEP2: Find UNIT left bound\n");
log_debug("STEP2: Find UNIT left bound\n");
/* STEP2: Find UNIT left bound */
while ((dqs_unit_delay_index >= 0) &&
!left_unit_bound_found) {
@ -1097,7 +1099,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
pr_debug("STEP3: Find PHase right bound\n");
log_debug("STEP3: Find PHase right bound\n");
/* STEP3: Find PHase right bound, start with "pass"
* condition
*/
@ -1135,7 +1137,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
pr_debug("STEP4: Find UNIT right bound\n");
log_debug("STEP4: Find UNIT right bound\n");
/* STEP4: Find UNIT right bound */
while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
!right_unit_bound_found) {
@ -1174,12 +1176,12 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
eye_training_val[byte][1]++;
pr_debug("** found phase : %d - %d & unit %d - %d\n",
right_bound.phase, left_bound.phase,
right_bound.unit, left_bound.unit);
pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
eye_training_val[byte][0],
eye_training_val[byte][1]);
log_debug("** found phase : %d - %d & unit %d - %d\n",
right_bound.phase, left_bound.phase,
right_bound.unit, left_bound.unit);
log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
eye_training_val[byte][0],
eye_training_val[byte][1]);
} else {
/* PPPPPPPPPP, we're already good.
* Set nominal values.
@ -1280,11 +1282,11 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
* or pppppff or ffppppp
*/
if (left_bound_found || right_bound_found) {
pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
left_bound_found,
right_bound_idx[0], left_bound_idx[0],
right_bound_found,
right_bound_idx[1], left_bound_idx[1]);
log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
left_bound_found,
right_bound_idx[0], left_bound_idx[0],
right_bound_found,
right_bound_idx[1], left_bound_idx[1]);
dqs_gate_values[byte][0] =
(right_bound_idx[0] + left_bound_idx[0]) / 2;
dqs_gate_values[byte][1] =
@ -1319,14 +1321,14 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
left_bound_idx[0];
}
}
pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
dqs_gate_values[byte][0],
dqs_gate_values[byte][1]);
pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
log_debug("*******calculating mid region: system latency: %d phase: %d********\n",
dqs_gate_values[byte][0],
dqs_gate_values[byte][1]);
log_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
}
} else {
/* if intermitant, restore defaut values */
pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
dqs_gate_values[byte][0] = 0;
dqs_gate_values[byte][1] = 2;
}

3
drivers/remoteproc/stm32_copro.c
View File

@ -2,7 +2,8 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#define LOG_CATEGORY UCLASS_REMOTEPROC
#include <common.h>
#include <dm.h>
#include <errno.h>

13
drivers/reset/stm32-reset.c
View File

@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_RESET
#include <common.h>
#include <dm.h>
#include <errno.h>
@ -12,6 +14,7 @@
#include <reset-uclass.h>
#include <stm32_rcc.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
/* offset of register without set/clear management */
@ -39,8 +42,9 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
if (bank != RCC_MP_GCR_OFFSET)
@ -59,8 +63,9 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
if (bank != RCC_MP_GCR_OFFSET)

3
drivers/rtc/stm32_rtc.c
View File

@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RTC
#include <common.h>
#include <clk.h>
#include <dm.h>

3
drivers/serial/serial_stm32.c
View File

@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_SERIAL
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -13,6 +15,7 @@
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include "serial_stm32.h"

46
drivers/spi/stm32_qspi.c
View File

@ -7,6 +7,8 @@
* STM32 QSPI driver
*/
#define LOG_CATEGORY UCLASS_SPI
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -136,7 +138,7 @@ static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
!(sr & STM32_QSPI_SR_BUSY),
STM32_BUSY_TIMEOUT_US);
if (ret)
pr_err("busy timeout (stat:%#x)\n", sr);
log_err("busy timeout (stat:%#x)\n", sr);
return ret;
}
@ -154,9 +156,9 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
sr & STM32_QSPI_SR_TCF,
STM32_QSPI_CMD_TIMEOUT_US);
if (ret) {
pr_err("cmd timeout (stat:%#x)\n", sr);
log_err("cmd timeout (stat:%#x)\n", sr);
} else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
pr_err("transfer error (stat:%#x)\n", sr);
log_err("transfer error (stat:%#x)\n", sr);
ret = -EIO;
}
@ -198,7 +200,7 @@ static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
sr & STM32_QSPI_SR_FTF,
STM32_QSPI_FIFO_TIMEOUT_US);
if (ret) {
pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
return ret;
}
@ -246,10 +248,10 @@ static int stm32_qspi_exec_op(struct spi_slave *slave,
u8 mode = STM32_QSPI_CCR_IND_WRITE;
int timeout, ret;
debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
op->dummy.buswidth, op->data.buswidth,
op->addr.val, op->data.nbytes);
dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
op->dummy.buswidth, op->data.buswidth,
op->addr.val, op->data.nbytes);
ret = _stm32_qspi_wait_for_not_busy(priv);
if (ret)
@ -320,7 +322,7 @@ abort:
writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
if (ret || timeout)
pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
return ret;
}
@ -353,8 +355,8 @@ static int stm32_qspi_probe(struct udevice *bus)
if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
return -EINVAL;
debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
__func__, priv->regs, priv->mm_base, priv->mm_size);
dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
priv->regs, priv->mm_base, priv->mm_size);
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0)
@ -475,8 +477,8 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
csht << STM32_QSPI_DCR_CSHT_SHIFT);
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
(qspi_clk / (prescaler + 1)));
dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
(qspi_clk / (prescaler + 1)));
return 0;
}
@ -485,6 +487,7 @@ static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
{
struct stm32_qspi_priv *priv = dev_get_priv(bus);
int ret;
const char *str_rx, *str_tx;
ret = _stm32_qspi_wait_for_not_busy(priv);
if (ret)
@ -500,21 +503,22 @@ static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
if (mode & SPI_CS_HIGH)
return -ENODEV;
debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
if (mode & SPI_RX_QUAD)
debug("quad, tx: ");
str_rx = "quad";
else if (mode & SPI_RX_DUAL)
debug("dual, tx: ");
str_rx = "dual";
else
debug("single, tx: ");
str_rx = "single";
if (mode & SPI_TX_QUAD)
debug("quad\n");
str_tx = "quad";
else if (mode & SPI_TX_DUAL)
debug("dual\n");
str_tx = "dual";
else
debug("single\n");
str_tx = "single";
dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
priv->regs, mode, str_rx, str_tx);
return 0;
}

31
drivers/spi/stm32_spi.c
View File

@ -4,6 +4,9 @@
*
* Driver for STMicroelectronics Serial peripheral interface (SPI)
*/
#define LOG_CATEGORY UCLASS_SPI
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -138,7 +141,7 @@ static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
}
}
debug("%s: %d bytes left\n", __func__, priv->tx_len);
log_debug("%d bytes left\n", priv->tx_len);
}
static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
@ -176,12 +179,12 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
}
debug("%s: %d bytes left\n", __func__, priv->rx_len);
log_debug("%d bytes left\n", priv->rx_len);
}
static int stm32_spi_enable(struct stm32_spi_priv *priv)
{
debug("%s\n", __func__);
log_debug("\n");
/* Enable the SPI hardware */
setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
@ -191,7 +194,7 @@ static int stm32_spi_enable(struct stm32_spi_priv *priv)
static int stm32_spi_disable(struct stm32_spi_priv *priv)
{
debug("%s\n", __func__);
log_debug("\n");
/* Disable the SPI hardware */
clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
@ -204,7 +207,7 @@ static int stm32_spi_claim_bus(struct udevice *slave)
struct udevice *bus = dev_get_parent(slave);
struct stm32_spi_priv *priv = dev_get_priv(bus);
debug("%s\n", __func__);
dev_dbg(slave, "\n");
/* Enable the SPI hardware */
return stm32_spi_enable(priv);
@ -215,7 +218,7 @@ static int stm32_spi_release_bus(struct udevice *slave)
struct udevice *bus = dev_get_parent(slave);
struct stm32_spi_priv *priv = dev_get_priv(bus);
debug("%s\n", __func__);
dev_dbg(slave, "\n");
/* Disable the SPI hardware */
return stm32_spi_disable(priv);
@ -227,7 +230,7 @@ static void stm32_spi_stopxfer(struct udevice *dev)
u32 cr1, sr;
int ret;
debug("%s\n", __func__);
dev_dbg(dev, "\n");
cr1 = readl(priv->base + STM32_SPI_CR1);
@ -255,7 +258,7 @@ static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
{
struct stm32_spi_priv *priv = dev_get_priv(dev);
debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
if (cs >= MAX_CS_COUNT)
return -ENODEV;
@ -274,7 +277,7 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode)
struct stm32_spi_priv *priv = dev_get_priv(bus);
u32 cfg2_clrb = 0, cfg2_setb = 0;
debug("%s: mode=%d\n", __func__, mode);
dev_dbg(bus, "mode=%d\n", mode);
if (mode & SPI_CPOL)
cfg2_setb |= SPI_CFG2_CPOL;
@ -330,7 +333,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz)
u32 mbrdiv;
long div;
debug("%s: hz=%d\n", __func__, hz);
dev_dbg(bus, "hz=%d\n", hz);
if (priv->cur_hz == hz)
return 0;
@ -404,8 +407,8 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
stm32_spi_enable(priv);
}
debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
priv->tx_len, priv->rx_len);
dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
priv->tx_len, priv->rx_len);
slave_plat = dev_get_parent_plat(slave);
if (flags & SPI_XFER_BEGIN)
@ -477,7 +480,7 @@ static int stm32_spi_get_fifo_size(struct udevice *dev)
stm32_spi_disable(priv);
debug("%s %d x 8-bit fifo size\n", __func__, count);
dev_dbg(dev, "%d x 8-bit fifo size\n", count);
return count;
}
@ -522,7 +525,7 @@ static int stm32_spi_probe(struct udevice *dev)
ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
ARRAY_SIZE(priv->cs_gpios), 0);
if (ret < 0) {
pr_err("Can't get %s cs gpios: %d", dev->name, ret);
dev_err(dev, "Can't get cs gpios: %d", ret);
goto reset_err;
}

2
drivers/timer/stm32_timer.c
View File

@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_TIMER
#include <common.h>
#include <clk.h>
#include <dm.h>

18
drivers/video/stm32/stm32_dsi.c
View File

@ -8,6 +8,8 @@
* drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
*/
#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -133,7 +135,7 @@ static enum dsi_color dsi_color_from_mipi(u32 fmt)
case MIPI_DSI_FMT_RGB565:
return DSI_RGB565_CONF1;
default:
pr_err("MIPI color invalid, so we use rgb888\n");
log_err("MIPI color invalid, so we use rgb888\n");
}
return DSI_RGB888;
}
@ -213,14 +215,14 @@ static int dsi_phy_init(void *priv_data)
u32 val;
int ret;
debug("Initialize DSI physical layer\n");
dev_dbg(dev, "Initialize DSI physical layer\n");
/* Enable the regulator */
dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
TIMEOUT_US);
if (ret) {
debug("!TIMEOUT! waiting REGU\n");
dev_dbg(dev, "!TIMEOUT! waiting REGU\n");
return ret;
}
@ -229,7 +231,7 @@ static int dsi_phy_init(void *priv_data)
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
TIMEOUT_US);
if (ret) {
debug("!TIMEOUT! waiting PLL\n");
dev_dbg(dev, "!TIMEOUT! waiting PLL\n");
return ret;
}
@ -242,8 +244,8 @@ static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
struct udevice *dev = device->dev;
struct stm32_dsi_priv *dsi = dev_get_priv(dev);
debug("Set mode %p enable %ld\n", dsi,
mode_flags & MIPI_DSI_MODE_VIDEO);
dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
mode_flags & MIPI_DSI_MODE_VIDEO);
if (!dsi)
return;
@ -325,8 +327,8 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
*lane_mbps = pll_out_khz / 1000;
debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
pll_in_khz, pll_out_khz, *lane_mbps);
dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
pll_in_khz, pll_out_khz, *lane_mbps);
return 0;
}

33
drivers/video/stm32/stm32_ltdc.c
View File

@ -5,6 +5,8 @@
* Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
*/
#define LOG_CATEGORY UCLASS_VIDEO
#include <common.h>
#include <clk.h>
#include <display.h>
@ -176,13 +178,13 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
pr_warn("%s: warning %dbpp not supported yet, %dbpp instead\n",
__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
log_warning("warning %dbpp not supported yet, %dbpp instead\n",
VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
return (u32)pf;
}
@ -249,7 +251,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
/* Signal polarities */
val = 0;
debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
log_debug("timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@ -379,8 +381,8 @@ static int stm32_ltdc_probe(struct udevice *dev)
dev_warn(dev, "fail to set pixel clock %d hz\n",
timings.pixelclock.typ);
debug("%s: Set pixel clock req %d hz get %ld hz\n", __func__,
timings.pixelclock.typ, clk_get_rate(&pclk));
dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
timings.pixelclock.typ, clk_get_rate(&pclk));
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
@ -394,12 +396,13 @@ static int stm32_ltdc_probe(struct udevice *dev)
if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (ret)
debug("No video bridge, or no backlight on bridge\n");
dev_dbg(dev,
"No video bridge, or no backlight on bridge\n");
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
dev_err(dev, "fail to attach bridge\n");
dev_err(bridge, "fail to attach bridge\n");
return ret;
}
}
@ -414,12 +417,12 @@ static int stm32_ltdc_probe(struct udevice *dev)
priv->crop_h = timings.vactive.typ;
priv->alpha = 0xFF;
debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
timings.hactive.typ, timings.vactive.typ,
VNBITS(priv->l2bpp), uc_plat->base);
debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
priv->bg_col_argb, priv->alpha);
dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
timings.hactive.typ, timings.vactive.typ,
VNBITS(priv->l2bpp), uc_plat->base);
dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
priv->bg_col_argb, priv->alpha);
/* Configure & start LTDC */
stm32_ltdc_set_mode(priv, &timings);
@ -457,7 +460,7 @@ static int stm32_ltdc_bind(struct udevice *dev)
uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
CONFIG_VIDEO_STM32_MAX_YRES *
(CONFIG_VIDEO_STM32_MAX_BPP >> 3);
debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size);
dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size);
return 0;
}

9
drivers/watchdog/stm32mp_wdt.c
View File

@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_WDT
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -10,6 +12,7 @@
#include <syscon.h>
#include <wdt.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
@ -77,7 +80,7 @@ static int stm32mp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ);
if (ret < 0) {
pr_err("Updating IWDG registers timeout");
dev_err(dev, "Updating IWDG registers timeout");
return -ETIMEDOUT;
}
@ -90,7 +93,7 @@ static int stm32mp_wdt_probe(struct udevice *dev)
struct clk clk;
int ret;
debug("IWDG init\n");
dev_dbg(dev, "IWDG init\n");
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
@ -112,7 +115,7 @@ static int stm32mp_wdt_probe(struct udevice *dev)
priv->wdt_clk_rate = clk_get_rate(&clk);
debug("IWDG init done\n");
dev_dbg(dev, "IWDG init done\n");
return 0;
}