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remoteproc: ti_k3_arm64: Program CNTFID0 register in GTC

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ARMv8's generic timer[1] picks up it's graycode from GTC. However,
the frequency of the GTC is supposed to be programmed in CNTFID0[2]
register prior to enabling the GTC in CNTCR[3] register.

In K3 architecture, GTC provides a central time to many parts of the
SoC including graycode to the generic timer in the ARMv8 subsystem.
However, due to the central nature and the need to enable the counter
early in the boot process, the R5 based u-boot enables GTC and
programs it's frequency based on central needs of the system. This
may not be a constant 200MHz based on the system. The bootloader is
supposed to program the FID0 register with the correct frequency it
has sourced for GTC from the central system controller OR from PLLs
as appropriate, and TF-A is supposed[4] to use that as the frequency for
it's local timer.

Currently we are programming just the CNTCR[3] register to enable the
GTC, however we dont let TF-A know the frequency that GTC is actually
running at. A mismatch in programmed frequency and what we program for
generic timer will, as we can imagine, all kind of weird mayhem.

So, program the CNTFID0 register with the clock frequency. Note:
assigned-clock-rates should have set the clock frequency, so the only
operation we need to explicitly do is to retrieve the frequency and
program it in FID0 register.

Since the valid in K3 for GTC clock frequencies are < U32_MAX, we can
just cast the ulong and continue.

[1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary
[2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0
[3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr
[4] 6a22d9ea3c

Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Nishanth Menon 2021-01-06 13:20:32 -06:00 committed by Lokesh Vutla
parent 965db9fb0c
commit ea3f534806
1 changed files with 15 additions and 0 deletions
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15
drivers/remoteproc/ti_k3_arm64_rproc.c
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@ -23,6 +23,7 @@
#define INVALID_ID 0xffff
#define GTC_CNTCR_REG 0x0
#define GTC_CNTFID0_REG 0x20
#define GTC_CNTR_EN 0x3
/**
@ -31,6 +32,7 @@
* @rproc_rst: rproc reset control data
* @sci: Pointer to TISCI handle
* @tsp: TISCI processor control helper structure
* @gtc_clk: GTC clock description
* @gtc_base: Timer base address.
*/
struct k3_arm64_privdata {
@ -38,6 +40,7 @@ struct k3_arm64_privdata {
struct power_domain gtc_pwrdmn;
struct reset_ctl rproc_rst;
struct ti_sci_proc tsp;
struct clk gtc_clk;
void *gtc_base;
};
@ -73,6 +76,7 @@ static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
static int k3_arm64_start(struct udevice *dev)
{
struct k3_arm64_privdata *rproc = dev_get_priv(dev);
ulong gtc_rate;
int ret;
dev_dbg(dev, "%s\n", __func__);
@ -83,6 +87,11 @@ static int k3_arm64_start(struct udevice *dev)
return ret;
}
gtc_rate = clk_get_rate(&rproc->gtc_clk);
dev_dbg(dev, "GTC RATE= %d\n", (u32) gtc_rate);
/* Store the clock frequency down for GTC users to pick up */
writel((u32)gtc_rate, rproc->gtc_base + GTC_CNTFID0_REG);
/* Enable the timer before starting remote core */
writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);
@ -169,6 +178,12 @@ static int k3_arm64_of_to_priv(struct udevice *dev,
return ret;
}
ret = clk_get_by_index(dev, 0, &rproc->gtc_clk);
if (ret) {
dev_err(dev, "clk_get failed: %d\n", ret);
return ret;
}
ret = reset_get_by_index(dev, 0, &rproc->rproc_rst);
if (ret) {
dev_err(dev, "reset_get() failed: %d\n", ret);