aspeed: Add AST2600 platform support
Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
This commit is contained in:
Chia-Wei, Wang
Tom Rini
parent
ec55a1df39
commit
4a84cf06aa
23
arch/arm/include/asm/arch-aspeed/boot0.h
Normal file
23
arch/arm/include/asm/arch-aspeed/boot0.h
Normal file
@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#ifndef _ASM_ARCH_BOOT0_H
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#define _ASM_ARCH_BOOT0_H
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_start:
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ARM_VECTORS
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.word 0x0 /* key location */
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.word 0x0 /* start address of image */
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.word 0xfc00 /* maximum image size: 63KB */
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.word 0x0 /* signature address */
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.word 0x0 /* header revision ID low */
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.word 0x0 /* header revision ID high */
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.word 0x0 /* reserved */
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.word 0x0 /* checksum */
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.word 0x0 /* BL2 secure header */
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.word 0x0 /* public key or digest offset for BL2 */
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#endif
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@ -13,6 +13,11 @@
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#define ASPEED_DRAM_BASE 0x80000000
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#define ASPEED_SRAM_BASE 0x1e720000
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#define ASPEED_SRAM_SIZE 0x9000
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#elif defined(CONFIG_ASPEED_AST2600)
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#define ASPEED_MAC_COUNT 4
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#define ASPEED_DRAM_BASE 0x80000000
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#define ASPEED_SRAM_BASE 0x10000000
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#define ASPEED_SRAM_SIZE 0x10000
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#else
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#err "Unrecognized Aspeed platform."
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#endif
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@ -9,6 +9,11 @@ config SYS_SOC
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config SYS_TEXT_BASE
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default 0x00000000
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choice
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prompt "Aspeed SoC select"
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depends on ARCH_ASPEED
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default ASPEED_AST2500
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config ASPEED_AST2500
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bool "Support Aspeed AST2500 SoC"
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depends on DM_RESET
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@ -18,6 +23,21 @@ config ASPEED_AST2500
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It is used as Board Management Controller on many server boards,
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which is enabled by support of LPC and eSPI peripherals.
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config ASPEED_AST2600
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bool "Support Aspeed AST2600 SoC"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select SYS_ARCH_TIMER
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select SUPPORT_SPL
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select ENABLE_ARM_SOC_BOOT0_HOOK
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help
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The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU.
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It is used as Board Management Controller on many server boards,
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which is enabled by support of LPC and eSPI peripherals.
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endchoice
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source "arch/arm/mach-aspeed/ast2500/Kconfig"
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source "arch/arm/mach-aspeed/ast2600/Kconfig"
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endif
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@ -4,3 +4,4 @@
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obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
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obj-$(CONFIG_ASPEED_AST2500) += ast2500/
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obj-$(CONFIG_ASPEED_AST2600) += ast2600/
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17
arch/arm/mach-aspeed/ast2600/Kconfig
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17
arch/arm/mach-aspeed/ast2600/Kconfig
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@ -0,0 +1,17 @@
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if ASPEED_AST2600
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config SYS_CPU
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default "armv7"
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config TARGET_EVB_AST2600
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bool "EVB-AST2600"
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depends on ASPEED_AST2600
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help
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EVB-AST2600 is Aspeed evaluation board for AST2600A0 chip.
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It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
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4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot,
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20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs.
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source "board/aspeed/evb_ast2600/Kconfig"
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endif
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2
arch/arm/mach-aspeed/ast2600/Makefile
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2
arch/arm/mach-aspeed/ast2600/Makefile
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@ -0,0 +1,2 @@
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obj-y += lowlevel_init.o board_common.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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105
arch/arm/mach-aspeed/ast2600/board_common.c
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105
arch/arm/mach-aspeed/ast2600/board_common.c
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@ -0,0 +1,105 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/arch/timer.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <dm/uclass.h>
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#include <asm/arch/scu_ast2600.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Memory Control registers */
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#define MCR_BASE 0x1e6e0000
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#define MCR_CONF (MCR_BASE + 0x004)
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/* bit fields of MCR_CONF */
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#define MCR_CONF_ECC_EN BIT(7)
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#define MCR_CONF_VGA_MEMSZ_MASK GENMASK(3, 2)
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#define MCR_CONF_VGA_MEMSZ_SHIFT 2
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#define MCR_CONF_MEMSZ_MASK GENMASK(1, 0)
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#define MCR_CONF_MEMSZ_SHIFT 0
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int dram_init(void)
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{
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int ret;
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struct udevice *dev;
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struct ram_info ram;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("cannot get DRAM driver\n");
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("cannot get DRAM information\n");
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return ret;
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}
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gd->ram_size = ram.size;
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return 0;
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}
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int board_init(void)
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{
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int i = 0, rc;
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struct udevice *dev;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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while (1) {
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rc = uclass_get_device(UCLASS_MISC, i++, &dev);
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if (rc)
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break;
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}
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return 0;
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}
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void board_add_ram_info(int use_default)
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{
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int rc;
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uint32_t conf;
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uint32_t ecc, act_size, vga_rsvd;
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struct udevice *scu_dev;
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struct ast2600_scu *scu;
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rc = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
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if (rc) {
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debug("%s: cannot find SCU device, rc=%d\n", __func__, rc);
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return;
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}
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scu = devfdt_get_addr_ptr(scu_dev);
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if (IS_ERR_OR_NULL(scu)) {
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debug("%s: cannot get SCU address pointer\n", __func__);
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return;
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}
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conf = readl(MCR_CONF);
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ecc = conf & MCR_CONF_ECC_EN;
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act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT);
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vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT);
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/* no VGA reservation if efuse VGA disable bit is set */
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if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA)
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vga_rsvd = 0;
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printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
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vga_rsvd, (ecc) ? "on" : "off");
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}
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void enable_caches(void)
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{
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/* get rid of the warning message */
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}
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233
arch/arm/mach-aspeed/ast2600/lowlevel_init.S
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233
arch/arm/mach-aspeed/ast2600/lowlevel_init.S
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@ -0,0 +1,233 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) ASPEED Technology Inc.
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*/
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#include <config.h>
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#include <asm/armv7.h>
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#include <linux/linkage.h>
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#include <asm/arch/scu_ast2600.h>
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/* SCU register offsets */
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#define SCU_BASE 0x1e6e2000
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#define SCU_PROT_KEY1 (SCU_BASE + 0x000)
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#define SCU_PROT_KEY2 (SCU_BASE + 0x010)
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#define SCU_SMP_BOOT (SCU_BASE + 0x180)
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#define SCU_HWSTRAP1 (SCU_BASE + 0x510)
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#define SCU_CA7_PARITY_CHK (SCU_BASE + 0x820)
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#define SCU_CA7_PARITY_CLR (SCU_BASE + 0x824)
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#define SCU_MMIO_DEC (SCU_BASE + 0xc24)
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/* FMC SPI register offsets */
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#define FMC_BASE 0x1e620000
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#define FMC_CE0_CTRL (FMC_BASE + 0x010)
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#define FMC_SW_RST_CTRL (FMC_BASE + 0x050)
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#define FMC_WDT1_CTRL_MODE (FMC_BASE + 0x060)
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#define FMC_WDT2_CTRL_MODE (FMC_BASE + 0x064)
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/*
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* The SMP mailbox provides a space with few instructions in it
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* for secondary cores to execute on and wait for the signal of
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* SMP core bring up.
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*
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* SMP mailbox
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* +----------------------+
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* | |
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* | mailbox insn. for |
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* | cpuN polling SMP go |
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* | |
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* +----------------------+ 0xC
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* | mailbox ready signal |
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* +----------------------+ 0x8
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* | cpuN GO signal |
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* +----------------------+ 0x4
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* | cpuN entrypoint |
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* +----------------------+ SMP_MAILBOX_BASE
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*/
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#define SMP_MBOX_BASE (SCU_SMP_BOOT)
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#define SMP_MBOX_FIELD_ENTRY (SMP_MBOX_BASE + 0x0)
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#define SMP_MBOX_FIELD_GOSIGN (SMP_MBOX_BASE + 0x4)
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#define SMP_MBOX_FIELD_READY (SMP_MBOX_BASE + 0x8)
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#define SMP_MBOX_FIELD_POLLINSN (SMP_MBOX_BASE + 0xc)
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.macro scu_unlock
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movw r0, #(SCU_UNLOCK_KEY & 0xffff)
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movt r0, #(SCU_UNLOCK_KEY >> 16)
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ldr r1, =SCU_PROT_KEY1
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str r0, [r1]
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ldr r1, =SCU_PROT_KEY2
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str r0, [r1]
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.endm
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.macro timer_init
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ldr r1, =SCU_HWSTRAP1
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ldr r1, [r1]
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and r1, #0x700
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lsr r1, #0x8
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/* 1.2GHz */
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cmp r1, #0x0
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movweq r0, #0x8c00
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movteq r0, #0x4786
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/* 1.6GHz */
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cmp r1, #0x1
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movweq r0, #0x1000
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movteq r0, #0x5f5e
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/* 1.2GHz */
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cmp r1, #0x2
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movweq r0, #0x8c00
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movteq r0, #0x4786
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/* 1.6GHz */
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cmp r1, #0x3
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movweq r0, #0x1000
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movteq r0, #0x5f5e
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/* 800MHz */
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cmp r1, #0x4
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movwge r0, #0x0800
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movtge r0, #0x2faf
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mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ
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.endm
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.globl lowlevel_init
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lowlevel_init:
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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mov pc, lr
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#else
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/* setup ARM arch timer frequency */
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timer_init
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/* reset SMP mailbox as early as possible */
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mov r0, #0x0
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ldr r1, =SMP_MBOX_FIELD_READY
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str r0, [r1]
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/* set ACTLR.SMP to enable cache use */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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/*
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* we treat cpu0 as the primary core and
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* put secondary core (cpuN) to sleep
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*/
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mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register
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ands r0, #0xff @; Mask off, leaving the CPU ID field
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movw r2, #0xab00
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movt r2, #0xabba
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orr r2, r0
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beq do_primary_core_setup
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/* hold cpuN until mailbox is ready */
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poll_mailbox_ready:
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wfe
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ldr r0, =SMP_MBOX_FIELD_READY
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ldr r0, [r0]
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movw r1, #0xcafe
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movt r1, #0xbabe
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cmp r1, r0
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bne poll_mailbox_ready
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/* parameters for relocated SMP go polling insn. */
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ldr r0, =SMP_MBOX_FIELD_GOSIGN
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ldr r1, =SMP_MBOX_FIELD_ENTRY
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/* no return */
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ldr pc, =SMP_MBOX_FIELD_POLLINSN
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do_primary_core_setup:
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scu_unlock
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/* MMIO decode setting */
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ldr r0, =SCU_MMIO_DEC
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mov r1, #0x2000
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str r1, [r0]
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/* enable CA7 cache parity check */
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mov r0, #0
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ldr r1, =SCU_CA7_PARITY_CLR
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str r0, [r1]
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mov r0, #0x1
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ldr r1, =SCU_CA7_PARITY_CHK
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str r0, [r1]
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/* do not fill FMC50[1] if boot from eMMC */
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ldr r0, =SCU_HWSTRAP1
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ldr r1, [r0]
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ands r1, #0x04
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bne skip_fill_wip_bit
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/* fill FMC50[1] for waiting WIP idle */
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mov r0, #0x02
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ldr r1, =FMC_SW_RST_CTRL
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str r0, [r1]
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skip_fill_wip_bit:
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/* disable FMC WDT for SPI address mode detection */
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mov r0, #0
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ldr r1, =FMC_WDT1_CTRL_MODE
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str r0, [r1]
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/* relocate mailbox insn. for cpuN polling SMP go signal */
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adrl r0, mailbox_insn
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adrl r1, mailbox_insn_end
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ldr r2, =#SMP_MBOX_FIELD_POLLINSN
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relocate_mailbox_insn:
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ldr r3, [r0], #0x4
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str r3, [r2], #0x4
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cmp r0, r1
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bne relocate_mailbox_insn
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/* reset SMP go sign */
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mov r0, #0
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ldr r1, =SMP_MBOX_FIELD_GOSIGN
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str r0, [r1]
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/* notify cpuN mailbox is ready */
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movw r0, #0xCAFE
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movt r0, #0xBABE
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ldr r1, =SMP_MBOX_FIELD_READY
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str r0, [r1]
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sev
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/* back to arch calling code */
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mov pc, lr
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/*
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* insn. inside mailbox to poll SMP go signal.
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*
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* Note that as this code will be relocated, any
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* pc-relative assembly should NOT be used.
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*/
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mailbox_insn:
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/*
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* r0 ~ r3 are parameters:
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* r0 = SMP_MBOX_FIELD_GOSIGN
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* r1 = SMP_MBOX_FIELD_ENTRY
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* r2 = per-cpu go sign value
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* r3 = no used now
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*/
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poll_mailbox_smp_go:
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wfe
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ldr r4, [r0]
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cmp r2, r4
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bne poll_mailbox_smp_go
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/* SMP GO signal confirmed, release cpuN */
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ldr pc, [r1]
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mailbox_insn_end:
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/* should never reach */
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b .
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#endif
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55
arch/arm/mach-aspeed/ast2600/spl.c
Normal file
55
arch/arm/mach-aspeed/ast2600/spl.c
Normal file
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <spl.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/arch/scu_ast2600.h>
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DECLARE_GLOBAL_DATA_PTR;
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|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
spl_early_init();
|
||||
preloader_console_init();
|
||||
timer_init();
|
||||
dram_init();
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
|
||||
{
|
||||
/*
|
||||
* When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff
|
||||
* to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL
|
||||
* has been located in SPI for XIP. In this case, the load buffer for
|
||||
* SPL image loading will be set to the remapped address of the next
|
||||
* BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR
|
||||
*/
|
||||
return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* boot linux */
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
12
board/aspeed/evb_ast2600/Kconfig
Normal file
12
board/aspeed/evb_ast2600/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_EVB_AST2600
|
||||
|
||||
config SYS_BOARD
|
||||
default "evb_ast2600"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "aspeed"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "evb_ast2600"
|
||||
|
||||
endif
|
||||
1
board/aspeed/evb_ast2600/Makefile
Normal file
1
board/aspeed/evb_ast2600/Makefile
Normal file
@ -0,0 +1 @@
|
||||
obj-y += evb_ast2600.o
|
||||
5
board/aspeed/evb_ast2600/evb_ast2600.c
Normal file
5
board/aspeed/evb_ast2600/evb_ast2600.c
Normal file
@ -0,0 +1,5 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
#include <common.h>
|
||||
@ -12,6 +12,7 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/wdt.h>
|
||||
#include <linux/err.h>
|
||||
#include <hang.h>
|
||||
|
||||
static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
||||
{
|
||||
@ -33,11 +34,15 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
||||
return -EPROTONOSUPPORT;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
ret = wdt_expire_now(wdt, reset_mode);
|
||||
if (ret) {
|
||||
debug("Sysreset failed: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
hang();
|
||||
#endif
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
||||
16
include/configs/evb_ast2600.h
Normal file
16
include/configs/evb_ast2600.h
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <configs/aspeed-common.h>
|
||||
|
||||
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* Memory Info */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x83000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user