Benoît Thébaudeau d5fe220df4 mx5 clocks: Fix MXC_FEC_CLK ... The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>		2012-10-15 11:54:12 -07:00
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cpu	mx5 clocks: Fix MXC_FEC_CLK	2012-10-15 11:54:12 -07:00
dts	tegra: fdt: Add NAND controller binding and definitions	2012-09-07 13:54:30 -07:00
imx-common	mx5/6: Define default SoC input clock frequencies	2012-10-15 11:54:10 -07:00
include/asm	mx5 clocks: Fix get_lp_apm()	2012-10-15 11:54:11 -07:00
lib	serial: Remove CONFIG_SERIAL_MULTI from remaining sources	2012-10-15 11:53:59 -07:00
config.mk	arm: work around assembler bug	2012-10-04 14:19:04 +02:00