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mx5/6: Define default SoC input clock frequencies

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Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Benoît Thébaudeau 2012-09-27 10:19:58 +00:00 committed by Tom Rini
parent e7bed5c2b3
commit 833b6435de
16 changed files with 64 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
arch/arm/cpu/armv7/mx5/clock.c
View File

@ -69,7 +69,7 @@ struct fixed_pll_mfd {
};
const struct fixed_pll_mfd fixed_mfd[] = {
{CONFIG_SYS_MX5_HCLK, 24 * 16},
{MXC_HCLK, 24 * 16},
};
struct pll_param {
@ -242,7 +242,7 @@ u32 get_mcu_main_clk(void)
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
MXC_CCM_CACRR_ARM_PODF_OFFSET;
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
return freq / (reg + 1);
}
@ -255,14 +255,14 @@ u32 get_periph_clk(void)
reg = __raw_readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
reg = __raw_readl(&mxc_ccm->cbcmr);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
case 1:
return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
default:
return 0;
}
@ -317,16 +317,13 @@ static u32 get_uart_clk(void)
switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
case 0x0:
freq = decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK],
CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK],
CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
break;
default:
return 66500000;
@ -353,9 +350,9 @@ static u32 get_lp_apm(void)
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
ret_val = CONFIG_SYS_MX5_HCLK;
ret_val = MXC_HCLK;
else
ret_val = ((32768 * 1024));
ret_val = MXC_CLK32 * 1024;
return ret_val;
}
@ -378,18 +375,15 @@ static u32 imx_get_cspiclk(void)
switch (clk_sel) {
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_SYS_MX5_HCLK) /
ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
CONFIG_SYS_MX5_HCLK) /
ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
CONFIG_SYS_MX5_HCLK) /
ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
@ -443,7 +437,7 @@ static u32 get_ddr_clk(void)
u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
MXC_CCM_CBCDR_DDR_PODF_OFFSET;
ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
ret_val /= ddr_clk_podf + 1;
return ret_val;
@ -489,8 +483,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_CSPI_CLK:
return imx_get_cspiclk();
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_SYS_MX5_HCLK);
return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
case MXC_SATA_CLK:
return get_ahb_clk();
case MXC_DDR_CLK:
@ -875,14 +868,14 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
printf("PLL1 %8d MHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
printf("PLL2 %8d MHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
printf("PLL3 %8d MHz\n", freq / 1000000);
#ifdef CONFIG_MX53
freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
printf("PLL4 %8d MHz\n", freq / 1000000);
#endif

20
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -110,7 +110,7 @@ static u32 get_mcu_main_clk(void)
reg = __raw_readl(&imx_ccm->cacrr);
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_SYS, MXC_HCLK);
return freq / (reg + 1);
}
@ -127,11 +127,11 @@ u32 get_periph_clk(void)
switch (reg) {
case 0:
freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 1:
case 2:
freq = CONFIG_SYS_MX6_HCLK;
freq = MXC_HCLK;
break;
default:
break;
@ -143,7 +143,7 @@ u32 get_periph_clk(void)
switch (reg) {
case 0:
freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
freq = PLL2_PFD2_FREQ;
@ -239,7 +239,7 @@ static u32 get_emi_slow_clk(void)
root_freq = get_axi_clk();
break;
case 1:
root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 2:
root_freq = PLL2_PFD2_FREQ;
@ -311,7 +311,7 @@ u32 imx_get_uartclk(void)
u32 imx_get_fecclk(void)
{
return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
return decode_pll(PLL_ENET, MXC_HCLK);
}
int enable_sata_clock(void)
@ -392,13 +392,13 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_SYS, MXC_HCLK);
printf("PLL_SYS %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_BUS, MXC_HCLK);
printf("PLL_BUS %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
printf("PLL_OTG %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
freq = decode_pll(PLL_ENET, MXC_HCLK);
printf("PLL_NET %8d MHz\n", freq / 1000000);
printf("\n");

12
arch/arm/imx-common/timer.c
View File

@ -27,6 +27,7 @@
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
/* General purpose timers registers */
struct mxc_gpt {
@ -44,7 +45,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
#define CLK_32KHZ 32768 /* 32Khz input */
DECLARE_GLOBAL_DATA_PTR;
@ -54,14 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CLK_32KHZ);
do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
usec = usec * CLK_32KHZ + 999999;
usec = usec * MXC_CLK32 + 999999;
do_div(usec, 1000000);
return usec;
@ -86,7 +86,7 @@ int timer_init(void)
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
val = __raw_readl(&cur_gpt->counter);
lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
return 0;
@ -114,7 +114,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
@ -145,5 +145,5 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
return CLK_32KHZ;
return MXC_CLK32;
}

14
arch/arm/include/asm/arch-mx5/clock.h
View File

@ -24,6 +24,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#include <common.h>
#ifdef CONFIG_SYS_MX5_HCLK
#define MXC_HCLK CONFIG_SYS_MX5_HCLK
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_SYS_MX5_CLK32
#define MXC_CLK32 CONFIG_SYS_MX5_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_AHB_CLK,

14
arch/arm/include/asm/arch-mx6/clock.h
View File

@ -24,6 +24,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#include <common.h>
#ifdef CONFIG_SYS_MX6_HCLK
#define MXC_HCLK CONFIG_SYS_MX6_HCLK
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_SYS_MX6_CLK32
#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_PER_CLK,

2
board/freescale/mx53loco/mx53loco.c
View File

@ -394,7 +394,7 @@ static int power_init(void)
static void clock_1GHz(void)
{
int ret;
u32 ref_clk = CONFIG_SYS_MX5_HCLK;
u32 ref_clk = MXC_HCLK;
/*
* After increasing voltage to 1.25V, we can switch
* CPU clock to 1GHz and DDR to 400MHz safely

3
include/configs/ima3-mx53.h
View File

@ -28,9 +28,6 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx51_efikamx.h
View File

@ -37,8 +37,6 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx51evk.h
View File

@ -28,8 +28,6 @@
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx53ard.h
View File

@ -24,8 +24,6 @@
#define CONFIG_MX53
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx53evk.h
View File

@ -24,8 +24,6 @@
#define CONFIG_MX53
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx53loco.h
View File

@ -25,8 +25,6 @@
#define CONFIG_MX53
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO

2
include/configs/mx53smd.h
View File

@ -24,8 +24,6 @@
#define CONFIG_MX53
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx6qarm2.h
View File

@ -23,8 +23,6 @@
#define __CONFIG_H
#define CONFIG_MX6Q
#define CONFIG_SYS_MX6_HCLK 24000000
#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/mx6qsabrelite.h
View File

@ -23,8 +23,6 @@
#define __CONFIG_H
#define CONFIG_MX6Q
#define CONFIG_SYS_MX6_HCLK 24000000
#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

2
include/configs/vision2.h
View File

@ -30,8 +30,6 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO