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mx5 clocks: Fix get_lp_apm()

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If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
 - on i.MX51, this clock comes from the output of the FPM,
 - on i.MX53, this clock comes from the output of PLL4.

This patch fixes the code accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-09-27 10:22:37 +00:00 committed by Tom Rini
parent 649dc8abd9
commit b94792982f
2 changed files with 38 additions and 1 deletions
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24
arch/arm/cpu/armv7/mx5/clock.c
View File

@ -221,6 +221,24 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
return ret;
}
#ifdef CONFIG_MX51
/*
* This function returns the Frequency Pre-Multiplier clock.
*/
static u32 get_fpm(void)
{
u32 mult;
u32 ccr = readl(&mxc_ccm->ccr);
if (ccr & MXC_CCM_CCR_FPM_MULT)
mult = 1024;
else
mult = 512;
return MXC_CLK32 * mult;
}
#endif
/*
* Get mcu main rate
*/
@ -326,7 +344,11 @@ static u32 get_lp_apm(void)
u32 ccsr = readl(&mxc_ccm->ccsr);
if (ccsr & MXC_CCM_CCSR_LP_APM)
ret_val = MXC_CLK32 * 1024;
#if defined(CONFIG_MX51)
ret_val = get_fpm();
#elif defined(CONFIG_MX53)
ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
#endif
else
ret_val = MXC_HCLK;

15
arch/arm/include/asm/arch-mx5/crm_regs.h
View File

@ -82,6 +82,21 @@ struct mxc_ccm_reg {
u32 cmeor;
};
/* Define the bits in register CCR */
#define MXC_CCM_CCR_COSC_EN (0x1 << 12)
#if defined(CONFIG_MX51)
#define MXC_CCM_CCR_FPM_MULT (0x1 << 11)
#endif
#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10)
#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9)
#if defined(CONFIG_MX51)
#define MXC_CCM_CCR_FPM_EN (0x1 << 8)
#endif
#define MXC_CCM_CCR_OSCNT_OFFSET 0
#define MXC_CCM_CCR_OSCNT_MASK 0xFF
#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF)
#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF)
/* Define the bits in register CCSR */
#if defined(CONFIG_MX51)
#define MXC_CCM_CCSR_LP_APM (0x1 << 9)