Prepare for 1.3.0-rc3 release

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,686 @@
+commit 68f14f77ca5fe5f9cc025c8cae101671f628309f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Sep 29 13:41:37 2007 +0200
+
+    Fix warning differ in signedness in cpu/pxa/mmc.c
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit fc19e36f741e8bc727c0a330170b3b5db90399ef
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Oct 13 23:51:14 2007 +0200
+
+    Fix warning differ in signedness in board/mpl/vcma9/vcma9.c
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit de74b9eeacccaf0a42e5ecc9ae79a88f7a311296
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Oct 13 21:15:39 2007 +0200
+
+    Coding Style cleanup.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e1893815b0999410d7a327589611c7b38e95299e
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Oct 12 15:49:39 2007 +0200
+
+    GP3 SSA: enable RTC
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8002012041f1ff9f997a5727abe5015f70cd2e46
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Tue Oct 9 13:58:24 2007 +0200
+
+    [ads5121] EEPROM support added.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 7b624ad254b97e5a25dca2304a398b64aeedaffe
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Sat Oct 6 18:55:35 2007 +0200
+
+    AVR32: Initialize bi_flash* in board_init_r
+
+    The ATSTK1000-specific flash driver intializes bi_flashstart,
+    bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI
+    driver, don't.
+
+    Initialize these in board_init_r instead so that things will still be
+    set up correctly when we switch to the CFI driver.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 2b2a587d6d3076387d22ac740f44044bf46e2cb8
+Author: Marian Balakowicz <m8@semihalf.com>
+Date:	Fri Oct 5 10:40:54 2007 +0200
+
+    tqm5200: Fix CONFIG_CMD_PCI typo in board config file.
+
+    Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 92869195ef8210758d2176230c0a36897afd50ed
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Fri Oct 5 09:46:06 2007 +0200
+
+    CM5200: Fix missing null-termination in hostname manipulation code
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 9add9884b1fddc34ca186e00a2f868ccd5d02d87
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Tue Oct 2 19:09:01 2007 +0200
+
+    Fix memtest breakage
+
+    CFG_MEMTEST_START uses weird magic involving gd, which fails to
+    compile. Use hardcoded values instead (we actually know how much RAM
+    we have on board.)
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 738815c0cc44aa329097f868dc1efc49ede9c5ba
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 2 11:44:46 2007 +0200
+
+    ppc4xx: Coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 87c1833a39e944db66385286fd5e28f9b3fcdd50
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 2 11:44:19 2007 +0200
+
+    ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2db64784061bfc34f4ba70ef1d2fbe7133b55670
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Mon Oct 1 09:51:50 2007 +0200
+
+    Program EPLD to force full duplex mode for PHY.
+
+    EPLD forces modes of PHY operation. By default full duplex is turned off.
+    This fix turns it on.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 86ec86c04326c3913178a7679aa910de071da75d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Sep 27 23:27:47 2007 +0200
+
+    Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3e954beb614b5b190d7f4f4c3b641437a0132e35
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Sep 11 14:12:55 2007 +0200
+
+    ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Sep 25 15:48:05 2007 -0600
+
+    Fpga: fix incorrect test of CFG_FPGA_XILINX macro
+
+    CFG_FPGA_XILINX is a bit value used to test against the value in
+    CONFIG_FPGA.  Testing for a value will always return TRUE.	I don't
+    think that is the intention in this code.
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 853643d8cf2ca80cb2e25c53ad5dc580abafe166
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:41:30 2007 +0200
+
+    [FIX] change command handling and removing code violation
+
+commit f240356507038e5ce55e8a24cb2607e9eae6d10c
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:36:06 2007 +0200
+
+    [FIX] change sets of commands
+    because changing of command handling brings
+    compilation problems
+
+commit cb1bc63b75a232571eb69aa2c8aa919321655845
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:30:42 2007 +0200
+
+    [FIX] Email reparation & Copyright
+    Both codes are written by myself without any
+    support from CTU
+
+commit 0731cbae6c2feab93b244d83fd6a43f5cc9bf852
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:25:11 2007 +0200
+
+    [PATCH] Change macro name for UartLite
+    because PowerPC 405 can use UartLite as console
+
+commit 1c1100d2fcf46b9d11dcf78d6e5aea75e2e8b716
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:21:19 2007 +0200
+
+    [PATCH] Add support for design without interrupt controller
+    Polling timer
+
+commit 0731933ec8ec45d02ba89b52df673d526873cdde
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:19:48 2007 +0200
+
+    [FIX] resolve problem with cpu without barrel shifter
+
+commit db14d77995ce515b728b178b63f82babe60e3d56
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:18:46 2007 +0200
+
+    [FIX] repair email address
+
+commit 481d4328618804add1f818a6c96296121cd0528e
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:17:42 2007 +0200
+
+    [FIX] repair MFSL commands
+
+commit b90c045f035c3cc9b5d2edaed6048dfb74e40763
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Sep 24 00:08:37 2007 +0200
+
+    synchronizition with mainline
+
+commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Sep 20 00:04:14 2007 +0200
+
+    v1.3.0-rc2
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 135e19bc2773ebca487e9a8371f67e1ba202313a
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 18 21:36:35 2007 +0200
+
+    Avoid compiler warning.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8a783a65851bc7421ab69f442261215e21b8891a
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Sep 18 12:24:57 2007 -0600
+
+    Bugfix: remove embedded null (\0) from CFG_BOOTFILE macro in TQM8540_config
+
+    /bin/bash and /bin/dash (which /bin/sh is linked to on ubuntu) handle embedded
+    nulls in a string differently.  For example, the following statement:
+	echo "this is a string\0" > afile
+    Will produce the following with /bin/bash:
+	"this is a string\0"
+    But with /bin/dash, will produce:
+	"this is a string
+
+    Bug fixed by moving the embedded null out of the makefile and into the
+    config header.  Also renamed the macro to avoid usage colision with the same
+    macro used by other board ports.
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit f8d3ca7b6fa322ac57e8e831f07dbeea039a9f35
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 18 17:40:27 2007 +0200
+
+    MCC200: fix build warning
+
+    The MCC200 board config file includes version.h for some customer-
+    specific setting, which causes warnings with "make depend"; build
+    version.h before depend.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit bd86220f58b99d6896198c385fda132f0c980915
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Tue Sep 18 13:07:54 2007 +0100
+
+    Move coloured led API to status_led.h
+    Improve indentation in drivers/at45.c
+
+commit e80e585b00fbbab7ad1bf71619741f2c5b029ab7
+Author: Eirik Aanonsen <eaa@wprmedical.com>
+Date:	Tue Sep 18 08:47:20 2007 +0200
+
+    Update atstk1002 bootargs.
+
+    Updates to atstk1002 U-Boot header file:
+    - Changed bootargs:
+	* Set the bootargs for at1002 to point to the SD-card partition instead
+	* ... of the boot flash.
+	* Removing the rootfstype since that argument are not needed.
+
+    Signed-off-by: Eirik Aanonsen <eaa@wprmedical.com>
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit a4f3aab6dfbed6c29367c688bfb8a47eef62c225
+Author: Eirik Aanonsen <eaa@wprmedical.com>
+Date:	Wed Sep 12 13:32:37 2007 +0200
+
+    Add some comments to clocks in atstk1002.h
+
+    This patch applies some clarifying comments to how the different
+    clocks are setup according to atstk1002.h Some of the previous
+    comments where stating wrongful information.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 97213f32416ead885deafea86774e912ffd60ad0
+Author: David Saada <David.Saada@ecitele.com>
+Date:	Mon Sep 17 17:04:47 2007 +0200
+
+    Description: Add NEC's PCI OHCI module ID to the USB OHCI driver
+
+    Signed-off-by: David Saada <david.saada@ecitele.com>
+
+commit 30363e98fa470fbecea5e8bc0f1443352754f303
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Sep 17 08:20:47 2007 +0200
+
+    Small whitespace cleanup of OneNAND patch
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d7e8ce101a4a45ed6ed45739fc2de5f87b13f7f1
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Mon Sep 10 17:15:14 2007 +0900
+
+    OneNAND support (take #2)
+
+    [PATCH 3/3] OneNAND support (take #2)
+
+    OneNAND support at U-Boot
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 17aa2800457df0c06b41516f46f126712c196219
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Mon Sep 10 17:14:34 2007 +0900
+
+    OneNAND support (take #2)
+
+    [PATCH 2/3] OneNAND support (take #2)
+
+    OneNAND support at U-Boot
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 916527f4809a7bcd811f1f1daf34af184e31dd8c
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Mon Sep 10 17:13:49 2007 +0900
+
+    OneNAND support (take #2)
+
+    [PATCH 1/3] OneNAND support (take #2)
+
+    OneNAND support at U-Boot
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 67c31036acaaaa992fc346cc89db0909a7e733c4
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Sep 16 17:10:04 2007 +0200
+
+    TQM8xx[LM]: Fix broken environment alignment.
+
+    With recent toolchains, the environment sectors were no longer aligned to
+    sector boundaries. The reason was a combination of two bugs:
+
+    1) common/environment.c assumed that CONFIG_TQM8xxL would be defined
+       for all TQM8xxL and TQM8xxM boards. But "include/common.h", where
+       this gets defined, is not included here (and cannot be included
+       without causing lots of problems).
+
+       Added a new #define CFG_USE_PPCENV for all boards which really
+       want to put the environment is a ".ppcenv" section.
+
+    2) The linker scripts just include environment.o, silently assuming
+       that the objects in that file are really in the order in which
+       they are coded in the C file, i. e. "environment" first, then
+       "redundand_environment", and "env_size" last. However, current
+       toolchains (GCC-4.x) reorder the objects, causing the environment
+       data not to start on a flash sector boundary:
+
+       Instead of:					we got:
+
+	40008000 T environment			40008000 T env_size
+	4000c000 T redundand_environment	40008004 T redundand_environment
+	40010000 T env_size			4000c004 T environment
+
+       Note: this patch fixes just the first part, and cures the alignment
+       problem by making sure that "env_size" gets placed correctly. However,
+       we still have a potential issue because primary and redundant
+       environment sectors are actually swapped, i. e. we have now:
+
+	40008000 T redundand_environment
+	4000c000 T environment
+	40010000 T env_size
+
+       This shall be fixed in the next version.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit eb6da8050797c204c9d010548424186c7ce32fc1
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Sep 16 02:39:35 2007 +0200
+
+    TQM8xx/FPS8xx: adjust flash partitions for 2.6 ARCH=powerpc kernels
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cd2d1602c54cc6957bdef3872272a4b264893960
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date:	Mon Sep 10 14:54:56 2007 -0400
+
+    Typo fix in tsec.c
+
+    Fixup for the break statement in wrong place.
+
+    [Patch by urwithsughosh@gmail.com]
+    Acked-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by:	Wolfgang Denk <wd@denx.de>
+
+commit 5bd7fe9aeb76906371f40b8fd07613f10922e3e7
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 11 17:04:00 2007 +0200
+
+    Fix do_div() usage in nand process output
+
+    Fix usage of do_div() in nand erase|read|write process output.
+
+    The last patch to nand_util.c introduced do_div() instead of libgcc's
+    implementation. But do_div() returns the quotient in its first
+    macro parameter and not as result.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit c750d2e6692a000a82f29de7bf24e3dc21239161
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Sep 12 12:36:53 2007 +0200
+
+    NAND: Add CFG_NAND_QUIET option
+
+    This config option sets the default for the progress information
+    output behavior that can also be configured through the 'quiet'
+    environment variable.
+
+    The legacy NAND code does not print the current progress info
+    on the console. So this option is for backward compatibility for
+    units that are in the field and where setting the quiet variable
+    is not an option. With CFG_NAND_QUIET set to '1' the console
+    progress info is turned off. This can still be overwritten
+    through the environment variable.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit dcb88630290d2bcd803386dd4c2be73142994c4f
+Author: Liew Tsi Chung-r5aahp <Tsi-chung.Liew@freescale.com>
+Date:	Thu Sep 13 16:06:05 2007 -0700
+
+    ColdFire: fix build error becasue of bad type of mii_init()
+
+    Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 314d5b6ce52a4ed19dd295d1364e246c5e605017
+Author: Liew Tsi Chung-r5aahp <Tsi-chung.Liew@freescale.com>
+Date:	Thu Sep 13 16:04:05 2007 -0700
+
+    ColdFire: Fix build error caused by pixis.c
+
+    Moved the #include <asm/cache.h> inside the #ifdef CONFIG_FSL_PIXIS.
+
+    Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit e21659e30660a1377c42af135a6114efe39801d9
+Author: Sam Sparks <SSparks@twacs.com>
+Date:	Fri Sep 14 11:14:42 2007 -0600
+
+    Update MPC8349ITX*_config to place config.tmp in right place.
+
+    MPC834ITX*_config does not store config.tmp at the correct locatation,
+    causing MPC8349ITXGP to have the wrong TEXT_BASE.
+
+    Signed-off-by: Sam Sparks <SSparks@twacs.com>
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 1218abf1b5817a39a82399b4b928b00750575bda
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Sep 15 20:48:41 2007 +0200
+
+    Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 66b3f24d665be678a9dbb125b1e84185400f63b5
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date:	Sat Sep 15 11:55:42 2007 +0200
+
+    Make DECLARE_GLOBAL_DATA_PTR global for DaVinci
+
+    As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not
+    function local.
+
+    Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+    [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805
+
+commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Thu Sep 13 18:21:48 2007 +0200
+
+    cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9
+
+    Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit e1f601b572db5de9aa81a0b77c68a86994fe24c4
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Thu Sep 13 16:33:59 2007 +0200
+
+    tqm5200: Restore customary env. variable boot commands for powerpc kernels
+
+    - update default definitions of kernel_addr and fdt_addr env. variables
+    - make arch/powerpc booting the default scenario
+    - update MTD partition layout to match the above
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit f34024d4a328e6edd906456da98d2c537155c4f7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Sep 12 00:48:57 2007 +0200
+
+    Fix memory corruption problem on STX GP3 SSA Board.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d94c79e47011af5e8dd10ed6163c09b4cfc743cc
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Tue Sep 11 15:35:01 2007 +0100
+
+    Final tidy
+
+commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Tue Sep 11 15:42:11 2007 +0200
+
+    [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to
+    scan on second pci bus.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 6c2f4f388e8181655ea8b69343ea00b68aa6e8d0
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Tue Sep 11 12:57:52 2007 +0200
+
+    [ppc4xx] Individual handling of sdram.c for bamboo_nand build
+
+    Bamboo has a file sdram.c which needs special treatment when building in
+    separate directory. It has to be linked to build directory otherwise it is
+    not seen.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit d45963854eff39d575124d859419bb4953ce2c87
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue Sep 11 00:37:04 2007 +0200
+
+    [FIX] Microblaze ML401 - repare FLASH handling
+
+commit 38c1ef728d19950414a8ab1ccfc53767848fa346
+Author: Sean MCGOOGAN <sean.mcgoogan@st.com>
+Date:	Mon Sep 10 16:55:59 2007 +0100
+
+    Allocate CPU Architecture Code for STMicroelectronics' ST200.
+
+    Signed-off-by: Sean McGoogan <Sean.McGoogan@st.com>
+    ---------------------------------------------------
+
+commit 754bac48156f8958d8f6a53a51eda88ab5758929
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 10 20:42:31 2007 +0200
+
+    Update version to match current state.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7a888d6b3c32a126dbb504ef146bb4c26574ca7b
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Mon Sep 10 17:39:08 2007 +0200
+
+    [MPC512x] Streamline frame handling in the FEC driver
+
+    - convert frame size settings to be derived from a single base
+    - set frame size to the recommended default value
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit e251e00d0db4b36d1d2b7e38fec43a7296b529a2
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Mon Sep 10 11:34:00 2007 +0900
+
+    Remove compiler warning: target CPU does not support interworking
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 1d9e31e04911a6bb7cc66dd91132c699101c32e2
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Sep 9 21:21:33 2007 +0200
+
+    Fix compile error in spc1920 config.
+
+    Signed-off-by: Markus Klotzb<7A>cher <mk@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a7d7eca791a37f452c9da10fef4b31dd7aa9a622
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Fri Sep 7 09:25:07 2007 -0600
+
+    Bugfix: make bootm+libfdt compile on boards with no flash
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Fri Sep 7 18:35:37 2007 +0200
+
+    [PPC440SPe] PCIe environment settings for Katmai and Yucca
+
+    - 'pciconfighost' is set by default in order to be able to scan bridges
+    behind the primary host/PCIe
+
+    - 'pciscandelay' env variable is recognized to allow for user-controlled
+    delay before the PCIe bus enumeration; some peripheral devices require a
+    significant delay before they can be scanned (e.g. LSI8408E); without the
+    delay they are not detected
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 7f1913938984ef6c6a46cb53e003719196d9c5de
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Fri Sep 7 18:20:23 2007 +0200
+
+    [PPC440SPe] Improve PCIe configuration space access
+
+    - correct configuration space mapping
+    - correct bus numbering
+    - better access to config space
+
+    Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
+    first device on the first bus. We now allow to configure up to 16 buses;
+    also, scanning for devices behind the PCIe-PCIe bridge is supported, so
+    peripheral devices farther in hierarchy can be identified.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 15ee4734e4e08003d73d9ead3ca80e2a0672e427
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Fri Sep 7 17:46:18 2007 +0200
+
+    [PPC440SPe] Convert machine check exceptions handling
+
+    Convert using fixup mechanism to suppressing MCK for the duration of config
+    read/write transaction: while fixups work fine with the case of a precise
+    exception, we identified a major drawback with this approach when there's
+    an imprecise case. In this scenario there is the following race condition:
+    the fixup is (by design) set to catch the instruction following the one
+    actually causing the exception; if an interrupt (e.g. decrementer) happens
+    between those two instructions, the ISR code is executed before the fixup
+    handler the machine check is no longer protected by the fixup handler as it
+    appears as within the ISR code. In consequence the fixup approach is being
+    phased out and replaced with explicit suppressing of MCK during a PCIe
+    config read/write cycle.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit ff7640c9ead8806b5d827f2b29f9cb2632add729
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Sep 7 17:43:36 2007 +0200
+
+    Fix typo in MAKEALL script.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 08e2e5fcd2e06670b62e1680a3934c0e55c72810
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Fri Sep 7 17:09:21 2007 +0200
+
+    [MPC512x] Proper handling of larger frames in the FEC driver
+
+    When frame larger than local RX buffer is received, it is split and handled
+    by two buffer descriptors. Prior to this patch the FEC driver discarded
+    contents of a buffer descriptor without the 'LAST' bit set, so the first
+    part of the frame was lost in case of larger frames. This fix allows to
+    safely combine the two pieces into the whole frame.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 8d17979d0359492a822a0a409d26e3a3549b4cd4
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Fri Sep 7 17:05:36 2007 +0200
+
+    [MPC512x] Correct fixup relocation
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit a89cbbd27a60e6740772000fd0688ffba1c2576a
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Sep 7 01:21:25 2007 +0200
+
+    Update CHANGELOG, minor coding style cleanup.
+
 commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3
 Author: stefano babic <sbabic@denx.de>
 Date:	Thu Aug 30 23:01:49 2007 +0200
@@ -141,6 +824,14 @@ Date:	Thu Sep 6 09:46:17 2007 -0600
 
     Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 
+commit 80767a6cead9990d9e77e62be947843c2c72f469
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Wed Sep 5 16:04:41 2007 +0100
+
+    Changed API name to coloured_led.h
+    Removed code using deprecated ifdef CONFIG_BOOTBINFUNC
+    Tidied other cpu/arm920t/start.S code
+
 commit 56a9270521baaa00e12639a978302a67f61ef060
 Author: Kumar Gala <galak@kernel.crashing.org>
 Date:	Thu Aug 30 16:18:18 2007 -0500
@@ -166,6 +857,31 @@ Date:	Thu Aug 30 01:58:48 2007 -0500
 
     Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
 
+commit 9f5c3d3720e777a572dcdc8af2008b44c7243885
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Tue Sep 4 16:18:38 2007 +0100
+
+    Add coloured led interface for ARM boards.
+    Use it in cpu/arm920t/start.S to indicate U-Boot code has been entered.
+
+commit 7462fe0d5a9d40cde083fb1a3cd73911996b5ecb
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Tue Sep 4 14:49:28 2007 +0100
+
+    Move include/led.h to board/at91rm9200dk
+
+commit 6e4bf9b24e57c15abc6542e685d06380bc64af27
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Tue Sep 4 14:25:51 2007 +0100
+
+    Ran Lindent on drivers/at45.c
+
+commit 557ab89d294f08dd532f21d19861b40093200a33
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Tue Sep 4 14:23:50 2007 +0100
+
+    Rename CONFIG_CMD_MUX to CONFIG_CMD_AT91_SPIMUX
+
 commit 81b73dec16fd1227369a191e725e10044a9d56b8
 Author: Gary Jennejohn <garyj@denx.de>
 Date:	Fri Aug 31 15:21:46 2007 +0200
@@ -206,6 +922,24 @@ Date:	Fri Aug 31 10:01:51 2007 +0200
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 696dd1307cd8e73a10e9bb3c51731bfd6f837bee
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date:	Thu Aug 30 15:03:05 2007 +0200
+
+    Reduce BOOTDELAY variable to 1 second by default for STK1002
+
+    Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit c88b6e1cbf9a8ae2a34fb602f78a1bf4e6692b6a
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date:	Thu Aug 30 15:03:04 2007 +0200
+
+    Remove double quotation marks around MAC address for STK1002
+
+    Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
 commit ff13ac8c7bbebb238e339592de765c546dba1073
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu Aug 30 14:42:15 2007 +0200
@@ -241,6 +975,20 @@ Date:	Wed Aug 29 18:26:24 2007 -0600
 
     Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 
+commit 04625764cc93ce8a61625ac19d7fe2a2ceee8143
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Aug 29 16:31:18 2007 +0200
+
+    ppc4xx: Change lwmon5 default environment to support Linux RTC
+
+    The Linux PCF8563 RTC driver doesn't do autoprobing, so we need
+    to supply the RTC I2C address as bootline parameter. This patch
+    adds support for this rtc probing parameter to the bootargs:
+
+    "rtc-pcf8563.probe=0,0x51"
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 2602a5c40ae37ab965a4e240854fdaffb51328a4
 Author: Kim Phillips <kim.phillips@freescale.com>
 Date:	Wed Aug 29 09:06:05 2007 -0500
@@ -454,6 +1202,15 @@ Date:	Tue Aug 28 17:39:14 2007 +0200
 
     Signed-off-by: Heiko Schocher <hs@denx.de>
 
+commit 2c05fd125744981e5f2828d24e66ccc20a77d25d
+Author: Semih Hazar <semih.hazar@indefia.com>
+Date:	Mon Aug 20 19:00:01 2007 +0300
+
+    AVR32: Change prototype of memset
+
+    Signed-off-by: Semih Hazar <semih.hazar@indefia.com>
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
 commit 9c02defc29b57945b600714cf61ddfd02b02fb14
 Author: Yuri Tikhonov <yur@emcraft.com>
 Date:	Sat Aug 25 05:07:16 2007 +0200
@@ -979,6 +1736,18 @@ Date:	Fri Jun 22 17:32:28 2007 +0200
     Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 78cff50edba6b1508eb15c2f53ce966ac891eb9e
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Thu Aug 16 10:46:28 2007 +0200
+
+    [FIX] Changes for bios_emulator code for others architecture
+
+commit 6e0e2253f039344f8ebd2787285fdba90e6714e8
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Thu Aug 16 10:45:09 2007 +0200
+
+    [FIX] Remove unused include file
+
 commit 9de469bd960cc1870bb40d6672ed42726b8b50d7
 Author: Stefan Roese <sr@denx.de>
 Date:	Thu Aug 16 10:18:33 2007 +0200
@@ -1074,6 +1843,25 @@ Date:	Wed Aug 15 22:30:05 2007 -0500
 
     Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
 
+commit 5b4de9309d7a03aa1db2e5391ab696363391f460
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Wed Aug 15 21:15:05 2007 +0200
+
+    [FIX] Resolve problem with warnings
+    microblaze toolchain don't support PRAGMA PACK.
+
+commit d1ed28cf36ab6b1d4c479809de7252bf53d2f2d4
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Wed Aug 15 21:05:07 2007 +0200
+
+    [FIX] Correction command setting for Microblaze boards
+
+commit 7aa63d8cd30ab20ac2fd1ab86e60471de8b1f1e5
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Wed Aug 15 21:03:41 2007 +0200
+
+    [FIX] Correction command definition
+
 commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8
 Author: Jon Loeliger <jdl@freescale.com>
 Date:	Wed Aug 15 11:55:35 2007 -0500
@@ -2554,6 +3342,24 @@ Date:	Tue Aug 7 16:02:13 2007 +0200
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 706714d97a0d08d59eda4de2268c39f504688329
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Aug 6 23:41:53 2007 +0200
+
+    [FIX] remove cute code
+
+commit f500d9fdeb576288656dac427052ad2c5ca0ad1a
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Aug 6 23:35:26 2007 +0200
+
+    [FIX] Fix romfs code
+
+commit ab4b956d3143f8f8174089053f5dfabbb04762b0
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Aug 6 23:31:49 2007 +0200
+
+    [FIX] Coding style cleanup - Wolfgang's suggestions
+
 commit 6c33c78557ca6f8da68c01ce33e278695197d3f4
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Mon Aug 6 23:21:05 2007 +0200
@@ -2678,6 +3484,32 @@ Date:	Thu Aug 2 14:09:49 2007 -0500
     Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
     Signed-off-by: Jon Loeliger <jdl@freescale.com>
 
+commit a274ca4f6d68830e7c916f897561cff8c4101c38
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sun Aug 5 22:33:05 2007 +0200
+
+    [FIX] Coding style cleanup
+
+commit af8377d4eb3a0ac5a831830d5ce63fbf65fecb7f
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sun Aug 5 16:13:31 2007 +0200
+
+    [FIX] Xilinx Uartlite driver
+    Because PPC405 can use UARTLITE serial interface and
+    Microblaze can use Uart16550 serial interface not only Uartlite.
+
+commit 98889edd50aadf862071eb5664747ad0d568a20e
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sun Aug 5 15:54:53 2007 +0200
+
+    [FIX] Change configuration for XUPV2P Microblaze board
+
+commit 537091b4eed9302865d03fef3f7212b4fe5cf28f
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sun Aug 5 15:53:50 2007 +0200
+
+    [PATCH] Added support for Xilinx Emac community driver
+
 commit 86b116b1b1e165ca4840daefed36d2e3b8460173
 Author: Bartlomiej Sieka <tur@semihalf.com>
 Date:	Fri Aug 3 12:08:16 2007 +0200
@@ -2978,6 +3810,12 @@ Date:	Mon Jul 16 08:53:51 2007 +0200
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 0c0a9cda1bde37106520476ed486bd67eb8d30ae
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Jul 16 00:31:07 2007 +0200
+
+    [PATCH] Support for Xilinx EmacLite controller
+
 commit 3a6cab844cf74f76639d795e0be8717e02c86af7
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sat Jul 14 22:51:02 2007 +0200
@@ -2986,12 +3824,42 @@ Date:	Sat Jul 14 22:51:02 2007 +0200
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 5280f352c8da33b1d7fbf448768717d9e16ff9a1
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat Jul 14 13:11:28 2007 +0200
+
+    [FIX] support for simply measuring time
+
+commit 91bb4ca665d2e0cf7f60c4b5b370990250ec0c43
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat Jul 14 12:41:23 2007 +0200
+
+    [FS] Added support for ROMFS
+
 commit 011595307731a7a67a7445d107c279d031e8ab97
 Author: Heiko Schocher <hs@pollux.denx.de>
 Date:	Sat Jul 14 01:06:58 2007 +0200
 
     [PCS440EP]	- fix compile error, if BUILD_DIR is used
 
+commit 5a2f1098d81ad58b309e5e558d0492643166a799
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat Jul 14 00:18:48 2007 +0200
+
+    [PATCH] Support time without timer
+
+commit a476ca2ac2217ddd05a2bf0c514075814b10a3c0
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Fri Jul 13 21:43:55 2007 +0200
+
+    [PATCH] Remove problem with disabled BARREL SHIFTER
+
+commit 55e26ad62107d2f14f757de3ae0b14b9aa7aed94
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Fri Jul 13 21:41:44 2007 +0200
+
+    [FIX] correct help for rspr
+
 commit fad63407154f46246ce80d53a9c669a44362ac67
 Author: Heiko Schocher <hs@pollux.denx.de>
 Date:	Fri Jul 13 09:54:17 2007 +0200
@@ -5176,6 +6044,18 @@ Date:	Mon Jun 18 13:50:13 2007 -0500
 
     Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 
+commit 093172f08d6afb3f34d8a2f26ee0ee874261cf27
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sun Jun 17 19:04:11 2007 +0200
+
+    [fix] email reparation
+
+commit 3666afffe7baf859c6ae0ce2bebbc8ab7e512ddc
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sun Jun 17 19:03:21 2007 +0200
+
+    [FIX] fix microblaze file permitission
+
 commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
 Author: Stefan Roese <sr@denx.de>
 Date:	Fri Jun 15 11:33:41 2007 +0200

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -22,9 +22,9 @@
 #
 
 VERSION = 1
-PATCHLEVEL = 2
+PATCHLEVEL = 3
 SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc3
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -211,6 +211,7 @@ LIBS += drivers/libdrivers.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/onenand/libonenand.a
 LIBS += drivers/net/libnet.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
@@ -319,7 +320,7 @@ updater:
 env:
 		$(MAKE) -C tools/env all || exit 1
 
-depend dep:
+depend dep:	version
 		for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
 
 tags ctags:
@@ -1794,13 +1795,13 @@ MPC8349ITX_config \
 MPC8349ITX_LOWBOOT_config \
 MPC8349ITXGP_config:	unconfig
 	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/mpc8349itx
+	@mkdir -p $(obj)board/freescale/mpc8349itx
 	@echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
 	@if [ "$(findstring GP,$@)" ] ; then \
-		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+		echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
 	fi
 	@if [ "$(findstring LOWBOOT,$@)" ] ; then \
-		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+		echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
 	fi
 	@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
 
@@ -1961,7 +1962,7 @@ TQM8560_config:		unconfig
 	echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
-	echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h
+	echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
 	@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
 
 #########################################################################

board/ads5121/u-boot.lds

@@ -51,7 +51,6 @@ SECTIONS
   {
     cpu/mpc512x/start.o	(.text)
     *(.text)
-    *(.fixup)
     *(.got1)
     . = ALIGN(16);
     *(.rodata)

board/amcc/katmai/init.S

@@ -67,9 +67,9 @@ tlbtabA:
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -109,9 +109,9 @@ tlbtabB:
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

board/amcc/katmai/katmai.c

@@ -34,6 +34,8 @@
 #undef PCIE_ENDPOINT
 /* #define PCIE_ENDPOINT 1 */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int ppc440spe_init_pcie_rootport(int port);
 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
 
@@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
@@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
 	struct pci_controller *hose;
 	int i, bus;
+	char *env;
+	unsigned int delay;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
-	bus = 1;
+	bus = busno;
 	for (i = 0; i <= 2; i++) {
 		/* Check for katmai card presence */
 		if (!katmai_pcie_card_present(i))
@@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
 
 		hose = &pcie_hose[i];
 		hose->first_busno = bus;
-		hose->last_busno  = bus;
-		bus++;
+		hose->last_busno = bus;
+		hose->current_busno = bus;
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
@@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
 		 */
 #else
 		ppc440spe_setup_pcie_rootpoint(hose, i);
+
+		env = getenv ("pciscandelay");
+		if (env != NULL) {
+			delay = simple_strtoul (env, NULL, 10);
+			if (delay > 5)
+				printf ("Warning, expect noticable delay before PCIe"
+					"scan due to 'pciscandelay' value!\n");
+			mdelay (delay * 1000);
+		}
+
 		/*
 		 * Config access can only go down stream
 		 */
 		hose->last_busno = pci_hose_scan(hose);
+		bus = hose->last_busno + 1;
 #endif
 	}
 }

board/amcc/luan/luan.c

@@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  ************************************************************************/
 int board_early_init_f(void)
 {
-	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-
 	mtebc( pb0ap,  0x03800000 );	/* set chip selects */
 	mtebc( pb0cr,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
 	mtebc( pb1ap,  0x03800000 );
@@ -66,8 +64,6 @@ int board_early_init_f(void)
 	mtdcr( uic0sr, 0x00000000 );	/* clear all interrupts */
 	mtdcr( uic0sr, 0xffffffff );
 
-	x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
-
 	return  0;
 }
 
@@ -79,7 +75,18 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
 	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-	x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+	/* set modes of operation */
+	x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+		EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+	/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+	x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+	/* put Ethernet+PHY in reset */
+	x->ethuart &= ~EPLD2_RESET_ETH_N;
+	udelay(10000);
+	/* take Ethernet+PHY out of reset */
+	x->ethuart |= EPLD2_RESET_ETH_N;
 
 	return  0;
 }

board/amcc/taishan/taishan.c

@@ -32,6 +32,8 @@
 void show_reset_reg(void);
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int lcd_init(void);
 
 int board_early_init_f (void)
@@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/

board/amcc/yucca/init.S

@@ -70,9 +70,9 @@ tlbtabA:
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -112,9 +112,9 @@ tlbtabB:
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

board/amcc/yucca/yucca.c

@@ -34,6 +34,8 @@
 #include "yucca.h"
 #include "../cpu/ppc4xx/440spe_pcie.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef PCIE_ENDPOINT
 /* #define PCIE_ENDPOINT 1 */
 
@@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
@@ -846,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
 	struct pci_controller *hose;
 	int i, bus;
+	char *env;
+	unsigned int delay;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
-	bus = 1;
+	bus = busno;
 	for (i = 0; i <= 2; i++) {
 		/* Check for yucca card presence */
 		if (!yucca_pcie_card_present(i))
@@ -874,8 +876,8 @@ void pcie_setup_hoses(void)
 
 		hose = &pcie_hose[i];
 		hose->first_busno = bus;
-		hose->last_busno  = bus;
-		bus++;
+		hose->last_busno = bus;
+		hose->current_busno = bus;
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
@@ -895,10 +897,21 @@ void pcie_setup_hoses(void)
 		 */
 #else
 		ppc440spe_setup_pcie_rootpoint(hose, i);
+
+		env = getenv ("pciscandelay");
+		if (env != NULL) {
+			delay = simple_strtoul (env, NULL, 10);
+			if (delay > 5)
+				printf ("Warning, expect noticable delay before PCIe"
+					"scan due to 'pciscandelay' value!\n");
+			mdelay (delay * 1000);
+		}
+
 		/*
 		 * Config access can only go down stream
 		 */
 		hose->last_busno = pci_hose_scan(hose);
+		bus = hose->last_busno + 1;
 #endif
 	}
 }

board/at91rm9200dk/led.c

@@ -66,7 +66,7 @@ void	red_LED_off(void)
 }
 
 
-void LED_init (void)
+void coloured_LED_init (void)
 {
 	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
 	AT91PS_PMC	PMC	= AT91C_BASE_PMC;

board/atmel/atstk1000/flash.c

@@ -55,10 +55,6 @@ unsigned long flash_init(void)
 	unsigned long addr;
 	unsigned int i;
 
-	gd->bd->bi_flashstart = CFG_FLASH_BASE;
-	gd->bd->bi_flashsize = CFG_FLASH_SIZE;
-	gd->bd->bi_flashoffset = _edata - _text;
-
 	flash_info[0].size = CFG_FLASH_SIZE;
 	flash_info[0].sector_count = 135;
 

board/bf533-ezkit/bf533-ezkit.c

@@ -30,6 +30,8 @@
 #include "psd4256.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 #if (BFIN_CPU == ADSP_BF531)
@@ -46,7 +48,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/bf533-stamp/bf533-stamp.c

@@ -30,6 +30,8 @@
 #include <asm/io.h>
 #include "bf533-stamp.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define STATUS_LED_OFF 0
 #define STATUS_LED_ON  1
 
@@ -55,7 +57,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	printf("SDRAM attributes:\n");
 	printf

board/bf537-stamp/bf537-stamp.c

@@ -32,6 +32,8 @@
 #include <asm/io.h>
 #include "ether_bf537.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define POST_WORD_ADDR 0xFF903FFC
 
 /*
@@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/bf561-ezkit/bf561-ezkit.c

@@ -29,6 +29,8 @@
 #include <common.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	printf("CPU:   ADSP BF561\n");
@@ -39,7 +41,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/cm5200/cm5200.c

@@ -397,6 +397,7 @@ int misc_init_r(void)
 					"operational\n");
 
 	/* set the hostname appropriate to the module we're running on */
+	hostname[0] = 0x00;
 	compose_hostname(hw_id, hostname);
 	setenv("hostname", hostname);
 

board/cm5200/cmd_cm5200.c

@@ -27,7 +27,7 @@
 #include <i2c.h>
 #include <usb.h>
 
-#ifdef CONFIG_CMD_BSB
+#ifdef CONFIG_CMD_BSP
 
 int do_i2c(char *argv[])
 {

board/davinci/dv-evm/dv_board.c

@@ -31,6 +31,8 @@
 
 #define MACH_TYPE_DAVINCI_EVM		901
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void	i2c_init(int speed, int slaveaddr);
 extern void	timer_init(void);
 extern int	eth_hw_init(void);
@@ -115,8 +117,6 @@ void dsp_on(void)
 
 int board_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
 
@@ -202,8 +202,6 @@ int misc_init_r (void)
 
 int dram_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/davinci/schmoogie/dv_board.c

@@ -31,6 +31,8 @@
 
 #define MACH_TYPE_SCHMOOGIE		1255
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void	i2c_init(int speed, int slaveaddr);
 extern void	timer_init(void);
 extern int	eth_hw_init(void);
@@ -115,8 +117,6 @@ void dsp_on(void)
 
 int board_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
 
@@ -244,8 +244,6 @@ int misc_init_r (void)
 
 int dram_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/davinci/sonata/dv_board.c

@@ -31,6 +31,8 @@
 
 #define MACH_TYPE_SONATA		1254
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void	i2c_init(int speed, int slaveaddr);
 extern void	timer_init(void);
 extern int	eth_hw_init(void);
@@ -115,8 +117,6 @@ void dsp_on(void)
 
 int board_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_SONATA;
 
@@ -199,8 +199,6 @@ int misc_init_r (void)
 
 int dram_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/fads/fads.h

@@ -229,6 +229,7 @@
 #define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
 #define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define	CFG_DIRECT_FLASH_TFTP
 

board/freescale/common/pixis.c

@@ -25,10 +25,9 @@
 #include <common.h>
 #include <command.h>
 #include <watchdog.h>
-#include <asm/cache.h>
 
 #ifdef CONFIG_FSL_PIXIS
-
+#include <asm/cache.h>
 #include "pixis.h"
 
 

board/freescale/m5235evb/mii.c

@@ -204,7 +204,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {

board/freescale/m5329evb/mii.c

@@ -203,7 +203,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {

board/freescale/m54455evb/mii.c

@@ -221,7 +221,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {

board/freescale/mpc8313erdb/sdram.c

@@ -33,10 +33,11 @@
 
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CFG_8313ERDB_BROKEN_PMC
 static void resume_from_sleep(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	u32 magic = *(u32 *)0;
 
 	typedef void (*func_t)(void);

board/lpc2292sodimm/lpc2292sodimm.c

@@ -28,8 +28,7 @@
 #include <common.h>
 #include <clps7111.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -37,8 +36,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Activate LED flasher */
 	IO_LEDFLSH = 0x40;
 
@@ -53,8 +50,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/m5271evb/mii.c

@@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {

board/m5272c3/mii.c

@@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {

board/m5282evb/mii.c

@@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {

board/mpc7448hpc2/mpc7448hpc2.c

@@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd);
 
 #undef	DEBUG
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void flush_data_cache (void);
 extern void invalidate_l1_instruction_cache (void);
 extern void tsi108_init_f (void);
@@ -46,8 +48,6 @@ int display_mem_map (void);
 
 void after_reloc (ulong dest_addr)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*
 	 * Jump to the main U-Boot board init code
 	 */

board/mpc7448hpc2/tsi108_init.c

@@ -33,6 +33,8 @@
 #include <asm/processor.h>
 #include <tsi108.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void mpicInit (int verbose);
 
 /*
@@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void)
 
 int board_early_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	ulong i;
 
 	gd->mem_clk = 0;
@@ -583,7 +584,6 @@ unsigned long get_l2cr (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef CFG_CLK_SPREAD	/* Initialize Spread-Spectrum Clock generation */
 	ulong i;
 

board/mpl/vcma9/cmd_vcma9.c

@@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data)
 
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void print_vcma9_info(void);
 extern int vcma9_cantest(int);
 extern int vcma9_nandtest(void);
@@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	if (strcmp(argv[1], "info") == 0)
 	{
 		print_vcma9_info();

board/mpl/vcma9/vcma9.c

@@ -288,7 +288,7 @@ int dram_init(void)
 
 int checkboard(void)
 {
-	unsigned char s[50];
+	char s[50];
 	int i;
 	backup_t *b = (backup_t *) s;
 
@@ -337,7 +337,7 @@ int overwrite_console(void)
 ************************************************************************/
 void print_vcma9_info(void)
 {
-	unsigned char s[50];
+	char s[50];
 	int i;
 
 	if ((i = getenv_r("serial#", s, 32)) < 0) {

board/sbc2410x/sbc2410x.c

@@ -35,7 +35,7 @@
 #include <linux/mtd/nand.h>
 #endif
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define FCLK_SPEED 1
 
@@ -74,7 +74,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
@@ -128,8 +127,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/siemens/SMN42/smn42.c

@@ -31,8 +31,7 @@
 #include <common.h>
 #include <clps7111.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscellaneous platform dependent initialisations
@@ -40,8 +39,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number MACH_TYPE_ARMADILLO - not official*/
 	gd->bd->bi_arch_number = 83;
 
@@ -53,8 +50,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/stxssa/stxssa.c

@@ -378,9 +378,14 @@ static struct pci_config_table pci_stxgp3_config_table[] = {
 #endif
 
 
-static struct pci_controller hose = {
+static struct pci_controller hose[] = {
 #ifndef CONFIG_PCI_PNP
-	config_table: pci_stxgp3_config_table,
+	{ config_table: pci_stxgp3_config_table,},
+#else
+	{},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
 #endif
 };
 
@@ -393,6 +398,6 @@ pci_init_board(void)
 #ifdef CONFIG_PCI
 	extern void pci_mpc85xx_init(struct pci_controller *hose);
 
-	pci_mpc85xx_init(&hose);
+	pci_mpc85xx_init(hose);
 #endif /* CONFIG_PCI */
 }

board/stxssa/u-boot.lds

@@ -145,6 +145,7 @@ SECTIONS
   . = ALIGN(256);
   __init_end = .;
 
+  . = .;
   __bss_start = .;
   .bss       :
   {

board/tqm5200/tqm5200.c

@@ -43,6 +43,8 @@
 #include "mt48lc16m16a2-75.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_PS2MULT
 void ps2mult_early_init(void);
 #endif
@@ -477,8 +479,6 @@ int silent_boot (void)
 
 int board_early_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	if (silent_boot())
 		gd->flags |= GD_FLG_SILENT;
 

common/Makefile

@@ -37,13 +37,14 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
 	  cmd_load.o cmd_log.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
+	  cmd_onenand.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
 	  cmd_universe.o cmd_usb.o cmd_vfd.o \
 	  command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
-	  env_nvram.o env_nowhere.o \
+	  env_onenand.o env_nvram.o env_nowhere.o \
 	  exports.o \
 	  fdt_support.o flash.o fpga.o ft_build.o \
 	  hush.o kgdb.o lcd.o lists.o lynxkdi.o \

common/cmd_bootm.c

@@ -834,9 +834,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 			of_flat_tree += 4 - tail;
 		}
 
+#ifndef CFG_NO_FLASH
 		/* move the blob if it is in flash (set of_data to !null) */
 		if (addr2info ((ulong)of_flat_tree) != NULL)
 			of_data = (ulong)of_flat_tree;
+#endif
 
 
 #if defined(CONFIG_OF_FLAT_TREE)

common/cmd_fpga.c

@@ -60,6 +60,7 @@ static int fpga_get_op (char *opstr);
 /* Convert bitstream data and load into the fpga */
 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 {
+#if (CONFIG_FPGA & CFG_FPGA_XILINX)
 	unsigned int length;
 	unsigned char* swapdata;
 	unsigned int swapsize;
@@ -72,7 +73,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 
 	dataptr = (unsigned char *)fpgadata;
 
-#if CFG_FPGA_XILINX
 	/* skip the first bytes of the bitsteam, their meaning is unknown */
 	length = (*dataptr << 8) + *(dataptr+1);
 	dataptr+=2;

common/cmd_mfsl.c

@@ -355,19 +355,18 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	unsigned int reg = 0;
 	unsigned int val = 0;
 
-	reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
-	val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
-	if (argc < 1) {
+	if (argc < 2) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
+	reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
 	switch (reg) {
 	case 0x1:
 		if (argc > 2) {
 			MTS (val, rmsr);
 			NOP;
 			MFS (val, rmsr);
-
 		} else {
 			MFS (val, rmsr);
 		}
@@ -382,6 +381,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		puts ("ESR");
 		break;
 	default:
+		puts ("Unsupported register\n");
 		return 1;
 	}
 	printf (": 0x%08lx\n", val);
@@ -408,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 		" 3 - blocking control write\n");
 
 U_BOOT_CMD (rspr, 3, 1, do_rspr,
-		"rmsr    - read/write special purpose register\n",
+		"rspr    - read/write special purpose register\n",
 		"- reg_num [write value] read/write special purpose register\n"
-		" 0 - MSR - Machine status register\n"
-		" 1 - EAR - Exception address register\n"
-		" 2 - ESR - Exception status register\n");
+		" 1 - MSR - Machine status register\n"
+		" 3 - EAR - Exception address register\n"
+		" 5 - ESR - Exception status register\n");
 
 #endif

common/cmd_nand.c

@@ -161,7 +161,11 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	ulong addr, off, size;
 	char *cmd, *s;
 	nand_info_t *nand;
+#ifdef CFG_NAND_QUIET
+	int quiet = CFG_NAND_QUIET;
+#else
 	int quiet = 0;
+#endif
 	const char *quiet_str = getenv("quiet");
 
 	/* at least two arguments please */
@@ -452,7 +456,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand,
 	"info                  - show available NAND devices\n"
 	"nand device [dev]     - show or set current device\n"
 	"nand read[.jffs2]     - addr off|partition size\n"
-	"nand write[.jffs2]    - addr off|partiton size - read/write `size' bytes starting\n"
+	"nand write[.jffs2]    - addr off|partition size - read/write `size' bytes starting\n"
 	"    at offset `off' to/from memory address `addr'\n"
 	"nand erase [clean] [off size] - erase `size' bytes from\n"
 	"    offset `off' (entire device if not specified)\n"

common/cmd_nvedit.c

@@ -57,8 +57,9 @@ DECLARE_GLOBAL_DATA_PTR;
     !defined(CFG_ENV_IS_IN_FLASH)	&& \
     !defined(CFG_ENV_IS_IN_DATAFLASH)	&& \
     !defined(CFG_ENV_IS_IN_NAND)	&& \
+    !defined(CFG_ENV_IS_IN_ONENAND)	&& \
     !defined(CFG_ENV_IS_NOWHERE)
-# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
+# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
 #endif
 
 #define XMK_STR(x)	#x
@@ -553,7 +554,8 @@ int getenv_r (char *name, char *buf, unsigned len)
 
 #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
-    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
 int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern char * env_name_spec;
@@ -608,7 +610,8 @@ U_BOOT_CMD(
 
 #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
-    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
 U_BOOT_CMD(
 	saveenv, 1, 0,	do_saveenv,
 	"saveenv - save environment variables to persistent storage\n",

common/cmd_onenand.c

@@ -0,0 +1,155 @@
+/*
+ *  U-Boot command for OneNAND support
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int ret = 0;
+
+	switch (argc) {
+	case 0:
+	case 1:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+
+	case 2:
+		if (strncmp(argv[1], "open", 4) == 0) {
+			onenand_init();
+			return 0;
+		}
+		onenand_print_device_info(onenand_chip.device_id, 1);
+		return 0;
+
+	default:
+		/* At least 4 args */
+		if (strncmp(argv[1], "erase", 5) == 0) {
+			struct erase_info instr;
+			ulong start, end;
+			ulong block;
+
+			start = simple_strtoul(argv[2], NULL, 10);
+			end = simple_strtoul(argv[3], NULL, 10);
+			start -= (unsigned long)onenand_chip.base;
+			end -= (unsigned long)onenand_chip.base;
+
+			if (!end || end < 0)
+				end = start;
+
+			printf("Erase block from %d to %d\n", start, end);
+
+			for (block = start; block <= end; block++) {
+				instr.addr = block << onenand_chip.erase_shift;
+				instr.len = 1 << onenand_chip.erase_shift;
+				ret = onenand_erase(&onenand_mtd, &instr);
+				if (ret) {
+					printf("erase failed %d\n", block);
+					break;
+				}
+			}
+
+			return 0;
+		}
+
+		if (strncmp(argv[1], "read", 4) == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong ofs = simple_strtoul(argv[3], NULL, 16);
+			size_t len = simple_strtoul(argv[4], NULL, 16);
+			size_t retlen = 0;
+			int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
+
+			ofs -= (unsigned long)onenand_chip.base;
+
+			if (oob)
+				onenand_read_oob(&onenand_mtd, ofs, len,
+						 &retlen, (u_char *) addr);
+			else
+				onenand_read(&onenand_mtd, ofs, len, &retlen,
+					     (u_char *) addr);
+			printf("Done\n");
+
+			return 0;
+		}
+
+		if (strncmp(argv[1], "write", 5) == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong ofs = simple_strtoul(argv[3], NULL, 16);
+			size_t len = simple_strtoul(argv[4], NULL, 16);
+			size_t retlen = 0;
+
+			ofs -= (unsigned long)onenand_chip.base;
+
+			onenand_write(&onenand_mtd, ofs, len, &retlen,
+				      (u_char *) addr);
+			printf("Done\n");
+
+			return 0;
+		}
+
+		if (strncmp(argv[1], "block", 5) == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong block = simple_strtoul(argv[3], NULL, 10);
+			ulong page = simple_strtoul(argv[4], NULL, 10);
+			size_t len = simple_strtol(argv[5], NULL, 10);
+			size_t retlen = 0;
+			ulong ofs;
+			int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1;
+
+			ofs = block << onenand_chip.erase_shift;
+			if (page)
+				ofs += page << onenand_chip.page_shift;
+
+			if (!len) {
+				if (oob)
+					len = 64;
+				else
+					len = 512;
+			}
+
+			if (oob)
+				onenand_read_oob(&onenand_mtd, ofs, len,
+						 &retlen, (u_char *) addr);
+			else
+				onenand_read(&onenand_mtd, ofs, len, &retlen,
+					     (u_char *) addr);
+			return 0;
+		}
+
+		break;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	onenand,	6,	1,	do_onenand,
+	"onenand - OneNAND sub-system\n",
+	"info   - show available OneNAND devices\n"
+	"onenand read[.oob] addr ofs len - read data at ofs with len to addr\n"
+	"onenand write addr ofs len - write data at ofs with len from addr\n"
+	"onenand erase saddr eaddr - erase block start addr to end addr\n"
+	"onenand block[.oob] addr block [page] [len] - "
+		"read data with (block [, page]) to addr"
+);
+
+#endif /* CONFIG_CMD_ONENAND */

common/env_onenand.c

@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_IN_ONENAND)	/* Environment is in OneNAND */
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+/* References to names in env_common.c */
+extern uchar default_environment[];
+
+#define ONENAND_ENV_SIZE(mtd)	(mtd.oobblock - ENV_HEADER_SIZE)
+
+char *env_name_spec = "OneNAND";
+
+#ifdef ENV_IS_EMBEDDED
+extern uchar environment[];
+env_t *env_ptr = (env_t *) (&environment[0]);
+#else /* ! ENV_IS_EMBEDDED */
+static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
+env_t *env_ptr = (env_t *) onenand_env;
+#endif /* ENV_IS_EMBEDDED */
+
+uchar env_get_char_spec(int index)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	return (*((uchar *) (gd->env_addr + index)));
+}
+
+void env_relocate_spec(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long env_addr;
+	int use_default = 0;
+	int retlen;
+
+	env_addr = CFG_ENV_ADDR;
+	env_addr -= (unsigned long)onenand_chip.base;
+
+	/* Check OneNAND exist */
+	if (onenand_mtd.oobblock)
+		/* Ignore read fail */
+		onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock,
+			     &retlen, (u_char *) env_ptr);
+	else
+		onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE;
+
+	if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
+	    env_ptr->crc)
+		use_default = 1;
+
+	if (use_default) {
+		memcpy(env_ptr->data, default_environment,
+		       ONENAND_ENV_SIZE(onenand_mtd));
+		env_ptr->crc =
+		    crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
+	}
+
+	gd->env_addr = (ulong) & env_ptr->data;
+	gd->env_valid = 1;
+}
+
+int saveenv(void)
+{
+	unsigned long env_addr = CFG_ENV_ADDR;
+	struct erase_info instr;
+	int retlen;
+
+	instr.len = CFG_ENV_SIZE;
+	instr.addr = env_addr;
+	instr.addr -= (unsigned long)onenand_chip.base;
+	if (onenand_erase(&onenand_mtd, &instr)) {
+		printf("OneNAND: erase failed at 0x%08x\n", env_addr);
+		return 1;
+	}
+
+	/* update crc */
+	env_ptr->crc =
+	    crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE);
+
+	env_addr -= (unsigned long)onenand_chip.base;
+	if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
+	     (u_char *) env_ptr)) {
+		printf("OneNAND: write failed at 0x%08x\n", instr.addr);
+		return 2;
+	}
+
+	return 0;
+}
+
+int env_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* use default */
+	gd->env_addr = (ulong) & default_environment[0];
+	gd->env_valid = 1;
+
+	return 0;
+}
+
+#endif /* CFG_ENV_IS_IN_ONENAND */

common/environment.c

@@ -51,18 +51,7 @@
  * a seperate section.  Note that ENV_CRC is only defined when building
  * U-Boot itself.
  */
-#if (defined(CONFIG_CMI)	|| \
-     defined(CONFIG_FADS)	|| \
-     defined(CONFIG_HYMOD)	|| \
-     defined(CONFIG_ICU862)	|| \
-     defined(CONFIG_R360MPI)	|| \
-     defined(CONFIG_TQM8xxL)	|| \
-     defined(CONFIG_RRVISION)	|| \
-     defined(CONFIG_TRAB)   	|| \
-     defined(CONFIG_PPCHAMELEONEVB) || \
-     defined(CONFIG_M5271EVB)	|| \
-     defined(CONFIG_IDMR)	|| \
-     defined(CONFIG_NAND_U_BOOT))	&& \
+#if (defined(CFG_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
      defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
 /* XXX - This only works with GNU C */
 #  define __PPCENV__ __attribute__ ((section(".ppcenv")))

cpu/arm1136/config.mk

@@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv5
 #
 # =========================================================================
 PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm720t/serial.c

@@ -125,12 +125,12 @@ serial_puts (const char *s)
 
 #elif defined(CONFIG_LPC2292)
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #include <asm/arch/hardware.h>
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned short divisor = 0;
 
 	switch (gd->baudrate) {

cpu/arm920t/start.S

@@ -27,9 +27,7 @@
 
 #include <config.h>
 #include <version.h>
-#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-#include	<led.h>
-#endif
+#include <status_led.h>
 
 /*
  *************************************************************************
@@ -41,7 +39,7 @@
 
 
 .globl _start
-_start:	b       reset
+_start:	b       start_code
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -64,7 +62,7 @@ _fiq:			.word fiq
 /*
  *************************************************************************
  *
- * Startup Code (reset vector)
+ * Startup Code (called from the ARM reset exception vector)
  *
  * do important init only if we don't start from memory!
  * relocate armboot to ram
@@ -106,10 +104,10 @@ FIQ_STACK_START:
 
 
 /*
- * the actual reset code
+ * the actual start code
  */
 
-reset:
+start_code:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -118,58 +116,12 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-#if	CONFIG_AT91RM9200
-#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-	bl LED_init
+	bl coloured_LED_init
 	bl red_LED_on
-#endif
 
-#ifdef CONFIG_BOOTBINFUNC
-/* code based on entry.S from ATMEL */
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-	/* Get the CKGR Base Address */
-	ldr     r1, =AT91C_BASE_CKGR
-
-/* Main oscillator Enable register	APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
-/*	ldr 	r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
-	ldr 	r0, =0x0000FF01
-	str     r0, [r1, #CKGR_MOR]
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr 	r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-	/* scratch stack */
-	ldr 	r1, =0x00204000
-	/* Insure word alignment */
-	bic     r1, r1, #3
-	/* Init stack SYS	 */
-	mov     sp, r1
+#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
 	/*
-	 * This does a lot more than just set up the memory, which
-	 * is why it's called lowlevelinit
-	 */
-	bl	lowlevelinit /* in memsetup.S */
-	bl	icache_enable;
-	/* ------------------------------------
-	 * Read/modify/write CP15 control register
-	 * -------------------------------------
-	 * read cp15 control register (cp15 r1) in r0
-	 * ------------------------------------
-	 */
-	mrc     p15, 0, r0, c1, c0, 0
-	/* Reset bit :Little Endian end fast bus mode */
-	ldr     r3, =0xC0000080
-	/* Set bit :Asynchronous clock mode, Not Fast Bus */
-	ldr     r4, =0xC0000000
-	bic     r0, r0, r3
-	orr     r0, r0, r4
-	/* write r0 in cp15 control register (cp15 r1) */
-	mcr     p15, 0, r0, c1, c0, 0
-#endif /* CONFIG_BOOTBINFUNC */
-	/*
-	 * relocate exeception table
+	 * relocate exception table
 	 */
 	ldr	r0, =_start
 	ldr	r1, =0x0
@@ -181,19 +133,20 @@ copyex:
 	bne	copyex
 #endif
 
-/* turn off the watchdog */
-#if defined(CONFIG_S3C2400)
-# define pWTCON		0x15300000
-# define INTMSK		0x14400008	/* Interupt-Controller base addresses */
-# define CLKDIVN	0x14800014	/* clock divisor register */
-#elif defined(CONFIG_S3C2410)
-# define pWTCON		0x53000000
-# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
-# define INTSUBMSK	0x4A00001C
-# define CLKDIVN	0x4C000014	/* clock divisor register */
-#endif
-
 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+	/* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+#  define pWTCON		0x15300000
+#  define INTMSK		0x14400008	/* Interupt-Controller base addresses */
+#  define CLKDIVN	0x14800014	/* clock divisor register */
+#else
+#  define pWTCON		0x53000000
+#  define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+#  define INTSUBMSK	0x4A00001C
+#  define CLKDIVN	0x4C000014	/* clock divisor register */
+# endif
+
 	ldr     r0, =pWTCON
 	mov     r1, #0x0
 	str     r1, [r0]
@@ -226,25 +179,7 @@ copyex:
 #endif
 
 #ifdef	CONFIG_AT91RM9200
-#ifdef CONFIG_BOOTBINFUNC
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
 
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-#endif /* CONFIG_BOOTBINFUNC */
-#else
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
@@ -284,27 +219,6 @@ clbss_l:str	r2, [r0]		/* clear loop...                    */
 	cmp	r0, r1
 	ble	clbss_l
 
-#if 0
-	/* try doing this stuff after the relocation */
-	ldr     r0, =pWTCON
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =INTMR
-	str	r1, [r0]
-
-	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
-	ldr	r0, =CLKDIVN
-	mov	r1, #3
-	str	r1, [r0]
-	/* END stuff after relocation */
-#endif
-
 	ldr	pc, _start_armboot
 
 _start_armboot:	.word start_armboot

cpu/bf533/serial.c

@@ -76,7 +76,6 @@ void calc_baud(void)
 void serial_setbrg(void)
 {
 	int i;
-	DECLARE_GLOBAL_DATA_PTR;
 
 	calc_baud();
 

cpu/bf537/i2c.c

@@ -22,6 +22,8 @@
 #include <i2c.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define bfin_read16(addr) ({ unsigned __v; \
 			__asm__ __volatile__ (\
 			"%0 = w[%1] (z);\n\t"\
@@ -68,7 +70,6 @@
 
 #ifdef DEBUG_I2C
 #define PRINTD(fmt,args...)	do {	\
-	DECLARE_GLOBAL_DATA_PTR;	\
 	if (gd->have_console)		\
 		printf(fmt ,##args);	\
 	} while (0)

cpu/bf537/serial.c

@@ -52,6 +52,8 @@
 #include <asm/io.h>
 #include "serial.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned long pll_div_fact;
 
 void calc_baud(void)
@@ -74,7 +76,6 @@ void calc_baud(void)
 void serial_setbrg(void)
 {
 	int i;
-	DECLARE_GLOBAL_DATA_PTR;
 
 	calc_baud();
 

cpu/bf561/serial.c

@@ -52,6 +52,8 @@
 #include "serial.h"
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned long pll_div_fact;
 
 void calc_baud(void)
@@ -74,7 +76,6 @@ void calc_baud(void)
 void serial_setbrg(void)
 {
 	int i;
-	DECLARE_GLOBAL_DATA_PTR;
 
 	calc_baud();
 

cpu/mcf532x/cpu.c

@@ -31,6 +31,8 @@
 
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 {
 	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
@@ -48,8 +50,6 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 
 int checkcpu(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
 	u16 msk;
 	u16 id = 0;

cpu/mcf532x/speed.c

@@ -30,6 +30,8 @@
 
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* PLL min/max specifications */
 #define MAX_FVCO	500000	/* KHz */
 #define MAX_FSYS	80000	/* KHz */
@@ -208,8 +210,6 @@ int clock_pll(int fsys, int flags)
  */
 int get_clocks(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
 	gd->cpu_clk = (gd->bus_clk * 3);
 	return (0);

cpu/microblaze/cache.c

@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2007 Michal Simek
  *
- * Michal SIMEK <moonstr@monstr.eu>
+ * Michal SIMEK <monstr@monstr.eu>
  *
  * See file CREDITS for list of people who contributed to this
  * project.

cpu/microblaze/start.S

@@ -33,15 +33,13 @@ _start:
 	addi	r1, r0, CFG_INIT_SP_OFFSET
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 	/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
-	addi	r6, r0, 0xb000	/* hex b000 opcode imm */
-	bslli	r6, r6, 16	/* shift */
+	addi	r6, r0, 0xb0000000	/* hex b000 opcode imm */
 	swi	r6, r0, 0x0	/* reset address */
 	swi	r6, r0, 0x8	/* user vector exception */
 	swi	r6, r0, 0x10	/* interrupt */
 	swi	r6, r0, 0x20	/* hardware exception */
 
-	addi	r6, r0, 0xb808	/* hew b808 opcode brai*/
-	bslli	r6, r6, 16
+	addi	r6, r0, 0xb8080000	/* hew b808 opcode brai*/
 	swi	r6, r0, 0x4	/* reset address */
 	swi	r6, r0, 0xC	/* user vector exception */
 	swi	r6, r0, 0x14	/* interrupt */

cpu/microblaze/timer.c

@@ -33,10 +33,17 @@ void reset_timer (void)
 	timestamp = 0;
 }
 
+#ifdef CFG_TIMER_0
 ulong get_timer (ulong base)
 {
 	return (timestamp - base);
 }
+#else
+ulong get_timer (ulong base)
+{
+	return (timestamp++ - base);
+}
+#endif
 
 void set_timer (ulong t)
 {

cpu/mpc512x/config.mk

@@ -19,7 +19,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
 			-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e

cpu/mpc512x/fec.c

@@ -32,6 +32,9 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re
 int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
 
+static uchar rx_buff[FEC_BUFFER_SIZE];
+static int rx_buff_idx = 0;
+
 /********************************************************************/
 #if (DEBUG & 0x2)
 static void mpc512x_fec_phydump (char *devname)
@@ -234,8 +237,8 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 	/* Set Opcode/Pause Duration Register */
 	fec->eth->op_pause = 0x00010020;
 
-	/* Frame length=1518; MII mode */
-	fec->eth->r_cntrl = 0x05ee000c;
+	/* Frame length=1522; MII mode */
+	fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
 
 	/* Half-duplex, heartbeat disabled */
 	fec->eth->x_cntrl = 0x00000000;
@@ -245,7 +248,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 
 	/* Setup recv fifo start and buff size */
 	fec->eth->r_fstart = 0x500;
-	fec->eth->r_buff_size = 0x5e0;
+	fec->eth->r_buff_size = FEC_BUFFER_SIZE;
 
 	/* Setup BD base addresses */
 	fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
@@ -520,8 +523,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
 	volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
 	unsigned long ievent;
-	int frame_length, len = 0;
-	uchar buff[FEC_MAX_PKT_SIZE];
+	int frame_length = 0;
 
 #if (DEBUG & 0x1)
 	printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
@@ -555,31 +557,37 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	}
 
 	if (!(pRbd->status & FEC_RBD_EMPTY)) {
-		if ((pRbd->status & FEC_RBD_LAST) &&
-			!(pRbd->status & FEC_RBD_ERR) &&
+		if (!(pRbd->status & FEC_RBD_ERR) &&
 			((pRbd->dataLength - 4) > 14)) {
 
 			/*
 			 * Get buffer size
 			 */
-			frame_length = pRbd->dataLength - 4;
-
+			if (pRbd->status & FEC_RBD_LAST)
+				frame_length = pRbd->dataLength - 4;
+			else
+				frame_length = pRbd->dataLength;
 #if (DEBUG & 0x20)
 			{
 				int i;
-				printf ("recv data hdr:");
+				printf ("recv data length 0x%08x data hdr: ",
+					pRbd->dataLength);
 				for (i = 0; i < 14; i++)
 					printf ("%x ", *((uint8*)pRbd->dataPointer + i));
 				printf("\n");
 			}
 #endif
-
 			/*
 			 *  Fill the buffer and pass it to upper layers
 			 */
-			memcpy (buff, (void*)pRbd->dataPointer, frame_length);
-			NetReceive ((uchar*)buff, frame_length);
-			len = frame_length;
+			memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
+				frame_length - rx_buff_idx);
+			rx_buff_idx = frame_length;
+
+			if (pRbd->status & FEC_RBD_LAST) {
+				NetReceive ((uchar*)rx_buff, frame_length);
+				rx_buff_idx = 0;
+			}
 		}
 
 		/*
@@ -590,7 +598,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 
 	/* Try to fill Buffer Descriptors */
 	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */
-	return len;
+	return frame_length;
 }
 
 /********************************************************************/

cpu/mpc512x/fec.h

@@ -164,10 +164,13 @@ typedef enum {
 #define FEC_RBD_NUM		32	/* The user can adjust this value */
 
 /* packet size limit */
-#define FEC_MAX_PKT_SIZE	1536
+#define FEC_MAX_FRAME_LEN	1522	/* recommended default value */
+
+/* Buffer size must be evenly divisible by 16 */
+#define FEC_BUFFER_SIZE		((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
 
 typedef struct {
-	uint8 frame[FEC_MAX_PKT_SIZE];
+	uint8 frame[FEC_BUFFER_SIZE];
 } mpc512x_frame;
 
 typedef struct {

cpu/mpc86xx/cpu_init.c

@@ -29,6 +29,8 @@
 #include <common.h>
 #include <mpc86xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breathe some life into the CPU...
  *
@@ -38,7 +40,6 @@
 
 void cpu_init_f(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 

cpu/mpc86xx/speed.c

@@ -29,6 +29,7 @@
 #include <mpc86xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(sys_info_t *sysInfo)
 {
@@ -96,7 +97,6 @@ void get_sys_info(sys_info_t *sysInfo)
 
 int get_clocks(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	sys_info_t sys_info;
 
 	get_sys_info(&sys_info);

cpu/mpc86xx/traps.c

@@ -34,6 +34,8 @@
 #include <command.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
 #endif
@@ -50,8 +52,6 @@ extern unsigned long search_exception_table(unsigned long);
 void
 print_backtrace(unsigned long *sp)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int cnt = 0;
 	unsigned long i;
 

cpu/ppc4xx/405gp_pci.c

@@ -443,7 +443,7 @@ void pci_init_board(void)
 static struct pci_controller ppc440_hose = {0};
 
 
-void pci_440_init (struct pci_controller *hose)
+int pci_440_init (struct pci_controller *hose)
 {
 	int reg_num = 0;
 
@@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose)
 	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 		printf("PCI: SDR0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
-		return;
+		return -1;
 	}
 #elif defined(CONFIG_440GP)
 	unsigned long strap;
@@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose)
 	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 		printf("PCI: CPC0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
-		return;
+		return -1;
 	}
 #endif
 #endif /* CONFIG_DISABLE_PISE_TEST */
@@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose)
 	 * PCI controller init
 	 *--------------------------------------------------------------------------*/
 	hose->first_busno = 0;
-	hose->last_busno = 0xff;
+	hose->last_busno = 0;
 
 	/* PCI I/O space */
 	pci_set_region(hose->regions + reg_num++,
@@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose)
 	if (pci_pre_init (hose) == 0) {
 		printf("PCI: Board-specific initialization failed.\n");
 		printf("PCI: Configuration aborted.\n");
-		return;
+		return -1;
 	}
 
 	pci_register_hose( hose );
@@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose)
 #endif
 		hose->last_busno = pci_hose_scan(hose);
 	}
+	return hose->last_busno;
 }
 
 void pci_init_board(void)
 {
-	pci_440_init (&ppc440_hose);
+	int busno;
+
+	busno = pci_440_init (&ppc440_hose);
 #if defined(CONFIG_440SPE)
-	pcie_setup_hoses();
+	pcie_setup_hoses(busno + 1);
 #endif
 }
 

cpu/ppc4xx/440spe_pcie.c

@@ -40,73 +40,126 @@ enum {
 	LNKW_X8			= 0x8
 };
 
-static inline int pcie_in_8(const volatile unsigned char __iomem *addr)
+static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
 {
-	int ret;
+	u8 *base = (u8*)hose->cfg_data;
 
-	PCIE_IN(lbzx, ret, addr);
+	/* use local configuration space for the first bus */
+	if (PCI_BUS(devfn) == 0) {
+		if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
+			base = (u8*)CFG_PCIE0_XCFGBASE;
+		if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
+			base = (u8*)CFG_PCIE1_XCFGBASE;
+		if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
+			base = (u8*)CFG_PCIE2_XCFGBASE;
+	}
 
-	return ret;
+	return base;
 }
 
-static inline int pcie_in_le16(const volatile unsigned short __iomem *addr)
+static void pcie_dmer_disable(void)
 {
-	int ret;
-
-	PCIE_IN(lhbrx, ret, addr)
-
-	return ret;
+	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
+		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
+	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
+		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
+	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
+		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
 }
 
-static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr)
+static void pcie_dmer_enable(void)
 {
-	unsigned ret;
-
-	PCIE_IN(lwbrx, ret, addr);
-
-	return ret;
+	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
+		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
+	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
+		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
+	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
+		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
 }
 
-
 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
 	int offset, int len, u32 *val) {
 
+	u8 *address;
 	*val = 0;
+
 	/*
-	 * 440SPE implements only one function per port
+	 * Bus numbers are relative to hose->first_busno
 	 */
-	if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+	devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
+	/*
+	 * NOTICE: configuration space ranges are currenlty mapped only for
+	 * the first 16 buses, so such limit must be imposed. In case more
+	 * buses are required the TLB settings in board/amcc/<board>/init.S
+	 * need to be altered accordingly (one bus takes 1 MB of memory space).
+	 */
+	if (PCI_BUS(devfn) >= 16)
 		return 0;
 
-	devfn = PCI_BDF(0,0,0);
+	/*
+	 * Only single device/single function is supported for the primary and
+	 * secondary buses of the 440SPe host bridge.
+	 */
+	if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+		((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+		return 0;
+
+	address = pcie_get_base(hose, devfn);
 	offset += devfn << 4;
 
+	/*
+	 * Reading from configuration space of non-existing device can
+	 * generate transaction errors. For the read duration we suppress
+	 * assertion of machine check exceptions to avoid those.
+	 */
+	pcie_dmer_disable ();
+
 	switch (len) {
 	case 1:
-		*val = pcie_in_8(hose->cfg_data + offset);
+		*val = in_8(hose->cfg_data + offset);
 		break;
 	case 2:
-		*val = pcie_in_le16((u16 *)(hose->cfg_data + offset));
+		*val = in_le16((u16 *)(hose->cfg_data + offset));
 		break;
 	default:
-		*val = pcie_in_le32((u32*)(hose->cfg_data + offset));
+		*val = in_le32((u32*)(hose->cfg_data + offset));
 		break;
 	}
+
+	pcie_dmer_enable ();
+
 	return 0;
 }
 
 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
 	int offset, int len, u32 val) {
 
+	u8 *address;
+
 	/*
-	 * 440SPE implements only one function per port
+	 * Bus numbers are relative to hose->first_busno
 	 */
-	if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+	devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
+	/*
+	 * Same constraints as in pcie_read_config().
+	 */
+	if (PCI_BUS(devfn) >= 16)
 		return 0;
 
-	devfn = PCI_BDF(0,0,0);
+	if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+		((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+		return 0;
+
+	address = pcie_get_base(hose, devfn);
 	offset += devfn << 4;
 
+	/*
+	 * Suppress MCK exceptions, similar to pcie_read_config()
+	 */
+	pcie_dmer_disable ();
+
 	switch (len) {
 	case 1:
 		out_8(hose->cfg_data + offset, val);
@@ -118,6 +171,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
 		out_le32((u32 *)(hose->cfg_data + offset), val);
 		break;
 	}
+
+	pcie_dmer_enable ();
+
 	return 0;
 }
 
@@ -126,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u
 	u32 v;
 	int rv;
 
-	rv =  pcie_read_config(hose, dev, offset, 1, &v);
+	rv = pcie_read_config(hose, dev, offset, 1, &v);
 	*val = (u8)v;
 	return rv;
 }
@@ -783,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 	volatile void *rmbase = NULL;
 
 	pci_set_ops(hose,
-		    pcie_read_config_byte,
-		    pcie_read_config_word,
-		    pcie_read_config_dword,
-		    pcie_write_config_byte,
-		    pcie_write_config_word,
-		    pcie_write_config_dword);
+		pcie_read_config_byte,
+		pcie_read_config_word,
+		pcie_read_config_dword,
+		pcie_write_config_byte,
+		pcie_write_config_word,
+		pcie_write_config_dword);
 
 	switch (port) {
 	case 0:
@@ -811,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 	/*
 	 * Set bus numbers on our root port
 	 */
-	if (ppc440spe_revB()) {
-		out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
-		out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
-		out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
-	} else {
-		out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
-		out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
-	}
+	out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+	out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+	out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
 
 	/*
 	 * Set up outbound translation to hose->mem_space from PLB
@@ -875,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 		 in_le16((u16 *)(mbase + PCI_COMMAND)) |
 		 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	printf("PCIE:%d successfully set as rootpoint\n",port);
+
+	/* Set Device and Vendor Id */
+	switch (port) {
+	case 0:
+		out_le16(mbase + 0x200, 0xaaa0);
+		out_le16(mbase + 0x202, 0xbed0);
+		break;
+	case 1:
+		out_le16(mbase + 0x200, 0xaaa1);
+		out_le16(mbase + 0x202, 0xbed1);
+		break;
+	case 2:
+		out_le16(mbase + 0x200, 0xaaa2);
+		out_le16(mbase + 0x202, 0xbed2);
+		break;
+	default:
+		out_le16(mbase + 0x200, 0xaaa3);
+		out_le16(mbase + 0x202, 0xbed3);
+	}
+
+	/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
+	out_le32(mbase + 0x208, 0x06040001);
+
 }
 
 int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
@@ -952,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	/* Enable I/O, Mem, and Busmaster cycles */
 	out_le16((u16 *)(mbase + PCI_COMMAND),
-		 in_le16((u16 *)(mbase + PCI_COMMAND)) |
-		 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+		in_le16((u16 *)(mbase + PCI_COMMAND)) |
+		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	out_le16(mbase + 0x200,0xcaad);			/* Setting vendor ID */
 	out_le16(mbase + 0x202,0xfeed);			/* Setting device ID */
 	attempts = 10;

cpu/ppc4xx/440spe_pcie.h

@@ -38,6 +38,7 @@
 #define DCRN_PEGPL_REGBAL(base)		(base + 0x13)
 #define DCRN_PEGPL_REGMSK(base)		(base + 0x14)
 #define DCRN_PEGPL_SPECIAL(base)	(base + 0x15)
+#define DCRN_PEGPL_CFG(base)		(base + 0x16)
 
 /*
  * System DCRs (SDRs)
@@ -161,20 +162,7 @@
 	mtdcr(DCRN_SDR0_CFGADDR, offset); \
 	mtdcr(DCRN_SDR0_CFGDATA,data);})
 
-#define PCIE_IN(opcode, ret, addr) \
-	__asm__ __volatile__(			\
-		"sync\n"			\
-		#opcode " %0,0,%1\n"		\
-		"1: twi 0,%0,0\n"		\
-		"isync\n"			\
-		"b 3f\n"			\
-		"2: li %0,-1\n"			\
-		"3:\n"				\
-		".section __ex_table,\"a\"\n"	\
-		".balign 4\n"			\
-		".long 1b,2b\n"			\
-		".previous\n"			\
-		: "=r" (ret) : "r" (addr), "m" (*addr));
+#define GPL_DMER_MASK_DISA	0x02000000
 
 int ppc440spe_init_pcie(void);
 int ppc440spe_init_pcie_rootport(int port);

cpu/ppc4xx/4xx_enet.c

@@ -138,7 +138,8 @@
 #define BI_PHYMODE_MII   7
 #endif
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
+	defined(CONFIG_440GRX) || defined(CONFIG_440SP)
 #define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
 #endif
 
@@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	int ethgroup = -1;
 #endif
 #endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long mfr;
 #endif
 
@@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	__asm__ volatile ("eieio");
 
 	/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* provide clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
 	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	if (failsafe <= 0)
 		printf("\nProblem resetting EMAC!\n");
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* remove clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
 	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -920,8 +924,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 	/* set speed */
 	if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 		unsigned long pfc1;
 
 		mfsdr (sdr_pfc1, pfc1);

cpu/ppc4xx/traps.c

@@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs)
 	int uncorr_ecc = 0;
 #endif
 
-	/* Probing PCI(E) using config cycles may cause this exception
-	 * when a device is not present. To gracefully recover in such
-	 * scenarios config read/write routines need to be instrumented in
-	 * order to return via fixup handler. For examples refer to
-	 * pcie_in_8(), pcie_in_le16() and pcie_in_le32()
-	 */
 	if ((fixup = search_exception_table(regs->nip)) != 0) {
 		regs->nip = fixup;
 		val = mfspr(MCSR);

cpu/pxa/mmc.c

@@ -438,11 +438,11 @@ mmc_init(int verbose)
 		/* FIXME fill in the correct size (is set to 32MByte) */
 		mmc_dev.blksz = 512;
 		mmc_dev.lba = 0x10000;
-		sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
+		sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
 				cid->id[0], cid->id[1], cid->id[2],
 				cid->sn[0], cid->sn[1], cid->sn[2]);
-		sprintf(mmc_dev.product,"%s",cid->name);
-		sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
+		sprintf((char*)mmc_dev.product,"%s",cid->name);
+		sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
 		mmc_dev.removable = 0;
 		mmc_dev.block_read = mmc_bread;
 

drivers/at45.c

@@ -27,33 +27,31 @@
 /*
  * spi.c API
  */
-extern unsigned int	AT91F_SpiWrite (AT91PS_DataflashDesc pDesc);
-extern void 		AT91F_SpiEnable(int cs);
+extern unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc);
+extern void AT91F_SpiEnable(int cs);
 
 #define AT91C_TIMEOUT_WRDY			200000
 
-
 /*----------------------------------------------------------------------*/
 /* \fn    AT91F_DataFlashSendCommand					*/
 /* \brief Generic function to send a command to the dataflash		*/
 /*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char OpCode,
-	unsigned int CmdSize,
-	unsigned int DataflashAddress)
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash,
+						 unsigned char OpCode,
+						 unsigned int CmdSize,
+						 unsigned int DataflashAddress)
 {
 	unsigned int adr;
 
-	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+	if ((pDataFlash->pDataFlashDesc->state) != IDLE)
 		return DATAFLASH_BUSY;
 
 	/* process the address to obtain page address and byte address */
 	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) <<
-		pDataFlash->pDevice->page_offset) + (DataflashAddress %
-		(pDataFlash->pDevice->pages_size));
+		pDataFlash->pDevice->page_offset) +
+			(DataflashAddress % (pDataFlash->pDevice->pages_size));
 
-	/* fill the  command  buffer */
+	/* fill the command buffer */
 	pDataFlash->pDataFlashDesc->command[0] = OpCode;
 	if (pDataFlash->pDevice->pages_number >= 16384) {
 		pDataFlash->pDataFlashDesc->command[1] =
@@ -78,16 +76,16 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
 	pDataFlash->pDataFlashDesc->command[7] = 0;
 
 	/* Initialize the SpiData structure for the spi write fuction */
-	pDataFlash->pDataFlashDesc->tx_cmd_pt   =
+	pDataFlash->pDataFlashDesc->tx_cmd_pt =
 		pDataFlash->pDataFlashDesc->command;
-	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt   =
+	pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt =
 		pDataFlash->pDataFlashDesc->command;
-	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize;
+	pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
 
 	/* send the command and read the data */
-	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); }
-
+	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
 
 /*----------------------------------------------------------------------*/
 /* \fn    AT91F_DataFlashGetStatus					*/
@@ -98,50 +96,49 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
 	AT91S_DataFlashStatus status;
 
 	/* if a transfert is in progress ==> return 0 */
-	if( (pDesc->state) != IDLE)
+	if ((pDesc->state) != IDLE)
 		return DATAFLASH_BUSY;
 
 	/* first send the read status command (D7H) */
 	pDesc->command[0] = DB_STATUS;
 	pDesc->command[1] = 0;
 
-	pDesc->DataFlash_state  = GET_STATUS;
-	pDesc->tx_data_size 	= 0;	/* Transmit the command */
-					/* and receive response */
-	pDesc->tx_cmd_pt 		= pDesc->command;
-	pDesc->rx_cmd_pt 		= pDesc->command;
-	pDesc->rx_cmd_size 		= 2;
-	pDesc->tx_cmd_size 		= 2;
-	status = AT91F_SpiWrite (pDesc);
+	pDesc->DataFlash_state = GET_STATUS;
+	pDesc->tx_data_size = 0;	/* Transmit the command */
+	/* and receive response */
+	pDesc->tx_cmd_pt = pDesc->command;
+	pDesc->rx_cmd_pt = pDesc->command;
+	pDesc->rx_cmd_size = 2;
+	pDesc->tx_cmd_size = 2;
+	status = AT91F_SpiWrite(pDesc);
 
-	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+	pDesc->DataFlash_state = *((unsigned char *)(pDesc->rx_cmd_pt) + 1);
 
 	return status;
 }
 
-
 /*----------------------------------------------------------------------*/
 /* \fn    AT91F_DataFlashWaitReady					*/
 /* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
 /*----------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
-pDataFlashDesc, unsigned int timeout)
+						pDataFlashDesc,
+						unsigned int timeout)
 {
 	pDataFlashDesc->DataFlash_state = IDLE;
 
 	do {
 		AT91F_DataFlashGetStatus(pDataFlashDesc);
 		timeout--;
-	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
-			(timeout > 0) );
+	} while (((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
+		 (timeout > 0));
 
-	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+	if ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
 		return DATAFLASH_ERROR;
 
 	return DATAFLASH_OK;
 }
 
-
 /*--------------------------------------------------------------------------*/
 /* Function Name       : AT91F_DataFlashContinuousRead 			    */
 /* Object              : Continuous stream Read 			    */
@@ -151,17 +148,17 @@ pDataFlashDesc, unsigned int timeout)
 /*                     : <sizeToRead> = data buffer size		    */
 /* Return value		: State of the dataflash			    */
 /*--------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
-	AT91PS_DataFlash pDataFlash,
-	int src,
-	unsigned char *dataBuffer,
-	int sizeToRead )
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(
+				AT91PS_DataFlash pDataFlash,
+				int src,
+				unsigned char *dataBuffer,
+				int sizeToRead)
 {
 	AT91S_DataFlashStatus status;
 	/* Test the size to read in the device */
-	if ( (src + sizeToRead) >
-		(pDataFlash->pDevice->pages_size *
-		(pDataFlash->pDevice->pages_number)))
+	if ((src + sizeToRead) >
+			(pDataFlash->pDevice->pages_size *
+				(pDataFlash->pDevice->pages_number)))
 		return DATAFLASH_MEMORY_OVERFLOW;
 
 	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
@@ -169,13 +166,12 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
 	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
 	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
 
-	status = AT91F_DataFlashSendCommand
-			(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+	status = AT91F_DataFlashSendCommand(
+			pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
 	/* Send the command to the dataflash */
-	return(status);
+	return (status);
 }
 
-
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_DataFlashPagePgmBuf			     */
 /* Object              : Main memory page program thru buffer 1 or buffer 2  */
@@ -185,11 +181,10 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
 /*                     : <SizeToWrite> = data buffer size		     */
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int SizeToWrite)
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash,
+						unsigned char *src,
+						unsigned int dest,
+						unsigned int SizeToWrite)
 {
 	int cmdsize;
 	pDataFlash->pDataFlashDesc->tx_data_pt = src;
@@ -201,9 +196,9 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
 	/* Send the command to the dataflash */
 	if (pDataFlash->pDevice->pages_number >= 16384)
 		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1,
-cmdsize, dest)); }
-
+	return (AT91F_DataFlashSendCommand(
+			pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
 
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_MainMemoryToBufferTransfert		     */
@@ -214,26 +209,29 @@ cmdsize, dest)); }
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int page)
+					AT91PS_DataFlash
+					pDataFlash,
+					unsigned char
+					BufferCommand,
+					unsigned int page)
 {
 	int cmdsize;
 	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_PAGE_2_BUF1_TRF)
-		&& (BufferCommand != DB_PAGE_2_BUF2_TRF))
+	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) &&
+			(BufferCommand != DB_PAGE_2_BUF2_TRF)) {
 		return DATAFLASH_BAD_COMMAND;
+	}
 
 	/* no data to transmit or receive */
 	pDataFlash->pDataFlashDesc->tx_data_size = 0;
 	cmdsize = 4;
 	if (pDataFlash->pDevice->pages_number >= 16384)
 		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
-page*pDataFlash->pDevice->pages_size));
+	return (AT91F_DataFlashSendCommand(
+			pDataFlash, BufferCommand, cmdsize,
+			page * pDataFlash->pDevice->pages_size));
 }
 
-
 /*-------------------------------------------------------------------------- */
 /* Function Name       : AT91F_DataFlashWriteBuffer			     */
 /* Object              : Write data to the internal sram buffer 1 or 2	     */
@@ -244,58 +242,61 @@ page*pDataFlash->pDevice->pages_size));
 /*                     : <SizeToWrite> = data buffer size		     */
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned char *dataBuffer,
-	unsigned int bufferAddress,
-	int SizeToWrite )
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(
+					AT91PS_DataFlash pDataFlash,
+					unsigned char BufferCommand,
+					unsigned char *dataBuffer,
+					unsigned int bufferAddress,
+					int SizeToWrite)
 {
 	int cmdsize;
 	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_BUF1_WRITE)
-		&& (BufferCommand != DB_BUF2_WRITE))
+	if ((BufferCommand != DB_BUF1_WRITE) &&
+			(BufferCommand != DB_BUF2_WRITE)) {
 		return DATAFLASH_BAD_COMMAND;
+	}
 
 	/* buffer address must be lower than page size */
 	if (bufferAddress > pDataFlash->pDevice->pages_size)
 		return DATAFLASH_BAD_ADDRESS;
 
-	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
+	if ((pDataFlash->pDataFlashDesc->state) != IDLE)
 		return DATAFLASH_BUSY;
 
 	/* Send first Write Command */
 	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
 	pDataFlash->pDataFlashDesc->command[1] = 0;
 	if (pDataFlash->pDevice->pages_number >= 16384) {
-	    	pDataFlash->pDataFlashDesc->command[2] = 0;
-	    	pDataFlash->pDataFlashDesc->command[3] =
+		pDataFlash->pDataFlashDesc->command[2] = 0;
+		pDataFlash->pDataFlashDesc->command[3] =
 			(unsigned char)(((unsigned int)(bufferAddress &
-				pDataFlash->pDevice->byte_mask)) >> 8);
-	    	pDataFlash->pDataFlashDesc->command[4] =
-			(unsigned char)((unsigned int)bufferAddress  & 0x00FF);
+							pDataFlash->pDevice->
+							byte_mask)) >> 8);
+		pDataFlash->pDataFlashDesc->command[4] =
+			(unsigned char)((unsigned int)bufferAddress & 0x00FF);
 		cmdsize = 5;
 	} else {
-	    	pDataFlash->pDataFlashDesc->command[2] =
+		pDataFlash->pDataFlashDesc->command[2] =
 			(unsigned char)(((unsigned int)(bufferAddress &
-				pDataFlash->pDevice->byte_mask)) >> 8);
-	    	pDataFlash->pDataFlashDesc->command[3] =
-			(unsigned char)((unsigned int)bufferAddress  & 0x00FF);
-	    	pDataFlash->pDataFlashDesc->command[4] = 0;
+							pDataFlash->pDevice->
+							byte_mask)) >> 8);
+		pDataFlash->pDataFlashDesc->command[3] =
+			(unsigned char)((unsigned int)bufferAddress & 0x00FF);
+		pDataFlash->pDataFlashDesc->command[4] = 0;
 		cmdsize = 4;
 	}
 
-	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 =
+	pDataFlash->pDataFlashDesc->tx_cmd_pt =
 		pDataFlash->pDataFlashDesc->command;
 	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 =
+	pDataFlash->pDataFlashDesc->rx_cmd_pt =
 		pDataFlash->pDataFlashDesc->command;
 	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize;
 
-	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer;
-	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer;
-	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite;
-	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite;
+	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
 
 	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
 }
@@ -309,22 +310,22 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_PageErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int page)
+					AT91PS_DataFlash pDataFlash,
+					unsigned int page)
 {
 	int cmdsize;
 	/* Test if the buffer command is legal */
 	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
 
 	cmdsize = 4;
 	if (pDataFlash->pDevice->pages_number >= 16384)
 		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize,
-page*pDataFlash->pDevice->pages_size));
+	return (AT91F_DataFlashSendCommand(pDataFlash,
+				DB_PAGE_ERASE, cmdsize,
+				page * pDataFlash->pDevice->pages_size));
 }
 
-
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_BlockErase                                    */
 /* Object              : Erase a Block 					     */
@@ -334,18 +335,19 @@ page*pDataFlash->pDevice->pages_size));
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_BlockErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int block)
+				AT91PS_DataFlash pDataFlash,
+				unsigned int block)
 {
 	int cmdsize;
 	/* Test if the buffer command is legal */
 	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
 	cmdsize = 4;
 	if (pDataFlash->pDevice->pages_number >= 16384)
 		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize,
-block*8*pDataFlash->pDevice->pages_size));
+	return (AT91F_DataFlashSendCommand(pDataFlash, DB_BLOCK_ERASE, cmdsize,
+					block * 8 *
+					pDataFlash->pDevice->pages_size));
 }
 
 /*---------------------------------------------------------------------------*/
@@ -356,17 +358,16 @@ block*8*pDataFlash->pDevice->pages_size));
 /*                     : <dest> = main memory address			     */
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int dest )
+AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash,
+					unsigned char BufferCommand,
+					unsigned int dest)
 {
 	int cmdsize;
 	/* Test if the buffer command is correct */
 	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+			(BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+			(BufferCommand != DB_BUF2_PAGE_PGM) &&
+			(BufferCommand != DB_BUF2_PAGE_ERASE_PGM))
 		return DATAFLASH_BAD_COMMAND;
 
 	/* no data to transmit or receive */
@@ -376,9 +377,9 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain (
 	if (pDataFlash->pDevice->pages_number >= 16384)
 		cmdsize = 5;
 	/* Send the command to the dataflash */
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
-						dest)); }
-
+	return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand,
+						cmdsize, dest));
+}
 
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_PartialPageWrite				     */
@@ -387,11 +388,10 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain (
 /*			: <AdrInpage> = adr to begin the fading		     */
 /*                     : <length> = Number of bytes to erase		     */
 /*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int size)
+AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash,
+					unsigned char *src,
+					unsigned int dest,
+					unsigned int size)
 {
 	unsigned int page;
 	unsigned int AdrInPage;
@@ -400,10 +400,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
 	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
 
 	/* Read the contents of the page in the Sram Buffer */
-	AT91F_MainMemoryToBufferTransfert(pDataFlash,
-						DB_PAGE_2_BUF1_TRF, page);
+	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
 	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-						AT91C_TIMEOUT_WRDY);
+				 AT91C_TIMEOUT_WRDY);
 	/*Update the SRAM buffer */
 	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
 					AdrInPage, size);
@@ -416,12 +415,13 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
 		AT91F_PageErase(pDataFlash, page);
 		/* Rewrite the modified Sram Buffer in the main memory */
 		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-						AT91C_TIMEOUT_WRDY);
+					 AT91C_TIMEOUT_WRDY);
 	}
 
 	/* Rewrite the modified Sram Buffer in the main memory */
-	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
-				(page*pDataFlash->pDevice->pages_size)));
+	return (AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
+					(page *
+					 pDataFlash->pDevice->pages_size)));
 }
 
 /*---------------------------------------------------------------------------*/
@@ -431,11 +431,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
 /*                     : <dest> = dataflash adress			     */
 /*                     : <size> = data buffer size			     */
 /*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	int dest,
-	int size )
+AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash,
+						unsigned char *src,
+						int dest, int size)
 {
 	unsigned int length;
 	unsigned int page;
@@ -443,26 +441,24 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(
 
 	AT91F_SpiEnable(pDataFlash->pDevice->cs);
 
-	if ( (dest + size) > (pDataFlash->pDevice->pages_size *
-					(pDataFlash->pDevice->pages_number)))
+	if ((dest + size) > (pDataFlash->pDevice->pages_size *
+			(pDataFlash->pDevice->pages_number)))
 		return DATAFLASH_MEMORY_OVERFLOW;
 
 	/* If destination does not fit a page start address */
-	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 )
-	{
-		length = pDataFlash->pDevice->pages_size -
-				(dest %
-				((unsigned int)
-				(pDataFlash->pDevice->pages_size)));
+	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) {
+		length =
+			pDataFlash->pDevice->pages_size -
+			(dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
 
 		if (size < length)
 			length = size;
 
-		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+		if (!AT91F_PartialPageWrite(pDataFlash, src, dest, length))
 			return DATAFLASH_ERROR;
 
 		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-			AT91C_TIMEOUT_WRDY);
+					 AT91C_TIMEOUT_WRDY);
 
 		/* Update size, source and destination pointers */
 		size -= length;
@@ -470,78 +466,77 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(
 		src += length;
 	}
 
-	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+	while ((size - pDataFlash->pDevice->pages_size) >= 0) {
 		/* program dataflash page */
 		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
 
 		status = AT91F_DataFlashWriteBuffer(pDataFlash,
-				DB_BUF1_WRITE, src, 0,
-				pDataFlash->pDevice->pages_size);
+					DB_BUF1_WRITE, src, 0,
+					pDataFlash->pDevice->
+					pages_size);
 		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-						AT91C_TIMEOUT_WRDY);
+					 AT91C_TIMEOUT_WRDY);
 
 		status = AT91F_PageErase(pDataFlash, page);
 		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-						AT91C_TIMEOUT_WRDY);
+					 AT91C_TIMEOUT_WRDY);
 		if (!status)
 			return DATAFLASH_ERROR;
 
-		status = AT91F_WriteBufferToMain (pDataFlash,
-						DB_BUF1_PAGE_PGM, dest);
-		if(!status)
+		status = AT91F_WriteBufferToMain(pDataFlash,
+					 DB_BUF1_PAGE_PGM, dest);
+		if (!status)
 			return DATAFLASH_ERROR;
 
 		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-						AT91C_TIMEOUT_WRDY);
+					 AT91C_TIMEOUT_WRDY);
 
 		/* Update size, source and destination pointers */
 		size -= pDataFlash->pDevice->pages_size;
 		dest += pDataFlash->pDevice->pages_size;
-		src  += pDataFlash->pDevice->pages_size;
+		src += pDataFlash->pDevice->pages_size;
 	}
 
 	/* If still some bytes to read */
-	if ( size > 0 ) {
+	if (size > 0) {
 		/* program dataflash page */
-		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+		if (!AT91F_PartialPageWrite(pDataFlash, src, dest, size))
 			return DATAFLASH_ERROR;
 
 		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-						AT91C_TIMEOUT_WRDY);
+					 AT91C_TIMEOUT_WRDY);
 	}
 	return DATAFLASH_OK;
 }
 
-
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_DataFlashRead 				     */
 /* Object              : Read a block in dataflash			     */
 /* Input Parameters    : 						     */
 /* Return value		: 						     */
 /*---------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
-	AT91PS_DataFlash pDataFlash,
-	unsigned long addr,
-	unsigned long size,
-	char *buffer)
+int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash,
+			unsigned long addr, unsigned long size, char *buffer)
 {
 	unsigned long SizeToRead;
 
 	AT91F_SpiEnable(pDataFlash->pDevice->cs);
 
-	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+	if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
 					AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
 		return -1;
 
 	while (size) {
-		SizeToRead = (size < 0x8000)? size:0x8000;
+		SizeToRead = (size < 0x8000) ? size : 0x8000;
 
 		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
-					AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+					AT91C_TIMEOUT_WRDY) !=
+						DATAFLASH_OK)
 			return -1;
 
-		if (AT91F_DataFlashContinuousRead (pDataFlash, addr,
-				(uchar *) buffer, SizeToRead) != DATAFLASH_OK)
+		if (AT91F_DataFlashContinuousRead(pDataFlash, addr,
+						(uchar *) buffer,
+						SizeToRead) != DATAFLASH_OK)
 			return -1;
 
 		size -= SizeToRead;
@@ -558,9 +553,10 @@ int AT91F_DataFlashRead(
 /* Input Parameters    : 						     */
 /* Return value	       : Dataflash status register			     */
 /*---------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) {
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
 	AT91F_SpiEnable(cs);
 	AT91F_DataFlashGetStatus(pDesc);
-	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+	return ((pDesc->command[1] == 0xFF) ? 0 : pDesc->command[1] & 0x3C);
 }
 #endif

drivers/nand/nand_util.c

@@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 
 		if (!opts->quiet) {
 			unsigned long long n =(unsigned long long)
-				 (erase.addr+meminfo->erasesize-opts->offset)
-				 * 100;
-			int percent = (int)do_div(n, erase_length);
+				(erase.addr + meminfo->erasesize - opts->offset)
+				* 100;
+			int percent;
+
+			do_div(n, erase_length);
+			percent = (int)n;
 
 			/* output progress message only at whole percent
 			 * steps to reduce the number of messages printed
@@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
 		if (!opts->quiet) {
 			unsigned long long n = (unsigned long long)
 				 (opts->length-imglen) * 100;
-			int percent = (int)do_div(n, opts->length);
+			int percent;
+
+			do_div(n, opts->length);
+			percent = (int)n;
+
 			/* output progress message only at whole percent
 			 * steps to reduce the number of messages printed
 			 * on (slow) serial consoles
@@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
 		if (!opts->quiet) {
 			unsigned long long n = (unsigned long long)
 				 (opts->length-imglen) * 100;
-			int percent = (int)do_div(n ,opts->length);
+			int percent;
+
+			do_div(n, opts->length);
+			percent = (int)n;
+
 			/* output progress message only at whole percent
 			 * steps to reduce the number of messages printed
 			 * on (slow) serial consoles

drivers/onenand/Makefile

@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2005-2007 Samsung Electronics.
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)libonenand.a
+
+COBJS	:= onenand_base.o onenand_bbt.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

drivers/onenand/onenand_bbt.c

@@ -0,0 +1,265 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_bbt.c
+ *
+ *  Bad Block Table support for the OneNAND driver
+ *
+ *  Copyright(c) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  TODO:
+ *    Split BBT core and chip specific BBT.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <malloc.h>
+
+#include <asm/errno.h>
+
+/**
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @param buf		the buffer to search
+ * @param len		the length of buffer to search
+ * @param paglen	the pagelength
+ * @param td		search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers. Same as check_pattern, but
+ * no optional empty check and the pattern is expected to start
+ * at offset 0.
+ */
+static int check_short_pattern(uint8_t * buf, int len, int paglen,
+			       struct nand_bbt_descr *td)
+{
+	int i;
+	uint8_t *p = buf;
+
+	/* Compare the pattern */
+	for (i = 0; i < td->len; i++) {
+		if (p[i] != td->pattern[i])
+			return -1;
+	}
+	return 0;
+}
+
+/**
+ * create_bbt - [GENERIC] Create a bad block table by scanning the device
+ * @param mtd		MTD device structure
+ * @param buf		temporary buffer
+ * @param bd		descriptor for the good/bad block search pattern
+ * @param chip		create the table for a specific chip, -1 read all chips.
+ *              Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Create a bad block table by scanning the device
+ * for the given good/bad block identify pattern
+ */
+static int create_bbt(struct mtd_info *mtd, uint8_t * buf,
+		      struct nand_bbt_descr *bd, int chip)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int i, j, numblocks, len, scanlen;
+	int startblock;
+	loff_t from;
+	size_t readlen, ooblen;
+
+	printk(KERN_INFO "Scanning device for bad blocks\n");
+
+	len = 1;
+
+	/* We need only read few bytes from the OOB area */
+	scanlen = ooblen = 0;
+	readlen = bd->len;
+
+	/* chip == -1 case only */
+	/* Note that numblocks is 2 * (real numblocks) here;
+	 * see i += 2 below as it makses shifting and masking less painful
+	 */
+	numblocks = mtd->size >> (bbm->bbt_erase_shift - 1);
+	startblock = 0;
+	from = 0;
+
+	for (i = startblock; i < numblocks;) {
+		int ret;
+
+		for (j = 0; j < len; j++) {
+			size_t retlen;
+
+			/* No need to read pages fully,
+			 * just read required OOB bytes */
+			ret = onenand_read_oob(mtd,
+					     from + j * mtd->oobblock +
+					     bd->offs, readlen, &retlen,
+					     &buf[0]);
+
+			if (ret && ret != -EAGAIN) {
+				printk("ret = %d\n", ret);
+				return ret;
+			}
+
+			if (check_short_pattern
+			    (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
+				bbm->bbt[i >> 3] |= 0x03 << (i & 0x6);
+				printk(KERN_WARNING
+				       "Bad eraseblock %d at 0x%08x\n", i >> 1,
+				       (unsigned int)from);
+				break;
+			}
+		}
+		i += 2;
+		from += (1 << bbm->bbt_erase_shift);
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_memory_bbt - [GENERIC] create a memory based bad block table
+ * @param mtd		MTD device structure
+ * @param bd		descriptor for the good/bad block search pattern
+ *
+ * The function creates a memory based bbt by scanning the device
+ * for manufacturer / software marked good / bad blocks
+ */
+static inline int onenand_memory_bbt(struct mtd_info *mtd,
+				     struct nand_bbt_descr *bd)
+{
+	unsigned char data_buf[MAX_ONENAND_PAGESIZE];
+
+	bd->options &= ~NAND_BBT_SCANEMPTY;
+	return create_bbt(mtd, data_buf, bd, -1);
+}
+
+/**
+ * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad
+ * @param mtd		MTD device structure
+ * @param offs		offset in the device
+ * @param allowbbt	allow access to bad block table region
+ */
+static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int block;
+	uint8_t res;
+
+	/* Get block number * 2 */
+	block = (int)(offs >> (bbm->bbt_erase_shift - 1));
+	res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03;
+
+	DEBUG(MTD_DEBUG_LEVEL2,
+	      "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+	      (unsigned int)offs, block >> 1, res);
+
+	switch ((int)res) {
+	case 0x00:
+		return 0;
+	case 0x01:
+		return 1;
+	case 0x02:
+		return allowbbt ? 0 : 1;
+	}
+
+	return 1;
+}
+
+/**
+ * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s)
+ * @param mtd		MTD device structure
+ * @param bd		descriptor for the good/bad block search pattern
+ *
+ * The function checks, if a bad block table(s) is/are already
+ * available. If not it scans the device for manufacturer
+ * marked good / bad blocks and writes the bad block table(s) to
+ * the selected place.
+ *
+ * The bad block table memory is allocated here. It must be freed
+ * by calling the onenand_free_bbt function.
+ *
+ */
+int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int len, ret = 0;
+
+	len = mtd->size >> (this->erase_shift + 2);
+	/* Allocate memory (2bit per block) */
+	bbm->bbt = malloc(len);
+	if (!bbm->bbt) {
+		printk(KERN_ERR "onenand_scan_bbt: Out of memory\n");
+		return -ENOMEM;
+	}
+	/* Clear the memory bad block table */
+	memset(bbm->bbt, 0x00, len);
+
+	/* Set the bad block position */
+	bbm->badblockpos = ONENAND_BADBLOCK_POS;
+
+	/* Set erase shift */
+	bbm->bbt_erase_shift = this->erase_shift;
+
+	if (!bbm->isbad_bbt)
+		bbm->isbad_bbt = onenand_isbad_bbt;
+
+	/* Scan the device to build a memory based bad block table */
+	if ((ret = onenand_memory_bbt(mtd, bd))) {
+		printk(KERN_ERR
+		       "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n");
+		free(bbm->bbt);
+		bbm->bbt = NULL;
+	}
+
+	return ret;
+}
+
+/*
+ * Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks.
+ */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern,
+};
+
+/**
+ * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device
+ * @param mtd		MTD device structure
+ *
+ * This function selects the default bad block table
+ * support for the device and calls the onenand_scan_bbt function
+ */
+int onenand_default_bbt(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm;
+
+	this->bbm = malloc(sizeof(struct bbm_info));
+	if (!this->bbm)
+		return -ENOMEM;
+
+	bbm = this->bbm;
+
+	memset(bbm, 0, sizeof(struct bbm_info));
+
+	/* 1KB page has same configuration as 2KB page */
+	if (!bbm->badblock_pattern)
+		bbm->badblock_pattern = &largepage_memorybased;
+
+	return onenand_scan_bbt(mtd, bbm->badblock_pattern);
+}
+
+#endif /* CFG_CMD_ONENAND */

drivers/qe/qe.c

@@ -30,6 +30,8 @@
 qe_map_t		*qe_immr = NULL;
 static qe_snum_t	snums[QE_NUM_OF_SNUM];
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
 {
 	u32           cecr;
@@ -51,8 +53,6 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
 
 uint qe_muram_alloc(uint size, uint align)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint	retloc;
 	uint	align_mask, off;
 	uint	savebase;
@@ -158,8 +158,6 @@ void qe_put_snum(u8 snum)
 
 void qe_init(uint qe_base)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Init the QE IMMR base */
 	qe_immr = (qe_map_t *)qe_base;
 
@@ -204,7 +202,6 @@ void qe_assign_page(uint snum, uint para_ram_base)
 
 int qe_set_brg(uint brg, uint rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile uint	*bp;
 	u32		divisor;
 	int		div16 = 0;

drivers/serial_xuartlite.c

@@ -24,7 +24,7 @@
 
 #include <config.h>
 
-#ifdef	CONFIG_MICROBLAZE
+#ifdef	CONFIG_XILINX_UARTLITE
 
 #include <asm/serial_xuartlite.h>
 

drivers/tsec.c

@@ -1262,10 +1262,10 @@ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
 		case MIIM_LXT971_SR2_100HDX:
 			priv->speed = 100;
 			priv->duplexity = 0;
+			break;
 		default:
 			priv->speed = 100;
 			priv->duplexity = 1;
-			break;
 		}
 	} else {
 		priv->speed = 0;

drivers/usb_ohci.c

@@ -93,6 +93,7 @@
 #ifdef CONFIG_PCI_OHCI
 static struct pci_device_id ohci_pci_ids[] = {
 	{0x10b9, 0x5237},	/* ULI1575 PCI OHCI module ids */
+	{0x1033, 0x0035},	/* NEC PCI OHCI module ids */
 	/* Please add supported PCI OHCI controller ids here */
 	{0, 0}
 };

drivers/usbdcore_mpc8xx.c

@@ -64,6 +64,8 @@
 #include "usbdcore_mpc8xx.h"
 #include "usbdcore_ep0.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define ERR(fmt, args...)\
 	serial_printf("ERROR : [%s] %s:%d: "fmt,\
 				__FILE__,__FUNCTION__,__LINE__, ##args)
@@ -1216,7 +1218,6 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr,
 #elif defined(CFG_USB_BRGCLK)
 
 	/* This has been tested with brgclk == 50MHz */
-	DECLARE_GLOBAL_DATA_PTR;
 	int divisor = 0;
 
 	if (gd->cpu_clk < 48000000L) {

include/asm-avr32/string.h

@@ -23,6 +23,6 @@
 #define __ASM_AVR32_STRING_H
 
 #define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t n);
+extern void *memset(void *s, int c, __kernel_size_t n);
 
 #endif /* __ASM_AVR32_STRING_H */

include/common.h

@@ -275,7 +275,7 @@ void	pciinfo	      (int, int);
 #   endif
     int	    is_pci_host		(struct pci_controller *);
 #if defined(CONFIG_440SPE)
-   void pcie_setup_hoses(void);
+   void pcie_setup_hoses(int busno);
 #endif
 #endif
 

include/config_cmd_all.h

@@ -59,6 +59,7 @@
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
 #define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_ONENAND	/* OneNAND support		*/
 #define CONFIG_CMD_PCI		/* pciinfo			*/
 #define CONFIG_CMD_PCMCIA	/* PCMCIA support		*/
 #define CONFIG_CMD_PING		/* ping support			*/
@@ -76,6 +77,6 @@
 #define CONFIG_CMD_USB		/* USB Support			*/
 #define CONFIG_CMD_VFD		/* VFD support (TRAB)		*/
 #define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
-#define CONFIG_CMD_MUX		/* AT91 MMC/SPI Mux Support     */
+#define CONFIG_CMD_AT91_SPIMUX	/* AT91 MMC/SPI Mux Support     */
 
 #endif	/* _CONFIG_CMD_ALL_H */

include/configs/ASH405.h

@@ -158,7 +158,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff

include/configs/CATcenter.h

@@ -399,6 +399,8 @@
 #define CFG_ENV_ADDR_REDUND	0xFFFFA000
 #define CFG_ENV_SIZE_REDUND	0x2000
 
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 

include/configs/CMS700.h

@@ -165,7 +165,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff

include/configs/FADS823.h

@@ -206,6 +206,7 @@
 #define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
 #define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

include/configs/FADS850SAR.h

@@ -156,6 +156,7 @@
 #define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
 #define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

include/configs/FPS850L.h

@@ -39,28 +39,44 @@
 #undef	CONFIG_8xx_CONS_SMC1
 #define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		19200
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 40020000" /* autoboot command	*/
+#define CONFIG_BAUDRATE		115200
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
-				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
-				"nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/fps850L/uImage\0"				\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-
 /*
  * BOOTP options
  */
@@ -80,24 +96,32 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_TIMEOFFSET
 
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
 
 
 /*
  * Miscellaneous configurable options
  */
 #define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
 #if defined(CONFIG_CMD_KGDB)
 #define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else

include/configs/FPS860L.h

@@ -40,18 +40,37 @@
 #define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		115200
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 40040000" /* autoboot command	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
-				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
-				"nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/fps850L/uImage\0"				\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
@@ -79,11 +98,11 @@
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
@@ -95,7 +114,14 @@
  * Miscellaneous configurable options
  */
 #define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
 #if defined(CONFIG_CMD_KGDB)
 #define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else

include/configs/HH405.h

@@ -217,7 +217,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff

include/configs/HUB405.h

@@ -157,7 +157,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff

include/configs/ICU862.h

@@ -234,6 +234,7 @@
 
 #define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
 #define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

include/configs/M5271EVB.h

@@ -54,13 +54,12 @@
  */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
 #define CFG_ENV_OFFSET		0x4000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH	1
 #else
 #define CFG_ENV_ADDR		0xffe04000
+#endif
 #define CFG_ENV_SECT_SIZE	0x2000
 #define CFG_ENV_IS_IN_FLASH	1
-#endif
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*
  * BOOTP options

include/configs/PLU405.h

@@ -177,7 +177,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff

include/configs/PPChameleonEVB.h

@@ -429,6 +429,8 @@
 #define CFG_ENV_ADDR_REDUND	0xFFFFA000
 #define CFG_ENV_SIZE_REDUND	0x2000
 
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
 #endif	/* ENVIRONMENT_IN_EEPROM */
 
 

include/configs/R360MPI.h

@@ -233,6 +233,7 @@
 #define	CFG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
 #define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
 #define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

include/configs/RRvision.h

@@ -235,6 +235,8 @@
 #define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */