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Merge git://www.denx.de/git/u-boot

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This commit is contained in:
Michal Simek 2007-09-11 00:29:27 +02:00
commit 9c73f4b811
347 changed files with 28297 additions and 5432 deletions
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1994
CHANGELOG
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File diff suppressed because it is too large Load Diff

45
CREDITS
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@ -147,6 +147,11 @@ N: Daniel Engstr
E: daniel@omicron.se
D: x86 port, Support for sc520_cdp board
N: Hayden Fraser
E: Hayden.Fraser@freescale.com
D: Support for ColdFire MCF5253
W: www.freescale.com
N: Dr. Wolfgang Grandegger
E: wg@denx.de
D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
@ -283,6 +288,11 @@ E: team@leox.org
D: Support for LEOX boards, DS164x RTC
W: http://www.leox.org
N: TsiChung Liew
E: Tsi-Chung.Liew@freescale.com
D: Support for ColdFire MCF523x, MCF532x, MCF5445x
W: www.freescale.com
N: Leif Lindholm
E: leif.lindholm@i3micro.com
D: Support for AMD dbau1550 board.
@ -297,6 +307,11 @@ N: Raymond Lo
E: lo@routefree.com
D: Support for DOS partitions
N: James MacAulay
E: james.macaulay@amirix.com
D: Suppport for Amirix AP1000
W: www.amirix.com
N: Dan Malek
E: dan@embeddedalley.com
D: FADSROM, the grandfather of all of this
@ -372,8 +387,9 @@ D: Support for the Wind River sbc405, sbc8240 board
W: http://www.windriver.com
N: Stefan Roese
E: stefan.roese@esd-electronics.com
D: AMCC PPC401/403/405GP Support; Windows environment support
E: sr@denx.de
D: AMCC PPC4xx Support
W: http://www.denx.de
N: Erwin Rol
E: erwin@muffin.org
@ -407,6 +423,11 @@ N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
N: Michal Simek
E: monstr@monstr.eu
D: Support for Microblaze, ML401, XUPV2P board
W: www.monstr.eu
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
@ -420,6 +441,11 @@ E: andrea.scian@dave-tech.it
D: Port to B2 board
W: www.dave-tech.it
N: Timur Tabi
E: timur@freescale.com
D: Support for MPC8349E-mITX
W: www.freescale.com
N: Rob Taylor
E: robt@flyingpig.com
D: Port to MBX860T and Sandpoint8240
@ -473,18 +499,3 @@ N: Alex Zuepke
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
N: James MacAulay
E: james.macaulay@amirix.com
D: Suppport for Amirix AP1000
W: www.amirix.com
N: Timur Tabi
E: timur@freescale.com
D: Support for MPC8349E-mITX
W: www.freescale.com
N: Michal Simek
E: monstr@monstr.eu
D: Support for Microblaze, ML401, XUPV2P board
W: www.monstr.eu

47
MAINTAINERS
View File

@ -42,6 +42,10 @@ Yuli Barcohen <yuli@arabellasw.com>
Rattler MPC8248
ZPC1900 MPC8265
Michael Barkowski <michael.barkowski@freescale.com>
MPC8323ERDB MPC8323
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
sacsng MPC8260
@ -158,12 +162,12 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
VOH405 PPC405EP
VOM405 PPC405EP
WUH405 PPC405EP
CMS700 PPC405EP
CMS700 PPC405EP
Niklaus Giger <niklaus.giger@netstal.com>
HCU4 PPC405GPr
HCU5 PPC440EPx
HCU4 PPC405GPr
HCU5 PPC440EPx
Frank Gottschling <fgottschling@eltec.de>
@ -217,6 +221,10 @@ The LEOX team <team@leox.org>
ELPT860 MPC860T
Dave Liu <daveliu@freescale.com>
MPC8360EMDS MPC8360
Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
@ -273,6 +281,10 @@ Denis Peter <d.peter@mpl.ch>
MIP405 PPC4xx
PIP405 PPC4xx
Kim Phillips <kim.phillips@freescale.com>
MPC8349EMDS MPC8349
Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
@ -296,6 +308,7 @@ Stefan Roese <sr@denx.de>
ocotea PPC440GX
p3p440 PPC440GP
pcs440ep PPC440EP
rainier PPC440GRx
sequoia PPC440EPx
sycamore PPC405GPr
taishan PPC440GX
@ -320,6 +333,11 @@ Peter De Schrijver <p2@mind.be>
ML2 PPC4xx
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
MPC8349E-mITX-GP MPC8349
Erik Theisen <etheisen@mindspring.com>
W7OLMC PPC4xx
@ -352,19 +370,6 @@ John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
MPC8349E-mITX-GP MPC8349
Kim Phillips <kim.phillips@freescale.com>
MPC8349EMDS MPC8349
Dave Liu <daveliu@freescale.com>
MPC8360EMDS MPC8360
-------------------------------------------------------------------------
Unknown / orphaned boards:
@ -606,6 +611,16 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
r5200 mcf52x2
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M5235EVB mcf52x2
M5329EVB mcf532x
M54455EVB mcf5445x
Hayden Fraser <Hayden.Fraser@freescale.com>
M5253EVBE mcf52x2
#########################################################################
# AVR32 Systems: #
# #

19
MAKEALL
View File

@ -204,6 +204,7 @@ LIST_4xx=" \
PLU405 \
PMC405 \
PPChameleonEVB \
rainier \
sbc405 \
sc3 \
sequoia \
@ -298,6 +299,7 @@ LIST_8260=" \
LIST_83xx=" \
MPC8313ERDB_33 \
MPC8313ERDB_66 \
MPC8323ERDB \
MPC832XEMDS \
MPC8349EMDS \
MPC8349ITX \
@ -339,7 +341,7 @@ LIST_85xx=" \
LIST_86xx=" \
MPC8641HPCN \
SBC8641D \
sbc8641d \
"
#########################################################################
@ -358,6 +360,12 @@ LIST_74xx=" \
ZUMA \
"
LIST_TSEC=" \
${LIST_85xx} \
${LIST_86xx} \
${LIST_83xx} \
"
LIST_7xx=" \
BAB7xx \
CPCI750 \
@ -612,11 +620,16 @@ LIST_coldfire=" \
EB+MCF-EV123 \
EB+MCF-EV123_internal \
idmr \
M5235EVB \
M5249EVB \
M5253EVB \
M5271EVB \
M5272C3 \
M5282EVB \
TASREG \
M5329EVB \
M54455EVB \
r5200 \
TASREG \
"
#########################################################################
@ -672,7 +685,7 @@ do
mips|mips_el| \
nios|nios2| \
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
x86|I486)
x86|I486|TSEC)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}

85
Makefile
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@ -190,6 +190,8 @@ endif
OBJS := $(addprefix $(obj),$(OBJS))
LIBS = lib_generic/libgeneric.a
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
LIBS += board/$(BOARDDIR)/lib$(BOARD).a
LIBS += cpu/$(CPU)/lib$(CPU).a
ifdef SOC
@ -210,13 +212,14 @@ LIBS += drivers/libdrivers.a
LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
LIBS += drivers/net/libnetdrv.a
LIBS += drivers/net/libnet.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
endif
LIBS += drivers/serial/libserial.a
LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/drivers/libpostdrivers.a
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
@ -1639,6 +1642,31 @@ ZPC1900_config: unconfig
## Coldfire
#########################################################################
M5235EVB_config \
M5235EVB_Flash16_config \
M5235EVB_Flash32_config: unconfig
@case "$@" in \
M5235EVB_config) FLASH=16;; \
M5235EVB_Flash16_config) FLASH=16;; \
M5235EVB_Flash32_config) FLASH=32;; \
esac; \
>include/config.h ; \
if [ "$${FLASH}" != "16" ] ; then \
echo "#define NORFLASH_PS32BIT 1" >> include/config.h ; \
echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \
else \
echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \
fi
@$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale
M5249EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
M5253EVBE_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
cobra5272_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
@ -1674,6 +1702,46 @@ TASREG_config : unconfig
r5200_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
M5329AFEE_config \
M5329BFEE_config : unconfig
@case "$@" in \
M5329AFEE_config) NAND=0;; \
M5329BFEE_config) NAND=16;; \
esac; \
>include/config.h ; \
if [ "$${NAND}" != "0" ] ; then \
echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
M54455EVB_config \
M54455EVB_atmel_config \
M54455EVB_intel_config \
M54455EVB_a33_config \
M54455EVB_a66_config \
M54455EVB_i33_config \
M54455EVB_i66_config : unconfig
@case "$@" in \
M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \
M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \
M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \
M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \
M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \
M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
esac; \
>include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "... with INTEL boot..." ; \
else \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "... with ATMEL boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
echo "... with $${FREQ}Hz input clock"
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
#########################################################################
## MPC83xx Systems
#########################################################################
@ -1690,7 +1758,7 @@ MPC8313ERDB_66_config: unconfig
echo -n "...66M..." ; \
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
MPC8323ERDB_config: unconfig
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
@ -1718,10 +1786,10 @@ MPC832XEMDS_SLAVE_config: unconfig
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
MPC8349EMDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale
MPC8349ITX_config \
MPC8349ITX_LOWBOOT_config \
@ -1735,7 +1803,7 @@ MPC8349ITXGP_config: unconfig
@if [ "$(findstring LOWBOOT,$@)" ] ; then \
echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
fi
@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx
@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
@ -1760,7 +1828,7 @@ MPC8360EMDS_SLAVE_config: unconfig
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
@ -1902,7 +1970,7 @@ TQM8560_config: unconfig
#########################################################################
MPC8641HPCN_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
sbc8641d_config: unconfig
@./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
@ -2267,6 +2335,9 @@ scpu_config: unconfig
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
trizepsiv_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250

12
README
View File

@ -136,6 +136,8 @@ Directory Hierarchy:
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
- mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- mips Files specific to MIPS CPUs
- mpc5xx Files specific to Freescale MPC5xx CPUs
- mpc5xxx Files specific to Freescale MPC5xxx CPUs
@ -336,7 +338,7 @@ The following options need to be configured:
CONFIG_OF_LIBFDT
* New libfdt-based support
* Adds the "fdt" command
* The bootm command does _not_ modify the fdt
* The bootm command automatically updates the fdt
CONFIG_OF_FLAT_TREE
* Deprecated, see CONFIG_OF_LIBFDT
@ -345,15 +347,13 @@ The following options need to be configured:
* The environment variable "disable_of", when set,
disables this functionality.
CONFIG_OF_FLAT_TREE_MAX_SIZE
The maximum size of the constructed OF tree.
OF_CPU - The proper name of the cpus node.
OF_SOC - The proper name of the soc node.
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
boards with QUICC Engines require OF_QE to set UCC mac addresses
CONFIG_OF_HAS_BD_T
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
@ -363,7 +363,7 @@ The following options need to be configured:
CONFIG_OF_HAS_UBOOT_ENV
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
* CONFIG_OF_LIBFDT - enables the "fdt env" command
* CONFIG_OF_FLAT_TREE - The resulting flat device tree
will have a copy of u-boot's environment variables

2
board/BuS/EB+MCF-EV123/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

304
board/BuS/EB+MCF-EV123/mii.c Normal file
View File

@ -0,0 +1,304 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
MCFGPIO_PEHLPAR = CFG_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_AMD79C874VC "AMD79C874VC"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
strcpy(info->phy_name,
STR_ID_AMD79C874VC);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
printf(STR_ID_AMD79C874VC);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

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1
board/ads5121/u-boot.lds
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@ -51,7 +51,6 @@ SECTIONS
{
cpu/mpc512x/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)

12
board/amcc/katmai/init.S
View File

@ -67,9 +67,9 @@ tlbtabA:
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@ -109,9 +109,9 @@ tlbtabB:
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

21
board/amcc/katmai/katmai.c
View File

@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void)
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = 1;
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for katmai card presence */
if (!katmai_pcie_card_present(i))
@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
bus++;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul (env, NULL, 10);
if (delay > 5)
printf ("Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!\n");
mdelay (delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
#endif
}
}

209
board/amcc/sequoia/cmd_sequoia.c
View File

@ -26,76 +26,185 @@
#include <command.h>
#include <i2c.h>
static u8 boot_533_nor[] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
/*
* There are 2 versions of production Sequoia & Rainier platforms.
* The primary difference is the reference clock. Those with
* 33333333 reference clocks will also have 667MHz rated
* processors. Not enough differences to have unique clock
* settings.
*
* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
* values are independent of the rest of the clock settings.
*
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* the only value affected for a 66MHz PCI and simply needs a +0x10.
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
/* check with Stefan on CFG_I2C_EEPROM_ADDR */
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
static u8 boot_533_nand[] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
static u8 boot_configs[][17] = {
{
(NOR_COMPATIBLE),
0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
};
static u8 boot_667_nor[] = {
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
};
static u8 boot_667_nand[] = {
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
/*
* Bytes 6,8,9,11 change for NAND boot
*/
static u8 nand_boot[] = {
0xd0, 0xa0, 0x68, 0x58
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 chip;
u8 *buf;
int cpu_freq;
u8 *buf, bNAND;
int x, y, nbytes, selcfg;
extern char console_buffer[];
if (argc < 3) {
if (argc < 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
cpu_freq = simple_strtol(argv[1], NULL, 10);
if (!((cpu_freq == 533) || (cpu_freq == 667))) {
printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
return 1;
}
/* use 0x52 as I2C EEPROM address for now */
chip = 0x52;
if ((strcmp(argv[2], "nor") != 0) &&
(strcmp(argv[2], "nand") != 0)) {
if ((strcmp(argv[1], "nor") != 0) &&
(strcmp(argv[1], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
if (strcmp(argv[2], "nand") == 0) {
switch (cpu_freq) {
default:
case 533:
buf = boot_533_nand;
break;
case 667:
buf = boot_667_nand;
break;
/* set the nand flag based on provided input */
if ((strcmp(argv[1], "nand") == 0))
bNAND = 1;
else
bNAND = 0;
printf("Available configurations: \n\n");
if (bNAND) {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nand compatible */
if (boot_configs[x][0] & NAND_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
} else {
switch (cpu_freq) {
default:
case 533:
buf = boot_533_nor;
break;
case 667:
buf = boot_667_nor;
break;
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nor compatible */
if (boot_configs[x][0] & NOR_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
}
if (i2c_write(chip, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", chip);
do {
nbytes = readline(" Selection [1-x / quit]: ");
if (nbytes) {
if (strcmp(console_buffer, "quit") == 0)
return 0;
selcfg = simple_strtol(console_buffer, NULL, 10);
if ((selcfg < 1) || (selcfg > y))
nbytes = 0;
}
} while (nbytes == 0);
y = (selcfg - 1);
for (x = 0; boot_configs[x][0] != 0; x++) {
if (bNAND) {
if (boot_configs[x][0] & NAND_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
} else {
if (boot_configs[x][0] & NOR_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
}
}
buf = &boot_configs[x][1];
if (bNAND) {
buf[6] = nand_boot[0];
buf[8] = nand_boot[1];
buf[9] = nand_boot[2];
buf[11] = nand_boot[3];
}
/* check CPLD register +5 for PCI 66MHz flag */
if (in8(CFG_BCSR_BASE + 5) & 0x01)
buf[5] += 0x10;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
bootstrap, 3, 0, do_bootstrap,
bootstrap, 2, 0, do_bootstrap,
"bootstrap - program the I2C bootstrap EEPROM\n",
"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
"<nand|nor> - strap to boot from NAND or NOR flash\n"
);

3
board/amcc/sequoia/init.S
View File

@ -126,6 +126,9 @@ tlbtab:
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry PCI IO Space - from sr@denx.de */
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

12
board/amcc/yucca/init.S
View File

@ -70,9 +70,9 @@ tlbtabA:
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@ -112,9 +112,9 @@ tlbtabB:
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

21
board/amcc/yucca/yucca.c
View File

@ -846,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void)
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = 1;
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
@ -874,8 +876,8 @@ void pcie_setup_hoses(void)
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
bus++;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
@ -895,10 +897,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul (env, NULL, 10);
if (delay > 5)
printf ("Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!\n");
mdelay (delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
#endif
}
}

16
board/cds/mpc8548cds/mpc8548cds.c
View File

@ -362,20 +362,28 @@ pci_init_board(void)
);
/* outbound memory */
/* inbound */
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 1,
pci_set_region(hose->regions + 2,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 2;
hose->region_count = 3;
/* relocate config table pointers */
hose->config_table = \
@ -534,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd)
#endif
#ifdef CONFIG_PCIE1
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
if (p != NULL) {
p[0] = 0;
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;

2
board/cobra5272/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
COBJS = $(BOARD).o flash.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

5
board/cobra5272/cobra5272.c
View File

@ -22,8 +22,7 @@
*/
#include <common.h>
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#include <asm/immap.h>
int checkboard (void)
@ -35,7 +34,7 @@ int checkboard (void)
long int initdram (int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;

303
board/cobra5272/mii.c Normal file
View File

@ -0,0 +1,303 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
} else {
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_AMD79C874VC "AMD79C874VC"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
strcpy(info->phy_name,
STR_ID_AMD79C874VC);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
printf(STR_ID_AMD79C874VC);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

4
board/esd/ash405/Makefile
View File

@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

44
board/esd/ash405/ash405.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -33,6 +34,7 @@
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
@ -164,17 +166,11 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
@ -218,35 +214,17 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
void reset_phy(void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#ifdef CONFIG_LXT971_NO_SLEEP
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}

5
board/esd/cms700/Makefile
View File

@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
COBJS = $(BOARD).o flash.o \
../common/misc.o \
$(CPLD) \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

39
board/esd/cms700/cms700.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2005
* (C) Copyright 2005-2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -68,9 +69,9 @@ int board_early_init_f (void)
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
return 0;
@ -94,13 +95,7 @@ int misc_init_r (void)
/*
* Setup and enable EEPROM write protection
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
return (0);
}
@ -153,11 +148,6 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
break;
}
}
@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP

8
board/esd/common/auto_update.c
View File

@ -24,14 +24,12 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
#endif
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#if defined(CFG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#endif
#include <fat.h>
#include <part.h>
@ -294,6 +292,8 @@ int au_do_update(int i, long sz)
rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
#else
rc = -1;
#endif
}
if (rc != 0) {

87
board/esd/common/esd405ep_nand.c Normal file
View File

@ -0,0 +1,87 @@
/*
* (C) Copyright 2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#include <asm/io.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
{
switch(cmd) {
case NAND_CTL_SETCLE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
break;
case NAND_CTL_CLRCLE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
break;
case NAND_CTL_SETALE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
break;
case NAND_CTL_CLRALE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
break;
case NAND_CTL_SETNCE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
break;
case NAND_CTL_CLRNCE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
break;
}
}
/*
* read device ready pin
*/
static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
{
if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
return 1;
return 0;
}
int board_nand_init(struct nand_chip *nand)
{
/*
* Set NAND-FLASH GPIO signals to defaults
*/
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
/*
* Initialize nand_chip structure
*/
nand->hwcontrol = esd405ep_nand_hwcontrol;
nand->dev_ready = esd405ep_nand_device_ready;
nand->eccmode = NAND_ECC_SOFT;
nand->chip_delay = NAND_BIG_DELAY_US;
nand->options = NAND_SAMSUNG_LP_OPTIONS;
return 0;
}
#endif

89
board/esd/cpci750/cpci750.c
View File

@ -55,6 +55,71 @@
#define DP(x)
#endif
static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
{"PCI0DLL_1 "}, /* 30 */
{"PCI0DLL_0 "}, /* 29 */
{"PCI1DLL_2 "}, /* 28 */
{"PCI1DLL_1 "}, /* 27 */
{"PCI1DLL_0 "}, /* 26 */
{"BbEP2En "}, /* 25 */
{"SDRAMRdDataDel"}, /* 24 */
{"SDRAMRdDel "}, /* 23 */
{"SDRAMSync "}, /* 22 */
{"SDRAMPipeSel_1"}, /* 21 */
{"SDRAMPipeSel_0"}, /* 20 */
{"SDRAMAddDel "}, /* 19 */
{"SDRAMClkSel "}, /* 18 */
{"Reserved(1!) "}, /* 17 */
{"PCIRty "}, /* 16 */
{"BootCSWidth_1 "}, /* 15 */
{"BootCSWidth_0 "}, /* 14 */
{"PCI1PadsCal "}, /* 13 */
{"PCI0PadsCal "}, /* 12 */
{"MultiMVId_1 "}, /* 11 */
{"MultiMVId_0 "}, /* 10 */
{"MultiGTEn "}, /* 09 */
{"Int60xArb "}, /* 08 */
{"CPUBusConfig_1"}, /* 07 */
{"CPUBusConfig_0"}, /* 06 */
{"DefIntSpc "}, /* 05 */
{0 }, /* 04 */
{"SROMAdd_1 "}, /* 03 */
{"SROMAdd_0 "}, /* 02 */
{"DRAMPadCal "}, /* 01 */
{"SInitEn "}, /* 00 */
{0 }, /* 31 */
{0 }, /* 30 */
{0 }, /* 29 */
{0 }, /* 28 */
{0 }, /* 27 */
{0 }, /* 26 */
{0 }, /* 25 */
{0 }, /* 24 */
{0 }, /* 23 */
{0 }, /* 22 */
{"JTAGCalBy "}, /* 21 */
{"GB2Sel "}, /* 20 */
{"GB1Sel "}, /* 19 */
{"DRAMPLL_MDiv_5"}, /* 18 */
{"DRAMPLL_MDiv_4"}, /* 17 */
{"DRAMPLL_MDiv_3"}, /* 16 */
{"DRAMPLL_MDiv_2"}, /* 15 */
{"DRAMPLL_MDiv_1"}, /* 14 */
{"DRAMPLL_MDiv_0"}, /* 13 */
{"GB0Sel "}, /* 12 */
{"DRAMPLLPU "}, /* 11 */
{"DRAMPLL_HIKVCO"}, /* 10 */
{"DRAMPLLNP "}, /* 09 */
{"DRAMPLL_NDiv_7"}, /* 08 */
{"DRAMPLL_NDiv_6"}, /* 07 */
{"CPUPadCal "}, /* 06 */
{"DRAMPLL_NDiv_5"}, /* 05 */
{"DRAMPLL_NDiv_4"}, /* 04 */
{"DRAMPLL_NDiv_3"}, /* 03 */
{"DRAMPLL_NDiv_2"}, /* 02 */
{"DRAMPLL_NDiv_1"}, /* 01 */
{"DRAMPLL_NDiv_0"}}; /* 00 */
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern flash_info_t flash_info[];
@ -901,21 +966,37 @@ void board_prebootm_init ()
dcache_disable ();
}
int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned int reset_sample_low;
unsigned int reset_sample_high;
unsigned int l, l1, l2;
GT_REG_READ(0x3c4, &reset_sample_low);
GT_REG_READ(0x3d4, &reset_sample_high);
printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
l2 = 0;
for (l=0; l<63; l++) {
if (show_config_tab[l][0] != 0) {
printf("%14s:%1x ", show_config_tab[l],
((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
l2++;
if ((l2 % 4) == 0)
printf("\n");
} else {
l1++;
}
if (l == 32)
reset_sample_low = reset_sample_high;
}
printf("\n");
return(0);
}
U_BOOT_CMD(
show_cfg, 1, 1, do_show_cfg,
"show_cfg- Show Marvell strapping register\n",
show_config, 1, 1, do_show_config,
"show_config - Show Marvell strapping register\n",
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
);

2
board/esd/cpci750/ide.c
View File

@ -43,6 +43,8 @@ int ide_preinit (void)
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
if (devbusfn == -1)
devbusfn = pci_find_device (0x1095, 0x3114, 0);
if (devbusfn != -1) {
status = 0;

5
board/esd/hh405/Makefile
View File

@ -28,7 +28,10 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

22
board/esd/hh405/hh405.c
View File

@ -5,7 +5,7 @@
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -476,12 +476,6 @@ int misc_init_r (void)
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Reset touch-screen controller
*/
@ -690,20 +684,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state

4
board/esd/hub405/Makefile
View File

@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

34
board/esd/hub405/hub405.c
View File

@ -152,12 +152,6 @@ int misc_init_r (void)
out32(GPIO0_OR, val);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* check board type and setup AP power
*/
@ -242,33 +236,5 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif

5
board/esd/plu405/Makefile
View File

@ -28,7 +28,10 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

56
board/esd/plu405/plu405.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -31,6 +32,8 @@
#define FPGA_DEBUG
#endif
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
@ -114,6 +117,10 @@ int misc_init_r (void)
int index;
int i;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
@ -177,17 +184,11 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
@ -226,24 +227,10 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
@ -262,31 +249,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#ifdef CONFIG_AUTO_UPDATE_SHOW
void board_auto_update_show(int au_active)
{
if (au_active) {
printf("\n Dies ist die board-funktion: Updating!!!\n");
} else {
printf("\n Dies ist die board-funktion: Updating done!!!\n");
}
}
#endif
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP

4
board/esd/voh405/Makefile
View File

@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

20
board/esd/voh405/voh405.c
View File

@ -194,12 +194,6 @@ int misc_init_r (void)
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
@ -340,17 +334,3 @@ void ide_set_reset(int on)
}
}
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif

4
board/esd/wuh405/Makefile
View File

@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

36
board/esd/wuh405/wuh405.c
View File

@ -169,12 +169,6 @@ int misc_init_r (void)
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
@ -218,35 +212,5 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif

3
board/fads/fads.h
View File

@ -71,7 +71,10 @@
#undef CONFIG_BOOTARGS
#undef CONFIG_WATCHDOG /* watchdog disabled */
#if !defined(CONFIG_MPC885ADS)
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
#endif
/*
* New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:

56
board/freescale/common/Makefile Normal file
View File

@ -0,0 +1,56 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
LIB = $(obj)lib$(VENDOR).a
COBJS := sys_eeprom.o \
pixis.o \
pq-mds-pib.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

3
board/freescale/common/pixis.c
View File

@ -27,6 +27,8 @@
#include <watchdog.h>
#include <asm/cache.h>
#ifdef CONFIG_FSL_PIXIS
#include "pixis.h"
@ -470,3 +472,4 @@ U_BOOT_CMD(
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
);
#endif /* CONFIG_FSL_PIXIS */

105
board/freescale/common/pq-mds-pib.c Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Tony Li <tony.li@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#ifdef CONFIG_PQ_MDS_PIB
#include "pq-mds-pib.h"
int pib_init(void)
{
u8 val8;
u8 orig_i2c_bus;
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0;
#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
/* Assign PIB PMC slot to desired PCI bus */
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
#if defined(CONFIG_MPC832XEMDS)
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
eieio();
#if defined(CONFIG_MPC832XEMDS)
printf("PCI 32bit bus on PMC2 &PMC3\n");
#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
#if defined(CONFIG_MPC8360EMDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
val8 = 0xdf;
i2c_write(0x20, 0x2, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x20, 0x3, 1, &val8, 1);
eieio();
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
val = 0;
i2c_write(0x26, 0x7, 1, &val, 1);
val = 0xf7;
i2c_write(0x26, 0x3, 1, &val, 1);
val = 0;
i2c_write(0x21, 0x6, 1, &val, 1);
i2c_write(0x21, 0x7, 1, &val, 1);
val = 0xdf;
i2c_write(0x21, 0x2, 1, &val, 1);
val = 0xef;
i2c_write(0x21, 0x3, 1, &val, 1);
eieio();
printf("QOC3 ATM card on PMC1\n");
#endif
#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
return 0;
}
#endif /* CONFIG_PQ_MDS_PIB */

9
board/freescale/common/pq-mds-pib.h Normal file
View File

@ -0,0 +1,9 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*/
extern int pib_init(void);

0
board/mpc8641hpcn/sys_eeprom.c → board/freescale/common/sys_eeprom.c
View File

44
board/freescale/m5235evb/Makefile Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/freescale/m5235evb/config.mk Normal file
View File

@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
/*TEXT_BASE = 0xFFC00000*/
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

117
board/freescale/m5235evb/m5235evb.c Normal file
View File

@ -0,0 +1,117 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M5235 EVB\n");
return 0;
};
long int initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 dramsize, i, dramclk;
/*
* When booting from external Flash, the port-size is less than
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
gpio->par_ad =
GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
GPIO_PAR_AD_DATAL;
/* Initialize PAR to enable SDRAM signals */
gpio->par_sdram =
GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
dramsize = CFG_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
/* Initialize DRAM Control Register: DCR */
sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
/* Initialize DACR0 */
sdram->dacr0 =
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
asm("nop");
}
/* Write to this block to initiate precharge */
*(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_RE;
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 0x2000; i++) {
asm("nop");
}
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
/* Write to the SDRAM Mode Register */
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

307
board/freescale/m5235evb/mii.c Normal file
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@ -0,0 +1,307 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_KS8721BL "KS8721BL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
strcpy(info->phy_name,
STR_ID_KS8721BL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
printf(STR_ID_KS8721BL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

145
board/freescale/m5235evb/u-boot.16 Normal file
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@ -0,0 +1,145 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
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.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu_init.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

153
board/freescale/m5235evb/u-boot.32 Normal file
View File

@ -0,0 +1,153 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.rodata : { *(.rel.rodata) }
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.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu.o (.text)
cpu/mcf523x/cpu_init.o (.text)
cpu/mcf523x/interrupts.o (.text)
cpu/mcf523x/speed.o (.text)
lib_m68k/libm68k.a (.text)
common/dlmalloc.o (.text)
common/cmd_bootm.o (.text)
common/cmd_flash.o (.text)
common/cmd_elf.o (.text)
common/cmd_mem.o (.text)
common/console.o (.text)
common/main.o (.text)
lib_generic/libgeneric.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

145
board/freescale/m5235evb/u-boot.lds Normal file
View File

@ -0,0 +1,145 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu_init.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

44
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@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/m5249evb/config.mk Normal file
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@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xffe00000

113
board/freescale/m5249evb/m5249evb.c Normal file
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@ -0,0 +1,113 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <asm/immap.h>
/* Prototypes */
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int checkboard (void) {
ulong val;
uchar val8;
puts ("Board: ");
puts("Freescale M5249EVB");
val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
printf(" (Switch=%1X)\n", val8);
/*
* Set LED on
*/
val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
};
long int initdram (int board_type) {
unsigned long junk = 0xa5a59696;
/*
* Note:
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
#ifdef CFG_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
#elif CFG_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
*/
mbar_writeShort(MCFSIM_DCR, 0x8202);
#else
/*
* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
*/
mbar_writeShort(MCFSIM_DCR, 0x8222);
#endif
/*
* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
* PM=1 (continuous page mode)
*/
/* RE=0 (keep auto-refresh disabled while setting up registers) */
mbar_writeLong(MCFSIM_DACR0, 0x00003324);
/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
/** Precharge sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
udelay(0x10); /* Allow several Precharge cycles */
/** Refresh Sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
udelay(0x7d0); /* Allow gobs of refresh cycles */
/** Mode Register initialization **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
return CFG_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
return (0);
}

146
board/freescale/m5249evb/u-boot.lds Normal file
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
lib_m68k/traps.o (.text)
cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

44
board/freescale/m5253evbe/Makefile Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/m5253evbe/config.mk Normal file
View File

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xffe00000

132
board/freescale/m5253evbe/m5253evbe.c Normal file
View File

@ -0,0 +1,132 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
int checkboard(void)
{
puts("Board: ");
puts("Freescale MCF5253 EVBE\n");
return 0;
};
long int initdram(int board_type)
{
int i;
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, dramsize;
RC = (CFG_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
mbar_writeLong(MCFSIM_DACR0, 0x00003224);
/* Initialize DMR0 */
dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
/* Write to this block to initiate precharge */
*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
/* Set RE bit in DACR */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x8000);
/* Wait for at least 8 auto refresh cycles to occur */
udelay(500);
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x0040);
*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
}
return CFG_SDRAM_SIZE * 1024 * 1024;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#ifdef CONFIG_CMD_IDE
#include <ata.h>
int ide_preinit(void)
{
return (0);
}
void ide_set_reset(int idereset)
{
volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
};
if (idereset) {
ata->cr = 0; /* control reset */
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / (CFG_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
ata->t2w = CALC_TIMING(piotms[2][1]);
ata->t2r = CALC_TIMING(piotms[2][1]);
ata->ta = CALC_TIMING(piotms[2][8]);
ata->trd = CALC_TIMING(piotms[2][7]);
ata->t4 = CALC_TIMING(piotms[2][3]);
ata->t9 = CALC_TIMING(piotms[2][6]);
ata->cr = 0x40; /* IORDY enable */
udelay(2000);
ata->cr |= 0x01; /* IORDY enable */
}
}
#endif /* CONFIG_CMD_IDE */

144
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@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
lib_m68k/traps.o (.text)
cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

44
board/freescale/m5329evb/Makefile Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/m5329evb/config.mk Normal file
View File

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0

88
board/freescale/m5329evb/m5329evb.c Normal file
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@ -0,0 +1,88 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale FireEngine 5329 EVB\n");
return 0;
};
long int initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CFG_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
sdram->cs0 = (CFG_SDRAM_BASE | i);
sdram->cfg1 = CFG_SDRAM_CFG1;
sdram->cfg2 = CFG_SDRAM_CFG2;
/* Issue PALL */
sdram->ctrl = CFG_SDRAM_CTRL | 2;
/* Issue LEMR */
sdram->mode = CFG_SDRAM_EMOD;
sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
sdram->ctrl = (CFG_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
sdram->ctrl = CFG_SDRAM_CTRL | 4;
sdram->ctrl = CFG_SDRAM_CTRL | 4;
sdram->mode = CFG_SDRAM_MODE;
sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

306
board/freescale/m5329evb/mii.c Normal file
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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
} else {
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
strcpy(info->phy_name,
STR_ID_DP83848VV);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
printf(STR_ID_DP83848VV);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

114
board/freescale/m5329evb/nand.c Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
#define CLR_CLE ~SET_CLE
#define SET_ALE 0x08
#define CLR_ALE ~SET_ALE
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
{
struct nand_chip *this = mtdinfo->priv;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
switch (cmd) {
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
case NAND_CTL_SETCLE:
nand_baseaddr |= SET_CLE;
break;
case NAND_CTL_CLRCLE:
nand_baseaddr &= CLR_CLE;
break;
case NAND_CTL_SETALE:
nand_baseaddr |= SET_ALE;
break;
case NAND_CTL_CLRALE:
nand_baseaddr |= CLR_ALE;
break;
case NAND_CTL_SETWP:
fbcs->csmr2 |= CSMR_WP;
break;
case NAND_CTL_CLRWP:
fbcs->csmr2 &= ~CSMR_WP;
break;
}
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
}
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
*((volatile u8 *)(this->IO_ADDR_W)) = byte;
}
static u8 nand_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
return (u8) (*((volatile u8 *)this->IO_ADDR_R));
}
static int nand_dev_ready(struct mtd_info *mtdinfo)
{
return 1;
}
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
/* set up pin configuration */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
gpio->pclrr_timer = 0;
gpio->podr_timer = 0;
nand->chip_delay = 50;
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = nand_hwcontrol;
nand->read_byte = nand_read_byte;
nand->write_byte = nand_write_byte;
nand->dev_ready = nand_dev_ready;
return 0;
}
#endif

144
board/freescale/m5329evb/u-boot.lds Normal file
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@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf532x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

44
board/freescale/m54455evb/Makefile Normal file
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@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/m54455evb/config.mk Normal file
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@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0

974
board/freescale/m54455evb/flash.c Normal file
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@ -0,0 +1,974 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
#ifndef CFG_FLASH_CFI
typedef unsigned char FLASH_PORT_WIDTH;
typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
/* Intel-compatible flash commands */
#define INTEL_PROGRAM 0x00100010
#define INTEL_ERASE 0x00200020
#define INTEL_WRSETUP 0x00400040
#define INTEL_CLEAR 0x00500050
#define INTEL_LOCKBIT 0x00600060
#define INTEL_PROTECT 0x00010001
#define INTEL_STATUS 0x00700070
#define INTEL_READID 0x00900090
#define INTEL_CFIQRY 0x00980098
#define INTEL_SUSERASE 0x00B000B0
#define INTEL_PROTPROG 0x00C000C0
#define INTEL_CONFIRM 0x00D000D0
#define INTEL_WRBLK 0x00e800e8
#define INTEL_RESET 0x00FF00FF
/* Intel-compatible flash status bits */
#define INTEL_FINISHED 0x00800080
#define INTEL_OK 0x00800080
#define INTEL_ERASESUS 0x00600060
#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
/* 28F160C3B CFI Data offset - This could vary */
#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
#define INTEL_CFI_PART 0x01 /* Product ID */
#define INTEL_CFI_LOCK 0x02 /* */
#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
#define INTEL_CFI_CAP 0x28
#define INTEL_CFI_WRBUF 0x2A
#define INTEL_CFI_BANK 0x2C /* Number of Bank */
#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
#define INTEL_CFI_SZ1B 0x30
#define INTEL_CFI_BLK2A 0x31
#define INTEL_CFI_BLK2B 0x32
#define INTEL_CFI_SZ2A 0x33
#define INTEL_CFI_SZ2B 0x34
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x0aaa
#define WR_BLOCK 0x20
/* not in the flash.h yet */
#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
* Functions
*/
ulong flash_get_size(FPWV * addr, flash_info_t * info);
int flash_get_offsets(ulong base, flash_info_t * info);
int flash_cmd_rd(volatile u16 * addr, int index);
int write_data(flash_info_t * info, ulong dest, FPW data);
int write_data_block(flash_info_t * info, ulong src, ulong dest);
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
void inline spin_wheel(void);
void flash_sync_real_protect(flash_info_t * info);
uchar intel_sector_protected(flash_info_t * info, ushort sector);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
ulong flash_init(void)
{
int i;
ulong size = 0;
ulong fbase = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
memset(&flash_info[i], 0, sizeof(flash_info_t));
switch (i) {
case 0:
fbase = (ulong) CFG_FLASH0_BASE;
break;
case 1:
fbase = (ulong) CFG_FLASH1_BASE;
break;
}
flash_get_size((FPWV *) fbase, &flash_info[i]);
flash_get_offsets((ulong) fbase, &flash_info[i]);
fbase += flash_info[i].size;
size += flash_info[i].size;
/* get the h/w and s/w protection status in sync */
flash_sync_real_protect(&flash_info[i]);
}
/* Protect monitor and environment sectors */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
return size;
}
int flash_get_offsets(ulong base, flash_info_t * info)
{
int i, j, k;
int sectors, bs, banks;
ulong start;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
int sect[] = CFG_ATMEL_SECT;
int sectsz[] = CFG_ATMEL_SECTSZ;
info->start[0] = base;
for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
for (j = 0; j < sect[i]; j++, k++) {
info->start[k + 1] = info->start[k] + sectsz[i];
info->protect[k] = 0;
}
}
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
volatile u16 *addr16 = (volatile u16 *)base;
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
*addr16 = (FPW) INTEL_READID;
banks = addr16[INTEL_CFI_BANK] & 0xff;
sectors = 0;
info->start[0] = base;
for (k = 0, i = 0; i < banks; i++) {
/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
*/
bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
0x100);
sectors =
(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
for (j = 0; j < sectors; j++, k++) {
info->start[k + 1] = info->start[k] + bs;
}
}
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
}
return ERR_OK;
}
void flash_print_info(flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf("INTEL ");
break;
case FLASH_MAN_ATM:
printf("ATMEL ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AT040:
printf("AT49BV040A\n");
break;
case FLASH_28F128J3A:
printf("Intel 28F128J3A\n");
break;
default:
printf("Unknown Chip Type\n");
return;
}
if (info->size > 0x100000) {
int remainder;
printf(" Size: %ld", info->size >> 20);
remainder = (info->size % 0x100000);
if (remainder) {
remainder >>= 10;
remainder = (int)((float)
(((float)remainder / (float)1024) *
10000));
printf(".%d ", remainder);
}
printf("MB in %d Sectors\n", info->sector_count);
} else
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size(FPWV * addr, flash_info_t * info)
{
volatile u16 *addr16 = (volatile u16 *)addr;
int intel = 0, banks = 0;
u16 value;
int i;
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
switch (addr[0] & 0xff) {
case (u8) ATM_MANUFACT:
info->flash_id = FLASH_MAN_ATM;
value = addr[1];
break;
case (u8) INTEL_MANUFACT:
/* Terminate Atmel ID read */
addr[0] = (FPWV) 0x00F000F0;
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
*addr16 = (FPW) INTEL_READID;
info->flash_id = FLASH_MAN_INTEL;
value = (addr16[INTEL_CFI_MFG] << 8);
value |= addr16[INTEL_CFI_PART] & 0xff;
intel = 1;
break;
default:
printf("Unknown Flash\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
*addr = (FPW) 0x00F000F0;
*addr = (FPW) INTEL_RESET; /* restore read mode */
return (0); /* no or unknown flash */
}
switch (value) {
case (u8) ATM_ID_LV040:
info->flash_id += FLASH_AT040;
break;
case (u16) INTEL_ID_28F128J3:
info->flash_id += FLASH_28F128J3A;
break;
case (u16) INTEL_ID_28F64P30T:
info->flash_id += FLASH_28F64P30T;
break;
case (u16) INTEL_ID_28F64P30B:
info->flash_id += FLASH_28F64P30B;
break;
case (u16) INTEL_ID_28F128P30T:
info->flash_id += FLASH_28F128P30T;
break;
case (u16) INTEL_ID_28F128P30B:
info->flash_id += FLASH_28F128P30B;
break;
case (u16) INTEL_ID_28F256P30T:
info->flash_id += FLASH_28F256P30T;
break;
case (u16) INTEL_ID_28F256P30B:
info->flash_id += FLASH_28F256P30B;
break;
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (intel) {
/* Intel spec. under CFI section */
u32 sz;
int sectors, bs;
banks = addr16[INTEL_CFI_BANK] & 0xff;
sectors = sz = 0;
for (i = 0; i < banks; i++) {
/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
*/
bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
0x100);
sectors +=
(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
sz += (bs * sectors);
}
info->sector_count = sectors;
info->size = sz;
*addr = (FPW) INTEL_RESET; /* restore read mode */
} else {
int sect[] = CFG_ATMEL_SECT;
int sectsz[] = CFG_ATMEL_SECTSZ;
info->sector_count = 0;
info->size = 0;
for (i = 0; i < CFG_ATMEL_REGION; i++) {
info->sector_count += sect[i];
info->size += sect[i] * sectsz[i];
}
/* reset ID mode */
addr[0] = (FPWV) 0x00F000F0;
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
printf("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
}
return (info->size);
}
int flash_cmd_rd(volatile u16 * addr, int index)
{
return (int)addr[index];
}
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
* status stored in hardware.
*/
void flash_sync_real_protect(flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
for (i = 0; i < info->sector_count; ++i) {
info->protect[i] = intel_sector_protected(info, i);
}
break;
default:
/* no h/w protect support */
break;
}
}
/*
* checks if "sector" in bank "info" is protected. Should work on intel
* strata flash chips 28FxxxJ3x in 8-bit mode.
* Returns 1 if sector is protected (or timed-out while trying to read
* protection status), 0 if it is not.
*/
uchar intel_sector_protected(flash_info_t * info, ushort sector)
{
FPWV *addr;
FPWV *lock_conf_addr;
ulong start;
unsigned char ret;
/*
* first, wait for the WSM to be finished. The rationale for
* waiting for the WSM to become idle for at most
* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* because of: (1) erase, (2) program or (3) lock bit
* configuration. So we just wait for the longest timeout of
* the (1)-(3), i.e. the erase timeout.
*/
/* wait at least 35ns (W12) before issuing Read Status Register */
/*udelay(1); */
addr = (FPWV *) info->start[sector];
*addr = (FPW) INTEL_STATUS;
start = get_timer(0);
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
*addr = (FPW) INTEL_RESET; /* restore read mode */
printf("WSM busy too long, can't get prot status\n");
return 1;
}
}
/* issue the Read Identifier Codes command */
*addr = (FPW) INTEL_READID;
/* Intel example code uses offset of 4 for 8-bit flash */
lock_conf_addr = (FPWV *) info->start[sector];
ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
/* put flash back in read mode */
*addr = (FPW) INTEL_RESET;
return ret;
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
int rcode = 0, intel = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
else
printf("- no sectors to erase\n");
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
type = (info->flash_id & FLASH_VENDMASK);
printf
("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
}
if (type == FLASH_MAN_INTEL)
intel = 1;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf("\n");
start = get_timer(0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
int min = 0;
printf(".");
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
if (intel) {
*addr = (FPW) INTEL_READID;
min = addr[INTEL_CFI_TERB] & 0xff;
min = 1 << min; /* ms */
min = (min / info->sector_count) * 1000;
/* start erase block */
*addr = (FPW) INTEL_CLEAR; /* clear status register */
*addr = (FPW) INTEL_ERASE; /* erase setup */
*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
while ((*addr & (FPW) INTEL_FINISHED) !=
(FPW) INTEL_FINISHED) {
if (get_timer(start) >
CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = (FPW) INTEL_SUSERASE; /* suspend erase */
*addr = (FPW) INTEL_RESET; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = (FPW) INTEL_RESET; /* resest to read mode */
} else {
FPWV *base; /* first address in bank */
FPWV *atmeladdr;
flag = disable_interrupts();
atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
*atmeladdr = (u8) 0x00300030; /* erase sector */
if (flag)
enable_interrupts();
while ((*atmeladdr & (u8) 0x00800080) !=
(u8) 0x00800080) {
if (get_timer(start) >
CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
rcode = 1;
break;
}
}
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
} /* Atmel or Intel */
}
}
printf(" done\n");
return rcode;
}
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
if (info->flash_id == FLASH_UNKNOWN)
return 4;
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_ATM:
{
u16 data = 0;
int bytes; /* number of bytes to program in current word */
int left; /* number of bytes left to program */
int i, res;
for (left = cnt, res = 0;
left > 0 && res == 0;
addr += sizeof(data), left -=
sizeof(data) - bytes) {
bytes = addr & (sizeof(data) - 1);
addr &= ~(sizeof(data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
for (i = 0; i < sizeof(data); i++) {
data <<= 8;
if (i < bytes || i - bytes >= left)
data += *((uchar *) addr + i);
else
data += *src++;
}
data = (data >> 8) | (data << 8);
res = write_word_atm(info, (FPWV *) addr, data);
}
return res;
} /* case FLASH_MAN_ATM */
case FLASH_MAN_INTEL:
{
ulong cp, wp;
u16 data;
int count, i, l, rc, port_width;
/* get lower word aligned address */
wp = addr;
port_width = sizeof(FPW);
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp)
data = (data << 8) | (*(uchar *) cp);
if ((rc = write_data(info, wp, data)) != 0)
return (rc);
wp += port_width;
}
if (cnt > WR_BLOCK) {
/*
* handle word aligned part
*/
count = 0;
while (cnt >= WR_BLOCK) {
if ((rc =
write_data_block(info,
(ulong) src,
wp)) != 0)
return (rc);
wp += WR_BLOCK;
src += WR_BLOCK;
cnt -= WR_BLOCK;
if (count++ > 0x800) {
spin_wheel();
count = 0;
}
}
}
/* handle word aligned part */
if (cnt < WR_BLOCK) {
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i)
data = (data << 8) | *src++;
if ((rc =
write_data(info,
(ulong) ((FPWV *) wp),
(FPW) (data))) != 0)
return (rc);
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel();
count = 0;
}
}
}
if (cnt == 0)
return ERR_OK;
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0;
++i, ++cp) {
data = (data << 8) | (*src++);
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return write_data(info, (ulong) ((FPWV *) wp),
(FPW) data);
} /* case FLASH_MAN_INTEL */
} /* switch */
return ERR_OK;
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_data_block(flash_info_t * info, ulong src, ulong dest)
{
FPWV *srcaddr = (FPWV *) src;
FPWV *dstaddr = (FPWV *) dest;
ulong start;
int flag, i;
/* Check if Flash is (sufficiently) erased */
for (i = 0; i < WR_BLOCK; i++)
if ((*dstaddr++ & 0xff) != 0xff) {
printf("not erased at %08lx (%lx)\n",
(ulong) dstaddr, *dstaddr);
return (2);
}
dstaddr = (FPWV *) dest;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
if (flag)
enable_interrupts();
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
return (1);
}
}
*dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
for (i = 0; i < WR_BLOCK; i++)
*dstaddr++ = *srcaddr++;
dstaddr -= 1;
*dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
return (1);
}
}
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
return (0);
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_data(flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf("not erased at %08lx (%lx)\n", (ulong) addr,
(ulong) * addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = (int)disable_interrupts();
*addr = (FPW) INTEL_CLEAR;
*addr = (FPW) INTEL_RESET;
*addr = (FPW) INTEL_WRSETUP; /* write setup */
*addr = data;
if (flag)
enable_interrupts();
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW) INTEL_SUSERASE; /* suspend mode */
*addr = (FPW) INTEL_CLEAR; /* clear status */
*addr = (FPW) INTEL_RESET; /* reset */
return (1);
}
}
*addr = (FPW) INTEL_CLEAR; /* clear status */
*addr = (FPW) INTEL_RESET; /* restore read mode */
return (0);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for ATMEL FLASH
* A word is 16 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
{
ulong start;
int flag, i;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*((volatile u16 *)dest) & data) != data) {
return (2);
}
base = (FPWV *) (CFG_ATMEL_BASE);
for (i = 0; i < sizeof(u16); i++) {
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer(0);
/* data polling for D7 */
while (res == 0
&& (*dest & (u8) 0x00800080) !=
(data & (u8) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dest = (u8) 0x00F000F0; /* reset bank */
res = 1;
}
}
*dest++ = (u8) 0x00F000F0; /* reset bank */
data >>= 8;
}
return (res);
}
void inline spin_wheel(void)
{
static int p = 0;
static char w[] = "\\/-";
printf("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}
#ifdef CFG_FLASH_PROTECTION
/*-----------------------------------------------------------------------
*/
int flash_real_protect(flash_info_t * info, long sector, int prot)
{
int rcode = 0; /* assume success */
FPWV *addr; /* address of sector */
FPW value;
addr = (FPWV *) (info->start[sector]);
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
*addr = (FPW) INTEL_RESET; /* make sure in read mode */
*addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
if (prot)
*addr = (FPW) INTEL_PROTECT; /* lock sector */
else
*addr = (FPW) INTEL_CONFIRM; /* unlock sector */
/* now see if it really is locked/unlocked as requested */
*addr = (FPW) INTEL_READID;
/* read sector protection at sector address, (A7 .. A0) = 0x02.
* D0 = 1 for each device if protected.
* If at least one device is protected the sector is marked
* protected, but return failure. Mixed protected and
* unprotected devices within a sector should never happen.
*/
value = addr[2] & (FPW) INTEL_PROTECT;
if (value == 0)
info->protect[sector] = 0;
else if (value == (FPW) INTEL_PROTECT)
info->protect[sector] = 1;
else {
/* error, mixed protected and unprotected */
rcode = 1;
info->protect[sector] = 1;
}
if (info->protect[sector] != prot)
rcode = 1; /* failed to protect/unprotect as requested */
/* reload all protection bits from hardware for now */
flash_sync_real_protect(info);
break;
default:
/* no hardware protect that we support */
info->protect[sector] = prot;
break;
}
return rcode;
}
#endif
#endif

164
board/freescale/m54455evb/m54455evb.c Normal file
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@ -0,0 +1,164 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M54455 EVB\n");
return 0;
};
long int initdram(int board_type)
{
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 dramsize, i;
dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
gpio->mscr_sdram = 0xAA;
sdram->sdcs0 = (CFG_SDRAM_BASE | i);
sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
sdram->sdcfg1 = CFG_SDRAM_CFG1;
sdram->sdcfg2 = CFG_SDRAM_CFG2;
/* Issue PALL */
sdram->sdcr = CFG_SDRAM_CTRL | 2;
/* Issue LEMR */
sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
sdram->sdmr = CFG_SDRAM_MODE | 0x300;
udelay(500);
/* Issue PALL */
sdram->sdcr = CFG_SDRAM_CTRL | 2;
/* Perform two refresh cycles */
sdram->sdcr = CFG_SDRAM_CTRL | 4;
sdram->sdcr = CFG_SDRAM_CTRL | 4;
sdram->sdmr = CFG_SDRAM_MODE | 0x200;
sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
return (dramsize << 1);
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#if defined(CONFIG_CMD_IDE)
#include <ata.h>
int ide_preinit(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
gpio->par_feci2c |=
(gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
gpio->par_ata |=
(GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
| GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
GPIO_PAR_ATA_IORDY_IORDY);
gpio->par_pci |=
(GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
return (0);
}
void ide_set_reset(int idereset)
{
volatile atac_t *ata = (atac_t *) MMAP_ATA;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = {
{70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
{25, 70, 20, 10, 20, 5, 10, 0, 35}
}; /* PIO 4 */
if (idereset) {
ata->cr = 0; /* control reset */
udelay(10000);
} else {
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / gd->bus_clk; /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
ata->t2w = CALC_TIMING(piotms[2][1]);
ata->t2r = CALC_TIMING(piotms[2][1]);
ata->ta = CALC_TIMING(piotms[2][8]);
ata->trd = CALC_TIMING(piotms[2][7]);
ata->t4 = CALC_TIMING(piotms[2][3]);
ata->t9 = CALC_TIMING(piotms[2][6]);
ata->cr = 0x40; /* IORDY enable */
udelay(200000);
ata->cr |= 0x01; /* IORDY enable */
}
}
#endif
#if defined(CONFIG_PCI)
/*
* Initialize PCI devices, report devices found.
*/
static struct pci_controller hose;
extern void pci_mcf5445x_init(struct pci_controller *hose);
void pci_init_board(void)
{
pci_mcf5445x_init(&hose);
}
#endif /* CONFIG_PCI */

320
board/freescale/m54455evb/mii.c Normal file
View File

@ -0,0 +1,320 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CFG_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CFG_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
struct eth_device *dev;
int i, miispd;
u16 rst = 0;
dev = eth_get_dev();
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
for (i = 0; i < FEC_RESET_DELAY; ++i) {
udelay(500);
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
if ((rst & PHY_BMCR_RESET) == 0)
break;
}
if (i == FEC_RESET_DELAY)
printf("Mii reset timeout %d\n", i);
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
strcpy(info->phy_name,
STR_ID_DP83848VV);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
printf(STR_ID_DP83848VV);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

144
board/freescale/m54455evb/u-boot.lds Normal file
View File

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

0
board/mpc8313erdb/Makefile → board/freescale/mpc8313erdb/Makefile
View File

0
board/mpc8313erdb/config.mk → board/freescale/mpc8313erdb/config.mk
View File

19
board/mpc8313erdb/mpc8313erdb.c → board/freescale/mpc8313erdb/mpc8313erdb.c
View File

@ -23,7 +23,11 @@
*/
#include <common.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <pci.h>
#include <mpc83xx.h>
@ -96,21 +100,22 @@ void pci_init_board(void)
mpc83xx_pci_init(1, reg, warmboot);
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p) {
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif

3
board/mpc8313erdb/sdram.c → board/freescale/mpc8313erdb/sdram.c
View File

@ -112,8 +112,6 @@ long int initdram(int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
puts("Initializing\n");
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
@ -127,7 +125,6 @@ long int initdram(int board_type)
resume_from_sleep();
#endif
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return msize;
}

35
board/freescale/mpc8323erdb/mpc8323erdb.c
View File

@ -17,7 +17,6 @@
#include <miiphy.h>
#include <command.h>
#include <libfdt.h>
#include <libfdt_env.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
@ -92,8 +91,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
puts("\n DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@ -185,33 +182,21 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
/*
* Prototypes of functions that we use.
*/
void ft_cpu_setup(void *blob, bd_t *bd);
#ifdef CONFIG_PCI
void ft_pci_setup(void *blob, bd_t *bd);
#endif
void
ft_board_setup(void *blob, bd_t *bd)
void ft_board_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int tmp[2];
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
nodeoffset = fdt_find_node_by_path(blob, "/memory");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(bd->bi_memstart);
tmp[1] = cpu_to_be32(bd->bi_memsize);
fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */
#endif

0
board/mpc832xemds/Makefile → board/freescale/mpc832xemds/Makefile
View File

0
board/mpc832xemds/config.mk → board/freescale/mpc832xemds/config.mk
View File

31
board/mpc832xemds/mpc832xemds.c → board/freescale/mpc832xemds/mpc832xemds.c
View File

@ -29,6 +29,11 @@
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
@ -86,6 +91,14 @@ int board_early_init_f(void)
return 0;
}
int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
pib_init();
#endif
return 0;
}
int fixed_sdram(void);
long int initdram(int board_type)
@ -101,8 +114,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
puts("\n DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@ -155,22 +166,22 @@ int checkboard(void)
return 0;
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif

64
board/mpc832xemds/pci.c → board/freescale/mpc832xemds/pci.c
View File

@ -20,6 +20,8 @@
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <asm/fsl_i2c.h>
@ -129,7 +131,6 @@ void pci_init_board(void)
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
u8 val8, orig_i2c_bus;
u16 reg16;
u32 val32;
u32 dev;
@ -197,43 +198,6 @@ void pci_init_board(void)
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
PIWAR_IWS_2G;
/*
* Assign PIB PMC slot to desired PCI bus
*/
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
/*
* Release PCI RST Output signal
*/
@ -290,8 +254,6 @@ void pci_init_board(void)
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
printf("PCI 32bit bus on PMC2 & PMC3\n");
/*
* Hose scan.
*/
@ -299,7 +261,27 @@ void pci_init_board(void)
}
#endif /* CONFIG_PCISLAVE */
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{

0
board/mpc8349emds/Makefile → board/freescale/mpc8349emds/Makefile
View File

0
board/mpc8349emds/config.mk → board/freescale/mpc8349emds/config.mk
View File

26
board/mpc8349emds/mpc8349emds.c → board/freescale/mpc8349emds/mpc8349emds.c
View File

@ -34,6 +34,8 @@
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
int fixed_sdram(void);
@ -68,8 +70,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
puts("Initializing\n");
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
@ -88,7 +88,7 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@ -189,9 +189,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
@ -253,26 +250,25 @@ void sdram_init(void)
#else
void sdram_init(void)
{
puts(" SDRAM on Local Bus is NOT available!\n");
}
#endif
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif

41
board/mpc8349emds/pci.c → board/freescale/mpc8349emds/pci.c
View File

@ -25,6 +25,12 @@
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -382,7 +388,40 @@ pci_init_board(void)
}
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
#ifdef CONFIG_MPC83XX_PCI2
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
#endif
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{

0
board/mpc8349itx/Makefile → board/freescale/mpc8349itx/Makefile
View File

0
board/mpc8349itx/config.mk → board/freescale/mpc8349itx/config.mk
View File

21
board/mpc8349itx/mpc8349itx.c → board/freescale/mpc8349itx/mpc8349itx.c
View File

@ -39,6 +39,8 @@
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#ifndef CONFIG_SPD_EEPROM
@ -74,7 +76,7 @@ int fixed_sdram(void)
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
@ -160,7 +162,6 @@ long int initdram(int board_type)
ddr_enable_ecc(msize * 1048576);
#endif
puts(" DDR RAM: ");
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
@ -385,22 +386,22 @@ int misc_init_r(void)
return rc;
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif

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