Add support for canmb board

Update for esd apc405

CHANGELOG

@@ -2,6 +2,254 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Add support for canmb board
+
+* Patch by Stefan Roese, 13 Apr 2005:
+  Update for esd apc405
+
+* Fixes for TQM8560 board:
+  - fix clock rates
+  - remove debug messages
+  - fix flash sector protection
+
+* Patch by Steven Scholz, 07 Apr 2005:
+  Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
+
+* Patches by Steven Scholz, 07 Apr 2005:
+  Fix compiler warning in altera.c
+  Fix warning in cpu/arm920t/at91rm9200/i2c.c
+
+* Patch by Ladislav Michl, 06 Apr 2005:
+  Fix voiceblue configuration.
+
+* Patch by Stefan Roese, 06 Apr 2005:
+  Updates for OCOTEA board:
+  - Changed U-Boot size from 512kByte to 256kByte
+  - Fixed flash driver to support boot from soldered user flash
+  - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+  - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+    Problem found by Andrew Wozniak.
+
+* Patch by Steven Scholz, 06 Apr 2005:
+  - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+  - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
+* Patches by Robert Whaley, 29 Nov 2004:
+  - update the pxa-regs.h file for PXA27x chips
+  - add PXA27x based ADSVIX board
+  - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+  Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+  Fix logic of "test -z" and "test -n" commands
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Fix netboot_common() prototypes.
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+  subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+  (now in interupts.c)
+
+* Add support for MPC8220 based "sorcery" board.
+
+* Add support for TQM8560 board.
+
+* Add FEC support for TQM8540 board.
+  Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
+
+* Patch by Martin Krause, 04 Apr 2005:
+  Update default configuration for CMC_PU2 board.
+
+* Patch by Steven Scholz, 04 Apr 2005:
+  - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
+  - introduce two new configuration options instead:
+    CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
+
+* Patch by Steven Scholz, 04 Apr 2005:
+  Make sure that MDIO clock does not exceed 2.5 MHz on AT91
+
+* Fix timer code for ARM systems: make sure that udelay() does not
+  reset timers so it's save to use udelay() in timeout code.
+
+* Patch by Mathias Küster, 23 Nov 2004:
+  add udelay support for the mcf5282 cpu
+
+* Patch by Tolunay Orkun, 16 November 2004:
+  fix incorrect onboard Xilinx CPLD base address
+
+* Patch by Jerry Van Baren, 08 Nov 2004:
+  - Add low-boot option for MPC8260ADS board (if lowboot is selected,
+    the jumper for the HRCW source should select flash. If lowboot is
+    not selected, the jumper for the HRCW source should select the
+    BCSR.
+  - change default load base address to 0x00400000
+
+* Patch by Yuli Barcohen, 08 Nov 2004:
+  Add support for Analogue & Micro Rattler boards.
+  Tested on Rattler8248.
+
+* Patch by Andre Renaud, 08 Nov 2004:
+  Fix watchdog support in common/lcd.c
+
+* Patch by Marc Leeman, 05 Nov 2003:
+  Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
+  bug only affects the XPC8245 processors
+
+* Patches by Josef Wagner, 29 Oct 2004:
+  - Add support for MicroSys CPU87 board
+  - Add support for MicroSys PM854 board
+
+* Patch by Jian Zhang, 02 Nov 2004:
+  Add 16-bit NAND support
+
+* Patch by Scott McNutt, 01 Nov 2004:
+  Add missing NIOS/NIOS2 support for "iminfo" command
+
+* Patch by Detlev Zundel, 29 Oct 2004:
+  Add missing NIOS/NIOS2 support for "mkimage" tool.
+
+* Patch by David Adair, 27 Oct 2004:
+  Add missing 440GX SDRAM Controller reset
+
+* Patch by Steven Scholz, 25 Oct 2004:
+  Declare reset_cpu() in include/common.h instead locally
+
+* Patch by Yusdi Santoso, 22 Oct 2004:
+  - Add support for HIDDEN_DRAGON board
+  - fix endianess problem in driver/rtl1839.c
+
+* Patch by Allen Curtis, 21 Oct 2004:
+  support multiple serial ports
+
+* Patch by Richard Klingler, 03 Apr 2005:
+  Add call to eth_halt() in net/net.c when called functions fail
+  after eth_init() has been called.
+
+* Patch by Sam Song, 3 April 2005:
+  - Update README.Netconsole
+  - Update README
+
+* Prepare for SoC rework of ARM code:
+  - rename CONFIG_BOOTBINFUNC into  CONFIG_INIT_CRITICAL
+  - rename memsetup into lowlevel_init (function name and source files)
+  Patch by Steven Scholz, 03 Apr 2005:
+  - create SoC specific directories include/asm-arm/arch-imx and
+    include/asm-arm/arch-s3c24x0
+
+* Fix problems with SNTP support;
+  enable SNTP support in some boards.
+
+* Patches by Martin Krause, 01 Apr 2005:
+  - Fix flash erase timeout on CMC_PU2
+  - Add automatic HW detection for CMC_PU2 and CMC_BASIC
+
+* Patch by Steven Scholz, 13 March 2005:
+  fix cache enabling for AT91RM9200
+
+* Patch by Masami Komiya, 30 Mar 2005:
+  add SNTP support and expand time server and time offset fields of
+  DHCP support. See doc/README.SNTP
+
+* Patch by Steven Scholz, 13 Dec 2004:
+  Fix bug in at91rm920 ethernet driver
+
+* Patch by Steven Scholz, 13 Dec 2004:
+  Remove duplicated code by merging memsetup.S files for
+  at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
+
+* Patch by Detlev Zundel, 31 Mar 2005:
+  Cleanup duplicate definition of overwrite_console()
+
+* Update TQM5200 configuration;
+  prepare for Rev. 200 starter kit boards
+
+* Patch by Scott McNutt, 21 Oct 2004:
+  Add support for Nios-II EPCS Controller core.
+
+* Patch by Scott McNutt, 20 Oct 2004:
+  Nios-II cleanups:
+  - Add sysid command (Nios-II only).
+  - Locate default exception trampoline at proper offset.
+  - Implement I/O routines (readb, writeb, etc)
+  - Implement do_bootm_linux
+
+* Patches by Martin Krause, 22 Mar 2005:
+  - use TQM5200_auto as MAKEALL target for TQM5200 systems
+  - add support for SM501 graphics controller
+  - add support for graphic console on TQM5200
+  - add support for TQM5200 Rev 200
+  - cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Manfred Baral, 17 Mar 2005:
+  Fix typo
+
+* Fix RTC configuration for PPChameleon board
+
+* Cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Stefan Roese, 16 Mar 2005:
+  Update for esd auto_update and hh405 board
+
+* Adapt for U-Boot image size (new features enabled) on TQM5200
+
+* Update code for TQM8540 board (and 85xx in general):
+  - Change the name of the Ethernet driver: MOTO ENET -> ENET
+  - Reformat boot messages
+  - Enable redundant environment
+  - Replace the -O2 optimization flag with -mno-string
+
+* Patch by David Brownell, 10 Mar 2005:
+  Restore copyright statements in OHCI drivers.
+
+* Add support for TQM8540 board
+
+* Patch by Detlev Zundel, 14 Mar 2005:
+  NC650: changed NAND flash addressing to using UPMB
+
+* Patch by Stefan Roese, 14 Mar 2005:
+  Update for esd voh405 fpga image
+
+* INKA4x0: Allow initialization of LCD backlight dimming from
+  "brightness" environment variable.
+
+* Add port initialization for digital I/O on INKA4x0
+
+* Patch by Stefan Roese, 01 Mar 2005:
+  Update for esd boards dp405 and hub405
+
+* Fix get_partition_info() parameter error in all other calls
+  (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
+
+* Enable USB and IDE support for INKA4x0 board
+
+* Patch by Andrew Dyer, 28 Feb 2005:
+  fix ext2load passing an incorrect pointer to get_partition_info()
+  resulting in load failure for devices other than 0
+
+* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
+
+* Cleanup USB and partition defines
+
+* Add support for ext2 filesystems and image timestamps to TQM5200 board
+
+* Add reset code for Coral-P on INKA4x0 board
+
+* Patch by Martin Krause, 28 Jun 2004:
+  Update for TRAB board.
+
+* Fix some missing "volatile"s in MPC5xxx FEC driver
+
 * Fix cirrus voltage detection (for CPC45)
 
 * Fix byteorder problem in usbboot and scsiboot commands.

CREDITS

@@ -40,6 +40,7 @@ D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
 D: Support for Zephyr Engineering ZPC.1900 board.
 D: Support for Interphase iSPAN boards.
 D: Support for Analogue&Micro Adder boards.
+D: Support for Analogue&Micro Rattler boards.
 W: http://www.arabellasw.com
 
 N: Jerry van Baren
@@ -401,6 +402,10 @@ N: Christian Vejlbo
 E: christian.vejlbo@tellabs.com
 D: FADS860T ethernet support
 
+N: Robert Whaley
+E: rwhaley@applieddata.net
+D: Port to ARM PXA27x adsvix SBC
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board

MAINTAINERS

@@ -34,6 +34,7 @@ Yuli Barcohen <yuli@arabellasw.com>
 	Adder			MPC87x/MPC852T
 	ISPAN			MPC8260
 	MPC8260ADS		MPC826x/MPC827x/MPC8280
+	Rattler			MPC8248
 	ZPC1900			MPC8265
 
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
@@ -302,6 +303,10 @@ Dan Malek <dan@embeddededge.com>
 
 	STxGP3			MPC85xx
 
+Yusdi Santoso <yusdi_santoso@adaptec.com>
+
+	HIDDEN_DRAGON	MPC8241/MPC8245
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

MAKEALL

@@ -26,7 +26,7 @@ LIST_5xx="	\
 
 LIST_5xxx="	\
 	icecube_5100	icecube_5200	EVAL5200	PM520		\
-	Total5100	Total5200	Total5200_Rev2	TQM5200_AA	\
+	Total5100	Total5200	Total5200_Rev2	TQM5200_auto	\
 "
 
 #########################################################################
@@ -86,9 +86,10 @@ LIST_8220="	\
 
 LIST_824x="	\
 	A3000		BMW		CPC45		CU824		\
-	debris		eXalion		MOUSSE		MUSENKI		\
-	MVBLUE		OXC		PN62		Sandpoint8240	\
-	Sandpoint8245	SL8245		utx8245		sbc8240	\
+	debris		eXalion		HIDDEN_DRAGON	MOUSSE		\
+	MUSENKI		MVBLUE		OXC		PN62		\
+	Sandpoint8240	Sandpoint8245	SL8245		utx8245		\
+	sbc8240	\
 "
 
 #########################################################################
@@ -96,12 +97,13 @@ LIST_824x="	\
 #########################################################################
 
 LIST_8260="	\
-	atc		cogent_mpc8260	CPU86		ep8260		\
-	gw8260		hymod		IPHASE4539	ISPAN		\
-	MPC8260ADS	MPC8266ADS	MPC8272ADS	PM826		\
-	PM828		ppmc8260	RPXsuper	rsdproto	\
-	sacsng		sbc8260		SCM		TQM8260_AC	\
-	TQM8260_AD	TQM8260_AE	ZPC1900				\
+	atc		cogent_mpc8260	CPU86		CPU87		\
+	ep8260		gw8260		hymod		IPHASE4539	\
+	ISPAN		MPC8260ADS	MPC8266ADS	MPC8272ADS	\
+	PM826		PM828		ppmc8260	Rattler8248	\
+	RPXsuper	rsdproto	sacsng		sbc8260		\
+	SCM		TQM8260_AC	TQM8260_AD	TQM8260_AE	\
+	ZPC1900								\
 "
 
 #########################################################################
@@ -110,7 +112,8 @@ LIST_8260="	\
 
 LIST_85xx="	\
 	MPC8540ADS	MPC8541CDS	MPC8555CDS	MPC8560ADS	\
-	sbc8540		sbc8560		stxgp3				\
+	PM854		sbc8540		sbc8560		stxgp3		\
+	TQM8540								\
 "
 
 #########################################################################
@@ -154,7 +157,7 @@ LIST_ARM9="	\
 	lpd7a400	mx1ads		mx1fs2		omap1510inn	\
 	omap1610h2	omap1610inn	omap730p2	scb9328		\
 	smdk2400	smdk2410	trab		VCMA9		\
-	versatile							\
+	versatile	voiceblue					\
 "
 
 #########################################################################
@@ -167,9 +170,9 @@ LIST_ARM11="omap2420h4"
 #########################################################################
 
 LIST_pxa="	\
-	cerf250		cradle		csb226		innokom		\
-	lubbock		wepep250	xaeniax		xm250		\
-	xsengine							\
+	adsvix		cerf250		cradle		csb226		\
+	innokom		lubbock		wepep250	xaeniax		\
+	xm250		xsengine							\
 "
 
 LIST_ixp="ixdp425"

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -215,6 +215,9 @@ unconfig:
 ## MPC5xx Systems
 #########################################################################
 
+canmb_config:	unconfig
+	@./mkconfig -a canmb ppc mpc5xxx canmb
+
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
@@ -864,6 +867,9 @@ XPEDITE1K_config:	unconfig
 Alaska8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 alaska
 
+sorcery_config:		unconfig
+	@./mkconfig $(@:_config=) ppc mpc8220 sorcery
+
 Yukon8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 yukon
 
@@ -900,6 +906,9 @@ debris_config: unconfig
 eXalion_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x eXalion
 
+HIDDEN_DRAGON_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
+
 MOUSSE_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x mousse
 
@@ -956,6 +965,19 @@ CPU86_ROMBOOT_config: unconfig
 	fi; \
 	echo "export CONFIG_BOOT_ROM" >> config.mk;
 
+CPU87_config	\
+CPU87_ROMBOOT_config: unconfig
+	@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu87
+	@cd ./include ;				\
+	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
+		echo "... booting from 8-bit flash" ; \
+	else \
+		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
+		echo "... booting from 64-bit flash" ; \
+	fi; \
+	echo "export CONFIG_BOOT_ROM" >> config.mk;
+
 ep8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ep8260
 
@@ -976,13 +998,21 @@ ISPAN_REVB_config:	unconfig
 	@./mkconfig -a ISPAN ppc mpc8260 ispan
 
 MPC8260ADS_config	\
+MPC8260ADS_lowboot_config	\
 MPC8260ADS_33MHz_config	\
+MPC8260ADS_33MHz_lowboot_config	\
 MPC8260ADS_40MHz_config	\
+MPC8260ADS_40MHz_lowboot_config	\
 MPC8272ADS_config	\
+MPC8272ADS_lowboot_config	\
 PQ2FADS_config		\
+PQ2FADS_lowboot_config		\
 PQ2FADS-VR_config	\
+PQ2FADS-VR_lowboot_config	\
 PQ2FADS-ZU_config	\
+PQ2FADS-ZU_lowboot_config	\
 PQ2FADS-ZU_66MHz_config	\
+PQ2FADS-ZU_66MHz_lowboot_config	\
 	:		unconfig
 	$(if $(findstring PQ2FADS,$@), \
 	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \
@@ -991,6 +1021,10 @@ PQ2FADS-ZU_66MHz_config	\
 	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \
 	$(if $(findstring VR,$@), \
 	@echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h))
+	@[ -z "$(findstring lowboot_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF800000" >board/mpc8260ads/config.tmp ; \
+		  echo "... with lowboot configuration" ; \
+		}
 	@./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads
 
 MPC8266ADS_config:	unconfig
@@ -1050,6 +1084,12 @@ PM828_ROMBOOT_PCI_config:	unconfig
 ppmc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
 
+Rattler8248_config	\
+Rattler_config:		unconfig
+	$(if $(findstring 8248,$@), \
+	@echo "#define CONFIG_MPC8248" > include/config.h)
+	@./mkconfig -a Rattler ppc mpc8260 rattler
+
 RPXsuper_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 rpxsuper
 
@@ -1144,6 +1184,9 @@ MPC8541CDS_config:	unconfig
 MPC8555CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
 
+PM854_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx pm854
+
 sbc8540_config \
 sbc8540_33_config \
 sbc8540_66_config:	unconfig
@@ -1171,6 +1214,12 @@ sbc8560_66_config:      unconfig
 stxgp3_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
 
+TQM8540_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx tqm8540
+
+TQM8560_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx tqm8560
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -1239,6 +1288,12 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
 
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
+at91rm9200dk_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+
+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap
 
@@ -1336,6 +1391,19 @@ VCMA9_config	:	unconfig
 versatile_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs versatile
 
+voiceblue_smallflash_config	\
+voiceblue_config:	unconfig
+	@if [ "$(findstring _smallflash_,$@)" ] ; then \
+		echo "... boot from lower flash bank" ; \
+		echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
+	else \
+		echo "... boot from upper flash bank" ; \
+		>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
+	fi
+	@./mkconfig -a voiceblue arm arm925t voiceblue
+
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################
@@ -1359,20 +1427,13 @@ modnet50_config :	unconfig
 evb4510_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t evb4510
 
-#########################################################################
-## AT91RM9200 Systems
-#########################################################################
-
-at91rm9200dk_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-cmc_pu2_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
-
 #########################################################################
 ## XScale Systems
 #########################################################################
 
+adsvix_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa adsvix
+
 cerf250_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa cerf250
 

README

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2004
+# (C) Copyright 2000 - 2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -126,12 +126,12 @@ Directory Hierarchy:
   - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
   - arm720t	Files specific to ARM 720 CPUs
   - arm920t	Files specific to ARM 920 CPUs
+    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
     - imx	Files specific to Freescale MC9328 i.MX CPUs
     - s3c24x0	Files specific to Samsung S3C24X0 CPUs
   - arm925t	Files specific to ARM 925 CPUs
   - arm926ejs	Files specific to ARM 926 CPUs
   - arm1136	Files specific to ARM 1136 CPUs
-  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
@@ -627,6 +627,7 @@ The following options need to be configured:
 		CFG_CMD_SAVES	* save S record dump
 		CFG_CMD_SCSI	* SCSI Support
 		CFG_CMD_SDRAM	* print SDRAM configuration information
+				  (requires CFG_CMD_I2C)
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
@@ -2128,6 +2129,19 @@ Low Level (hardware related) configuration options:
 		This only takes effect if the memory commands are activated
 		globally (CFG_CMD_MEM).
 
+- CONFIG_SKIP_LOWLEVEL_INIT
+- CONFIG_SKIP_RELOCATE_UBOOT
+
+		[ARM only] If these variables are defined, then
+		certain low level initializations (like setting up
+		the memory controller) are omitted and/or U-Boot does
+		not relocate itself into RAM.
+		Normally these variables MUST NOT be defined. The
+		only exception is when U-Boot is loaded (to RAM) by
+		some other boot loader or by a debugger which
+		performs these intializations itself.
+
+
 Building the Software:
 ======================
 
@@ -3067,8 +3081,7 @@ Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
-meantime, send mail to bruno@exet-ag.de and/or wd@denx.de for
-details.
+meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
 
 
 Implementation Internals:

board/Marvell/common/ecctest.c

@@ -1,5 +1,3 @@
-indent: Standard input:49: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
-
 /*
  * (C) Copyright 2001
  *

board/adsvix/Makefile

@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= adsvix.o pcmcia.o
+SOBJS	:= lowlevel_init.o pxavoltage.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/adsvix/adsvix.c

@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of ADSVIX-Board */
+	gd->bd->bi_arch_number = 620;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}

board/adsvix/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0xa1700000

board/adsvix/lowlevel_init.S

@@ -0,0 +1,466 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc	p15,0,\reg,c2,c0,0
+   mov	\reg,\reg
+   sub	pc,pc,#4
+   .endm
+
+
+/*
+ *	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR3
+	ldr		r1,	=CFG_GPSR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR3
+	ldr		r1,	=CFG_GPCR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR3
+	ldr		r1,	=CFG_GPDR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_L
+	ldr		r1,	=CFG_GAFR3_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_U
+	ldr		r1,	=CFG_GAFR3_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller	    */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type			    */
+
+	/* MSC0: nCS(0,1)						    */
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
+						/* that data latches	    */
+	/* MSC1: nCS(2,3)						    */
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)						    */
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface				    */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register				    */
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing				    */
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing				    */
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
+	/* ---------------------------------------------------------------- */
+	ldr	r2,  =CFG_FLYCNFG_VAL
+	str	r2,  [r1, #FLYCNFG_OFFSET]
+	str	r2,	[r1, #FLYCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
+	/* this to power on defaults + DRI field.			    */
+
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+	ldr	r2,	=0xFFF
+	bic	r4,	r4, r2
+
+	ldr	r3,	=CFG_MDREFR_VAL
+	and	r3,	r3,  r2
+
+	orr	r4,	r4, r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+
+	orr	r4,  r4, #MDREFR_K0RUN
+	orr	r4,  r4, #MDREFR_K0DB4
+	orr	r4,  r4, #MDREFR_K0FREE
+	orr	r4,  r4, #MDREFR_K0DB2
+	orr	r4,  r4, #MDREFR_K1DB2
+	bic	r4,  r4, #MDREFR_K1FREE
+	bic	r4,  r4, #MDREFR_K2FREE
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4			    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits		    */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.						    */
+
+	ldr	r2,  =CFG_SXCNFG_VAL
+	str	r2,  [r1, #SXCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM					    */
+	/* ---------------------------------------------------------------- */
+
+	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*	    configure but not enable each SDRAM partition pair.	    */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
+	/*	    100..200 µsec.					    */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
+	/*	    attempting non-burst read or write accesses to disabled */
+	/*	    SDRAM, as commonly specified in the power up sequence   */
+	/*	    documented in SDRAM data sheets. The address(es) used   */
+	/*	    for this purpose must not be cacheable.		    */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted		    */
+	/*	    (MDCNFG:DEx set to 1).				    */
+
+	ldr	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3,	r3,	#MDCNFG_DE0
+	str	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS.					    */
+
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3,  [r1, #MDREFR_OFFSET]
+	orr	r3,  r3,  #MDREFR_APD
+	str	r3,  [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+setvoltage:
+
+	mov	r10,	lr
+	bl	initPXAvoltage	/* In case the board is rebooting with a    */
+	mov	lr,	r10	/* low voltage raise it up to a good one.   */
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0,	=RCSR
+	ldr	r1,	[r0]
+	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1,	[r0]
+	teq	r1,	#RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0,	=PSSR
+	mov	r1,	#PSSR_PH
+	str	r1,	[r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0,	=PSPR
+	ldr	r1,	[r0]
+	mov	pc,	r1
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller	    */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
+	str	r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation						    */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off on-chip peripheral clocks (except for memory)	    */
+	/* for re-configuration.					    */
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN
+	str	r2,  [r1]
+
+	/* ... and write the core clock config register			    */
+	ldr	r2,  =CFG_CCCR
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MEMC_BASE
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager		    */
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
+	/* has settled.							    */
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#else
+#error "RTC not defined"
+#endif
+
+	/* Interrupt init: Mask all interrupts				    */
+    ldr r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+	/* FIXME */
+
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init							    */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov	pc, lr

board/adsvix/pcmcia.c

@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void pcmcia_power_on(void)
+{
+#if 0
+	if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
+		GPCR(81) = GPIO_bit(81);
+		GPSR(82) = GPIO_bit(82);
+	}
+	else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
+		GPCR(81) = GPIO_bit(81);
+		GPCR(82) = GPIO_bit(82);
+	}
+#else
+#warning "Board will only supply 5V, wait for next HW spin for selectable power"
+	/* 5.0V */
+	GPCR(81) = GPIO_bit(81);
+	GPCR(82) = GPIO_bit(82);
+#endif
+
+	udelay(300000);
+
+	/* reset the card */
+	GPSR(52) = GPIO_bit(52);
+
+	/* enable PCMCIA */
+	GPCR(83) = GPIO_bit(83);
+
+	/* clear reset */
+	udelay(10);
+	GPCR(52) = GPIO_bit(52);
+
+	udelay(20000);
+}
+
+void pcmcia_power_off(void)
+{
+	/* 0V */
+	GPSR(81) = GPIO_bit(81);
+	GPSR(82) = GPIO_bit(82);
+	/* disable PCMCIA */
+	GPSR(83) = GPIO_bit(83);
+}

board/adsvix/pxavoltage.S

@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+#define LTC1663_ADDR    0x20
+
+#define LTC1663_SY	0x01	/* Sync ACK */
+#define LTC1663_SD	0x04	/* shutdown */
+#define LTC1663_BG	0x04	/* Internal Voltage Ref */
+
+#define VOLT_1_55         18    /* DAC value for 1.55V */
+
+		.global	initPXAvoltage
+
+@ Set the voltage to 1.55V early in the boot process so we can run
+@ at a high clock speed and boot quickly.  Note that this is necessary
+@ because the reset button does not reset the CPU voltage, so if the
+@ voltage was low (say 0.85V) then the CPU would crash without this
+@ routine
+
+@ This routine clobbers r0-r4
+
+initializei2c:
+
+		ldr	r2, =CKEN
+		ldr	r3, [r2]
+		orr	r3, r3, #CKEN15_PWRI2C
+		str	r3, [r2]
+
+		ldr	r2, =PCFR
+		ldr	r3, [r2]
+		orr	r3, r3, #PCFR_PI2C_EN
+		str	r3, [r2]
+
+		/* delay for about 250msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0000
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		ldr	r0, =PWRICR
+		ldr	r1, [r0]
+		bic	r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		ldr	r2, =PWRISR
+		ldr	r3, =0x7ff
+		str	r3, [r2]
+
+		bic	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		mov	r1, #(ICR_GCD | ICR_SCLE)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_IUE
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_FM
+		str	r1, [r0]
+
+		/* delay for about 1msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC00
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, lr
+
+sendbytei2c:
+		ldr	r3, =PWRIDBR
+		str	r0, [r3]
+		ldr	r3, =PWRICR
+		ldr	r0, [r3]
+		orr	r0, r0, r1
+		bic	r0, r0, r2
+		str	r0, [r3]
+		orr	r0, r0, #ICR_TB
+		str	r0, [r3]
+
+		mov	r2, #0x100000
+
+waitfortxemptyi2c:
+
+		ldr	r0, =PWRISR
+		ldr	r1, [r0]
+
+		/* take it from the top if we don't get empty after a while */
+		subs	r2, r2, #1
+		moveq	lr, r4
+		beq	initPXAvoltage
+
+		tst	r1, #ISR_ITE
+
+		beq	waitfortxemptyi2c
+
+		orr	r1, r1, #ISR_ITE
+		str	r1, [r0]
+
+		mov	pc, lr
+
+initPXAvoltage:
+
+		mov	r4, lr
+
+		bl	setleds
+
+		bl	initializei2c
+
+		bl	setleds
+
+		/* now send the real message to set the correct voltage */
+		ldr	r0, =LTC1663_ADDR
+		mov	r0, r0, LSL #1
+		mov	r1, #ICR_START
+		ldr	r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		mov	r0, #LTC1663_BG
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		and	r0, r0, #0xff
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		mov	r0, r0, ASR #8
+		and	r0, r0, #0xff
+		mov	r1, #ICR_STOP
+		mov	r2, #ICR_START
+		bl	sendbytei2c
+
+		bl	setleds
+
+		@ delay a little for the volatage to stablize
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, r4
+
+setleds:
+	mov		pc, lr
+
+	ldr		r5, =0x40e00058
+	ldr		r3, [r5]
+	bic		r3, r3, #0x3
+	str		r3, [r5]
+	ldr		r5, =0x40e0000c
+	ldr		r3, [r5]
+	orr		r3, r3, #0x00010000
+	str		r3, [r5]
+
+	@ inner loop
+	mov		r0, #0x2
+1:
+
+	ldr		r5, =0x40e00018
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+2:
+	subs		r3, r3, #1
+	bne		2b
+
+	ldr		r5, =0x40e00024
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+3:
+	subs		r3, r3, #1
+	bne		3b
+
+	subs		r0, r0, #1
+	bne		1b
+
+	mov		pc, lr

board/adsvix/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/alaska/Makefile

@@ -1,4 +1,4 @@
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o extserial.o serial.o
+OBJS	:= $(BOARD).o flash.o extserial.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/assabet/setup.S

@@ -80,8 +80,8 @@ BCR_DB1110:	.long	ASSABET_BCR_DB1110
 LEDS:		.long	NEPONSET_LEDS
 
 
-	.globl memsetup
-memsetup:
+	.globl lowlevel_init
+lowlevel_init:
 
 	/* Setting up the memory and stuff */
 

board/at91rm9200dk/Makefile

@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= at91rm9200dk.o at45.o dm9161.o flash.o
-SOBJS	:= memsetup.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/at91rm9200dk/memsetup.S

@@ -1,200 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifdef CONFIG_BOOTBINFUNC
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP 0xFFFFFF50
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER 0xFFFFFF54
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR 0xFFFFFF04
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR 0xFFFFFF08
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR 0xFFFFFF64
-#define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR 0xFFFFFF70
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR 0xFFFFFC2C
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR 0xFFFFFC30
-#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR 0xFFFFF804
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA 0xFFFFFF60
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR 0xFFFFFF94
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl lowlevelinit
-lowlevelinit:
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #80
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-1:
-	subs	r0, r0, #1
-	bhi	1b
-	ldr	r0, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #176
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word MC_PUIA
-	.word MC_PUIA_VAL
-	.word MC_PUP
-	.word MC_PUP_VAL
-	.word MC_PUER
-	.word MC_PUER_VAL
-	.word MC_ASR
-	.word MC_ASR_VAL
-	.word MC_AASR
-	.word MC_AASR_VAL
-	.word EBI_CFGR
-	.word EBI_CFGR_VAL
-	.word SMC2_CSR
-	.word SMC2_CSR_VAL
-	.word PLLAR
-	.word PLLAR_VAL
-	.word PLLBR
-	.word PLLBR_VAL
-	.word MCKR
-	.word MCKR_VAL
-	/* SMRDATA is 80 bytes long */
-	/* here there's a delay of 100 */
-SMRDATA1:
-	.word PIOC_ASR
-	.word PIOC_ASR_VAL
-	.word PIOC_BSR
-	.word PIOC_BSR_VAL
-	.word PIOC_PDR
-	.word PIOC_PDR_VAL
-	.word EBI_CSA
-	.word EBI_CSA_VAL
-	.word SDRC_CR
-	.word SDRC_CR_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL1
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL2
-	.word SDRAM1
-	.word SDRAM_VAL
-	.word SDRC_TR
-	.word SDRC_TR_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL3
-	.word SDRAM
-	.word SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_BOOTBINFUNC */

board/at91rm9200dk/u-boot.lds

@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}
 

board/canmb/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+#../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/canmb/canmb.c

@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+/*****************************************************************************
+ * initialize SDRAM/DDRAM controller.
+ * TBD: get data from I2C EEPROM
+ *****************************************************************************/
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+#if 0
+	ulong	t;
+	ulong	tap_del;
+#endif
+
+	#define	MODE_EN		0x80000000
+	#define	SOFT_PRE	2
+	#define	SOFT_REF	4
+
+	/* configure SDRAM start/end */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x8000000;
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+#ifdef CFG_DRAM_DDR
+	/* set extended mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
+#endif
+	/* set mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
+	/* set mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
+	/* write default TAP delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
+
+#endif /* CFG_RAMBOOT */
+
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20) +
+		((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
+
+	/* return total ram size */
+	return dramsize;
+}
+
+/*****************************************************************************
+ * print board identification
+ *****************************************************************************/
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}

board/canmb/config.mk

@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CANMB board
+#
+# allowed and functional TEXT_BASE values:
+#
+#   0xfe000000		low boot at 0x00000100 (default board setting)
+#	0x00100000		RAM load and test
+#
+
+TEXT_BASE = 0xFE000000
+#TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/canmb/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/cerf250/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= cerf250.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/cerf250/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -43,8 +43,8 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/* Set up GPIO pins first ----------------------------------------- */
 
@@ -403,9 +403,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc,	lr

board/cmc_pu2/Makefile

@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= cmc_pu2.o at45.o dm9161.o flash.o
-SOBJS	:= memsetup.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/cmc_pu2/cmc_pu2.c

@@ -6,6 +6,8 @@
  * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
  * (2004) garyj@denx.de
  *
+ * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -33,22 +35,67 @@
 /*
  * Miscelaneous platform dependent initialisations
  */
+#define CMC_BASIC	1
+#define CMC_PU2		2
+
+int hw_detect (void);
 
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	AT91PS_PIO piob = AT91C_BASE_PIOB;
+	AT91PS_PIO pioc = AT91C_BASE_PIOC;
 
 	/* Enable Ctrlc */
 	console_init_f ();
 
 	/* Correct IRDA resistor problem */
 	/* Set PA23_TXD in Output */
-	(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
+	/* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */
 
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
-	/* arch number of CMC_PU2-Board */
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	/*
+	 * configure PC0-PC3 as input without pull ups, so RS485 driver enable
+	 * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated.
+	 */
+	pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+	        	AT91C_PIO_PC2 | AT91C_PIO_PC3;
+
+	/*
+	 * On CMC-PU2 board configure PB3-PB6 to input without pull ups to
+	 * clear the duo LEDs (the external pull downs assure a proper
+	 * signal). On CMC-BASIC set PB3-PB6 to output and drive it
+	 * high, to configure current meassurement on AINx.
+	 */
+	if (hw_detect() & CMC_PU2) {
+		piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	else if (hw_detect() & CMC_BASIC) {
+		piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+		piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+
+	/*
+	 * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in
+	 * the linuxarm kernel, yet.
+	 */
 	/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
 	gd->bd->bi_arch_number = 251;
 	/* adress of boot parameters */
@@ -65,3 +112,30 @@ int dram_init (void)
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 	return 0;
 }
+
+int checkboard (void)
+{
+	if (hw_detect() & CMC_PU2)
+		puts ("Board: CMC-PU2 (Rittal GmbH)\n");
+	else if (hw_detect() & CMC_BASIC)
+		puts ("Board: CMC-BASIC (Rittal GmbH)\n");
+	else
+		puts ("Board: unknown\n");
+	return 0;
+}
+
+int hw_detect (void)
+{
+	AT91PS_PIO pio = AT91C_BASE_PIOB;
+
+	/* PIOB clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+
+	/* configure PB12 as input without pull up */
+	pio->PIO_ODR = AT91C_PIO_PB12;
+	pio->PIO_PPUDR = AT91C_PIO_PB12;
+	pio->PIO_PER = AT91C_PIO_PB12;
+
+	/* read board identification pin */
+	return ((pio->PIO_PDSR & AT91C_PIO_PB12) ? CMC_PU2 : CMC_BASIC);
+}

board/cmc_pu2/u-boot.lds

@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}
 

board/cpu87/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2003
+# (C) Copyright 2001-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,21 +23,17 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= lib$(CPU).a
+LIB	= lib$(BOARD).a
 
-START	= start.o
-OBJS	= serial.o interrupts.o cpu.o \
-	  at91rm9200_ether.o i2c.o
+OBJS	= $(BOARD).o flash.o
 
-all:	.depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
+$(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)
 
 #########################################################################
 
-.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
 
 sinclude .depend
 

board/cpu87/config.mk

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CPU87 board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFF800000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFF000000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)

board/cpu87/cpu87.c

@@ -0,0 +1,333 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu87.h"
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 32 * 1024 * 1024;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+			  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+				  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif

board/cpu87/cpu87.h

@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU87__
+#define __BOARD_CPU87__
+
+#include <config.h>
+
+#define REG8(x)			(*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT		0x01
+#define CPU86_BCR_FWRE		0x02
+
+#endif /* __BOARD_CPU87__ */

board/cpu87/flash.c

@@ -0,0 +1,624 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu87.h"
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write identify command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+	short i;
+	uchar vendor, devid;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x90;
+
+	udelay(1000);
+
+	vendor = addr[0];
+	devid = addr[1] & 0xff;
+
+	/* only support AMD */
+	if (vendor != 0x01) {
+		return 0;
+	}
+
+	vendor &= 0xf;
+	devid &= 0xff;
+
+	if (devid == AMD_ID_F040B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 8;
+		info->size         = info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F080B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 16;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F016D) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 32;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else {
+		printf ("## Unknown Flash Type: %02x\n", devid);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* sector base address */
+		info->start[i] = base + i * (info->size / info->sector_count);
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_char *)info->start[0];
+		addr[0] = 0xF0; /* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	unsigned long size_b1 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Disable flash protection */
+	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+
+	if (size_b0 > 0 || size_b1 > 0) {
+
+		printf("(");
+
+		if (size_b0 > 0) {
+			puts ("Bank#1 - ");
+			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+		}
+
+		if (size_b1 > 0) {
+			puts ("Bank#2 - ");
+			print_size (size_b1, ") ");
+		}
+	}
+	else {
+		printf ("## No FLASH found.\n");
+		return 0;
+	}
+	/* protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		 * but we shouldn't protect it.
+		 */
+
+		flash_protect  (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+		);
+	}
+#else
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		flash_protect (FLAG_PROTECT_SET,
+				CFG_ENV_ADDR,
+				CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+	}
+# else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (info->size < 0x100000)
+		printf ("  Size: %ld KB in %d Sectors\n",
+				info->size >> 10, info->sector_count);
+	else
+		printf ("  Size: %ld MB in %d Sectors\n",
+				info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Check the type of erased flash
+	 */
+	if (info->flash_id >> 16 == 0x1) {
+		/* Erase AMD flash
+		 */
+		l_sect = -1;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+		addr[0x0555] = 0x80;
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect<=s_last; sect++) {
+			if (info->protect[sect] == 0) { /* not protected */
+				addr = (vu_char *)(info->start[sect]);
+				addr[0] = 0x30;
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto AMD_DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (vu_char *)(info->start[l_sect]);
+		while ((addr[0] & 0x80) != 0x80) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {      /* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+AMD_DONE:
+		/* reset to read mode */
+		addr = (volatile unsigned char *)info->start[0];
+		addr[0] = 0xF0;     /* reset bank */
+
+	} else {
+		/* Erase Intel flash
+		 */
+
+		/* Start erase on unprotected sectors
+		 */
+		for (sect = s_first; sect <= s_last; sect++) {
+			volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+			start = get_timer (0);
+			last = start;
+			if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+				flag = disable_interrupts ();
+
+				/* Erase the block
+				 */
+				addr[0] = 0x00200020;
+				addr[1] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				addr[1] = 0x00D000D0;
+
+				/* re-enable interrupts if necessary
+				 */
+				if (flag)
+					enable_interrupts ();
+
+				/* wait at least 80us - let's wait 1 ms
+				 */
+				udelay (1000);
+
+				last = start;
+				while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+						printf ("Timeout (erase suspended!)\n");
+						/* Suspend erase
+						 */
+						addr[0] = 0x00B000B0;
+						addr[1] = 0x00B000B0;
+						goto DONE;
+					}
+					/* show that we're waiting
+					 */
+					if ((now - last) > 1000) {	/* every second */
+						serial_putc ('.');
+						last = now;
+					}
+				}
+				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+					printf ("*** ERROR: erase failed!\n");
+					goto DONE;
+				}
+			}
+			/* Clear status register and reset to read mode
+			 */
+			addr[0] = 0x00500050;
+			addr[1] = 0x00500050;
+			addr[0] = 0x00FF00FF;
+			addr[1] = 0x00FF00FF;
+		}
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, rc, cc = cnt, res = 0;
+
+	if (info->flash_id >> 16 == 0x1) {
+
+		/* Write to AMD 8-bit flash
+		 */
+		while (cnt > 0) {
+			if ((rc = write_byte(info, addr, *src)) != 0) {
+				return (rc);
+			}
+			addr++;
+			src++;
+			cnt--;
+		}
+
+		return (0);
+	} else {
+
+		/* Write to Intel 64-bit flash
+		 */
+		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+			l = (addr & 3);
+			addr &= ~3;
+
+			for (i = 0; i < 4; i++) {
+				v = (v << 8) + (i < l || i - l >= cc ?
+					*((unsigned char *) addr + i) : *src++);
+			}
+
+			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

board/cpu87/u-boot.lds

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/cradle/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= cradle.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/cradle/lowlevel_init.S

@@ -43,8 +43,8 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
    .endm
 
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -512,4 +512,4 @@ mem_init:
 
    mov   pc, r10
 
-@ End memsetup
+@ End lowlevel_init

board/csb226/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= csb226.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/csb226/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -46,8 +46,8 @@ _TEXT_BASE:
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -429,9 +429,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc, lr

board/csb472/init.S

@@ -129,7 +129,7 @@ ext_bus_cntlr_init:
 	 *******************************************************************/
 	/*WDCR_EBC(pb3ap, 0x07869200)*/
 	WDCR_EBC(pb3ap, 0x04055200)
-	WDCR_EBC(pb3cr, 0xff01c000)
+	WDCR_EBC(pb3cr, 0xf081c000)
 	/********************************************************************
 	 * Memory Bank 1,2,4-7 (Unused) initialization
 	 *******************************************************************/

board/dave/B2/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= B2.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/dave/B2/lowlevel_init.S

@@ -149,8 +149,8 @@ MEMORY_CONFIG:
   .word 0x20      /*MRSR7*/
 
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/*
 		the next instruction fail due memory relocation...

board/dbau1x00/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	= $(BOARD).o flash.o
-SOBJS	= memsetup.o
+SOBJS	= lowlevel_init.o
 
 $(LIB):	.depend $(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/dbau1x00/lowlevel_init.S

@@ -16,8 +16,8 @@
 	.set noreorder
 	.set mips32
 
-	.globl	memsetup
-memsetup:
+	.globl	lowlevel_init
+lowlevel_init:
 	/*
 	 * Step 1) Establish CPU endian mode.
 	 * Db1500-specific:

board/dnp1110/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= dnp1110.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/dnp1110/lowlevel_init.S

@@ -63,8 +63,8 @@ smcnfg:		.long	0x00000000
 
 /* setting up the memory */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	ldr	r0, MEM_BASE
 

board/ep7312/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= ep7312.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/ep7312/lowlevel_init.S

@@ -45,8 +45,8 @@ sdrfpr_val:	.long	0x00000240
 sdconf_val:	.long	0x00000522
 /* setting up the memory */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 	/*
 	 * SYSCON1-3
 	 */

board/esd/apc405/apc405.c

@@ -63,10 +63,56 @@ unsigned char logo_bmp[] =
  */
 #include "../common/lcd.c"
 
-#include "../common/"CFG_LCD_HEADER_NAME
+#include CFG_LCD_HEADER_NAME
 #endif /* CONFIG_LCD_USED */
 
 
+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version <= 1.2 */
+		return 2;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 1.4 */
+		return 4;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 1.5 */
+		return 5;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -120,8 +166,12 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *fpga_ctrl2 =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
 	volatile unsigned char *duart0_mcr =
 		(unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr =
@@ -204,6 +254,11 @@ int misc_init_r (void)
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */
 
+	/*
+	 * Write board revision in FPGA
+	 */
+	*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
+
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
@@ -228,8 +283,11 @@ int misc_init_r (void)
 		 logo_bmp, sizeof(logo_bmp));
 
 	/*
-	 * Enable microcontroller and setup backlight PWM controller
+	 * Reset microcontroller and setup backlight PWM controller
 	 */
+	*fpga_mode |= 0x0014;
+	for (i=0;i<10;i++)
+		udelay(1000);
 	*fpga_mode |= 0x001c;
 	*fuji_lcdbl_pwm = 0x00ff;
 
@@ -243,6 +301,8 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -254,7 +314,8 @@ int checkboard (void)
 		puts(str);
 	}
 
-	putc ('\n');
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld\n", gd->board_type);
 
 	/*
 	 * Disable sleep mode in LXT971

board/esd/common/auto_update.c

@@ -224,6 +224,25 @@ int au_do_update(int i, long sz)
 		start = au_image[i].start;
 		end = au_image[i].start + au_image[i].size - 1;
 
+		/*
+		 * do not update firmware when image is already in flash.
+		 */
+		if (au_image[i].type == AU_FIRMWARE) {
+			char *orig = (char*)start;
+			char *new  = (char *)((char *)hdr + sizeof(*hdr));
+			nbytes = ntohl(hdr->ih_size);
+
+			while(--nbytes) {
+				if (*orig++ != *new++) {
+					break;
+				}
+			}
+			if (!nbytes) {
+				printf("Skipping firmware update - images are identical\n");
+				break;
+			}
+		}
+
 		/* unprotect the address range */
 		/* this assumes that ONLY the firmware is protected! */
 		if (au_image[i].type == AU_FIRMWARE) {

board/esd/hh405/logo_320_240_4bpp.c

@@ -1,292 +1,227 @@
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-  0x5f,0xd7,0xe8,0x9a,0x51,0x17,0x6a,0x1d,0x2f,0x39,0x45,0x80,0xed,0xc1,0xdb,0x58,
-  0x04,0xbc,0x68,0x7f,0x7f,0x3f,0xfb,0x87,0x05,0x32,0xdb,0x27,0x1a,0xcc,0xd9,0xc8,
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-  0xbf,0x68,0x1a,0xeb,0x37,0x8d,0xf9,0x87,0x80,0x88,0x57,0xb9,0x51,0x25,0x25,0x39,
-  0xbc,0x26,0xde,0x14,0x2a,0x0f,0x84,0xaa,0xfb,0x78,0x9b,0x8b,0x31,0xc4,0x43,0xff,
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-  0x41,0x37,0xcc,0xc0,0x05,0xe3,0x14,0x6e,0xe2,0x58,0xdf,0xa9,0xd6,0x40,0x87,0x6c,
-  0x03,0xf1,0xd2,0x80,0x13,0x09,0xb8,0x52,0x36,0xfc,0xcb,0x52,0x07,0xe4,0x04,0x34,
-  0x00,0x79,0x05,0x18,0xbd,0xef,0x98,0x87,0x19,0xad,0x67,0x1e,0xc7,0x96,0x00,0xd5,
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-  0xf3,0xd8,0x87,0xd1,0xc2,0x66,0x64,0x89,0x8e,0x1c,0x74,0x20,0x01,0x6b,0x5c,0x6b,
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board/esd/hh405/logo_320_240_8bpp.c

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+  0xad,0x30,0xf9,0xe3,0xc4,0x89,0x13,0xf7,0x36,0x1e,0x78,0xe8,0xda,0x53,0x07,0x1e,
+  0x7a,0xeb,0x9e,0x37,0xae,0xbd,0x36,0x31,0x71,0x1c,0xe2,0x89,0x13,0x13,0x98,0x4e,
+  0x40,0x80,0x23,0xcc,0xc0,0xfe,0x38,0x66,0x27,0x58,0x72,0xe2,0x38,0x30,0xfe,0xc3,
+  0x47,0x66,0x3e,0xbc,0x7e,0xfd,0x57,0xcf,0x6e,0xee,0x3e,0x58,0xf4,0xb8,0x7c,0xda,
+  0x7d,0x0e,0x7b,0x2a,0x05,0x17,0xc1,0x64,0xb0,0xa0,0x19,0x11,0x58,0x2b,0xe8,0x40,
+  0x42,0x4f,0x28,0x0d,0x31,0x57,0xcc,0xe5,0x72,0x69,0x98,0x49,0xe8,0x01,0x9f,0x0b,
+  0xf3,0xb1,0x58,0xcc,0x59,0x38,0xa4,0x85,0xc3,0x79,0xbf,0x3f,0x9f,0x4f,0xe8,0x4e,
+  0xa6,0x84,0xf1,0xd5,0xc5,0x84,0xce,0x02,0xd4,0xe1,0xb2,0x1b,0xac,0x66,0x81,0xc5,
+  0x04,0x33,0x92,0x00,0xab,0x52,0x9f,0x19,0x77,0x69,0x4c,0x45,0x0f,0x8e,0xb0,0x6c,
+  0x6c,0x14,0xaa,0x80,0xb6,0xee,0x66,0xc5,0x36,0x66,0xa0,0x84,0x1e,0x78,0x15,0xeb,
+  0x09,0x53,0x52,0xa8,0x27,0xfc,0x3e,0xb3,0x15,0xfc,0xdc,0xc0,0x33,0xe3,0xe3,0xdb,
+  0xb7,0xdf,0xfd,0xd7,0x03,0xb5,0x07,0xf7,0xd4,0x3e,0xfd,0xfc,0x8f,0x7f,0x3f,0xfe,
+  0x9f,0xf1,0xed,0x2c,0xa0,0x7c,0x9c,0xb3,0x7d,0x9c,0xe7,0x2d,0x61,0x1c,0x7d,0x07,
+  0xce,0x6b,0xaa,0xaa,0xea,0x7f,0xf3,0xec,0xed,0xfc,0xd7,0x17,0x69,0x70,0xe6,0x83,
+  0x49,0xfb,0x4d,0xb8,0x43,0xaa,0x0e,0x65,0xb1,0x90,0x0f,0x67,0x23,0x95,0x91,0xd1,
+  0xd3,0xbd,0x4e,0xe7,0x88,0x58,0x33,0xf9,0xd8,0x3a,0x75,0xc4,0x29,0x72,0xb8,0xec,
+  0x32,0x0a,0x4a,0x00,0x07,0x8e,0xee,0xf6,0xed,0xf0,0xf9,0xca,0xf4,0x2c,0xf5,0x4c,
+  0x09,0x70,0x1a,0x2d,0x58,0xcd,0xf8,0x42,0xa6,0x0e,0x2b,0x30,0xab,0x8c,0x58,0xb4,
+  0x30,0x33,0xc2,0x2a,0x4b,0x03,0x25,0x1d,0x96,0x9c,0x2e,0x09,0xd7,0xf0,0xc0,0x49,
+  0xe4,0xf9,0xda,0x6f,0x7c,0x34,0x33,0x33,0xf3,0xf8,0xb7,0x0e,0x3e,0x3e,0x73,0x52,
+  0x30,0x73,0x72,0x17,0x26,0x10,0x67,0xc4,0x9e,0xb1,0x0b,0xf7,0xbb,0x4e,0xee,0xda,
+  0xf5,0xe1,0x9b,0xe0,0xbc,0xb1,0xb6,0xb1,0xb1,0x73,0xb7,0x19,0xbd,0x48,0xc6,0xb7,
+  0x14,0xf1,0x2f,0x3a,0x60,0x08,0x43,0x1f,0x54,0x61,0x14,0x07,0x0b,0x05,0x7f,0x3e,
+  0xac,0x69,0xf1,0xfb,0xb5,0x78,0x3c,0x1b,0x8f,0xe3,0x18,0x89,0x23,0xb0,0x63,0x41,
+  0x63,0x49,0x56,0x03,0x25,0x5e,0xc8,0x02,0x26,0x71,0xbe,0x69,0x59,0x8c,0x9c,0x38,
+  0xaf,0xcb,0x6a,0x6b,0x62,0xcf,0x07,0x39,0xd3,0x81,0x2d,0xce,0xe5,0x68,0xa2,0x94,
+  0xc3,0x53,0xb3,0xb3,0xf0,0x63,0x8d,0xcb,0x85,0xd4,0x34,0x19,0xe7,0xdf,0xf3,0x67,
+  0x8a,0xbc,0x09,0xdc,0x24,0x6e,0x5f,0x68,0x42,0xaa,0x9a,0x7e,0xba,0xef,0xe9,0xdf,
+  0x7e,0xf9,0x67,0xfb,0xfe,0xf6,0x00,0x1c,0x5b,0xc0,0x4c,0x3f,0xa4,0x18,0x44,0x14,
+  0x0a,0x55,0x55,0x63,0x63,0x6d,0x2d,0x40,0x5b,0xff,0xfc,0xed,0xdd,0x87,0x33,0xe1,
+  0xa5,0x08,0xf4,0xc0,0x17,0xe0,0x7e,0x80,0xa3,0x18,0x5c,0xb8,0xac,0x2c,0x2e,0xe2,
+  0x97,0x4e,0x74,0x19,0xe4,0xce,0x14,0x94,0x95,0x95,0x44,0x96,0x02,0xab,0x8a,0x69,
+  0x44,0x96,0x94,0xb2,0x42,0x8d,0x7f,0x69,0x46,0x2f,0xb3,0x2c,0x4f,0x1c,0x2c,0x55,
+  0xb4,0x9c,0xbb,0xd4,0x9e,0xf2,0x56,0xc9,0xfd,0x7d,0x2d,0x7b,0x31,0xec,0x6d,0x69,
+  0x79,0xf6,0x17,0x0f,0xef,0xfe,0xf8,0xf4,0xb7,0x5b,0x78,0x76,0x2f,0xd0,0x32,0x0f,
+  0xc7,0x2c,0xd3,0x22,0xa5,0x98,0xe5,0x85,0x50,0x3a,0x3f,0x7f,0x06,0xb6,0xb6,0xaa,
+  0xb6,0xad,0xb8,0x0f,0xff,0x36,0x65,0xa9,0x37,0xac,0x2f,0xab,0x2f,0xe0,0x34,0xf7,
+  0x28,0x73,0xa1,0x9a,0x53,0x73,0x39,0x47,0x4e,0xa2,0xb2,0xd4,0xa1,0x62,0x44,0xb1,
+  0x03,0x82,0xa9,0xa0,0x8a,0xd4,0x54,0xe7,0x4a,0x0e,0x2e,0xc2,0x52,0x5e,0x43,0x15,
+  0xaa,0x2a,0x2b,0x74,0x70,0x3d,0x59,0x0b,0x04,0x0e,0x07,0x2f,0xc9,0x99,0x12,0xeb,
+  0x69,0x1d,0xaa,0x45,0xb5,0x74,0x6a,0x69,0xd7,0x61,0x36,0x43,0x18,0x7d,0xbf,0xa6,
+  0x7d,0xae,0x66,0xae,0xa6,0xbd,0x46,0x32,0x27,0xe2,0xfb,0xb8,0x13,0x39,0xa4,0x9d,
+  0xeb,0xb4,0xf3,0x80,0xc7,0xed,0xed,0xed,0x67,0xce,0xcc,0xb7,0x8d,0xb5,0x6c,0xf5,
+  0x2b,0xd0,0x19,0xb8,0x06,0x1a,0xfe,0x20,0x4e,0xa4,0x99,0x07,0x53,0x70,0x3b,0xde,
+  0x9c,0xdb,0x95,0xdf,0x46,0xef,0x16,0xe2,0xad,0x5a,0xdc,0x22,0x67,0xcf,0xde,0x84,
+  0xc0,0x92,0xa3,0x17,0x59,0x6a,0x4a,0xf8,0xc1,0xcd,0x8b,0x67,0x21,0xf0,0x1c,0x66,
+  0x70,0x8f,0xe9,0xc5,0x8b,0x73,0x73,0x73,0x35,0x67,0xf6,0xb6,0x55,0xbd,0xbb,0x45,
+  0xef,0x21,0xf9,0x86,0x50,0x24,0x6c,0x0b,0x2e,0x3b,0xd4,0xff,0xcb,0xab,0xf9,0xac,
+  0xb9,0x69,0x3a,0x8f,0x7b,0x4c,0x64,0xce,0x96,0x49,0x85,0xd2,0xcd,0xb3,0xd6,0x80,
+  0xee,0x43,0xef,0x8d,0x35,0xbd,0x70,0x7b,0xaf,0x59,0xc7,0x70,0x64,0xc9,0x17,0x81,
+  0x39,0x5d,0x50,0x59,0x4e,0xb2,0x41,0xe1,0x60,0x83,0x18,0x70,0xb0,0xc1,0x2c,0xf2,
+  0xa5,0xc0,0x4a,0x73,0xa6,0xd0,0xc4,0xac,0x67,0x26,0x0e,0xa1,0x9a,0x53,0x73,0x52,
+  0xd7,0x61,0x4a,0xf0,0x00,0xab,0x38,0x2c,0xd6,0xb8,0x80,0x1f,0x9a,0x96,0x73,0x66,
+  0x2b,0x54,0x8b,0x75,0xa6,0x21,0x54,0x1d,0x66,0x4b,0xde,0xc7,0x2e,0xc4,0x37,0x33,
+  0xe2,0x60,0x9e,0x9b,0x2b,0x15,0x48,0x6a,0x4a,0x7b,0x8c,0xed,0x35,0x30,0x72,0xdb,
+  0xaa,0x9a,0xe6,0xef,0xf8,0x87,0x5c,0xc9,0xde,0xa5,0x1d,0xce,0xa2,0x96,0xb7,0x15,
+  0x12,0x41,0xcb,0x97,0x20,0xb7,0x8c,0xbe,0xbe,0xd2,0x46,0x46,0xee,0xd0,0xf8,0x1d,
+  0xa9,0xeb,0xf7,0xbd,0x6b,0xde,0x27,0x24,0x2d,0xb7,0x08,0x82,0x79,0x79,0x34,0xcf,
+  0xf4,0xda,0xda,0xda,0xc6,0xaa,0x9a,0xae,0xb7,0x7c,0xf5,0x4e,0xbd,0xc7,0xfa,0x60,
+  0x21,0x12,0x0a,0x8d,0x38,0x2b,0x8b,0x45,0xb7,0x81,0x13,0x01,0x43,0xce,0x06,0x3e,
+  0x2d,0x8c,0x72,0x63,0x9f,0xa6,0x69,0xc1,0xbf,0xff,0xd0,0xdf,0xcf,0x26,0x21,0xfd,
+  0xa5,0xd8,0x6f,0x39,0x6a,0x12,0xbb,0xd2,0x6c,0x45,0x6a,0x0b,0xae,0x7f,0xfd,0xfa,
+  0x58,0xfb,0xff,0xfe,0x23,0xc2,0xd4,0x62,0xc2,0xaf,0xb9,0xc1,0x83,0x88,0xbb,0x28,
+  0x30,0x64,0x14,0x9b,0x9b,0x97,0xb9,0x65,0x21,0x1e,0x72,0x05,0x77,0x49,0xc0,0x0f,
+  0x4c,0x1b,0x5c,0x2c,0x8d,0x18,0x56,0xa9,0xd0,0x75,0x5b,0xaa,0x95,0xb4,0xdc,0xb2,
+  0xcc,0xd2,0x02,0xf7,0x9a,0x16,0x71,0xfd,0xef,0xfd,0xf2,0xc1,0x73,0x4d,0xe7,0x9a,
+  0xca,0x58,0x93,0x5d,0xc7,0x39,0x8c,0xe7,0xb8,0xde,0xb9,0xa6,0xfe,0xb6,0x96,0x33,
+  0x73,0x9f,0xc5,0xdf,0x19,0x13,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,
+  0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,
+  0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,
+  0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,
+  0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,
+  0x10,0x04,0x41,0x10,0x5b,0xe6,0xbf,0x9f,0xe5,0x54,0xe2,0x36,0x30,0x01,0x00,

board/esd/hub405/hub405.c

@@ -30,6 +30,47 @@
 extern void lxt971_no_sleep(void);
 
 
+int board_revision(void)
+{
+	unsigned long osrl_reg;
+	unsigned long isr1l_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Get version of HUB405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pin(s) (IRQ6/GPIO23)
+	 */
+	osrl_reg = in32(GPIO0_OSRH);
+	isr1l_reg = in32(GPIO0_ISR1H);
+	tcr_reg = in32(GPIO0_TCR);
+	out32(GPIO0_OSRH, osrl_reg & ~0x00030000);     /* output select */
+	out32(GPIO0_ISR1H, isr1l_reg | 0x00030000);    /* input select  */
+	out32(GPIO0_TCR, tcr_reg & ~0x00000100);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00000100;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out32(GPIO0_OSRH, osrl_reg);                   /* output select */
+	out32(GPIO0_ISR1H, isr1l_reg);                 /* input select  */
+	out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x00000100) {
+		/* Revision 1.1 or 1.2 detected */
+		return 1;
+	}
+
+	/* Revision 1.0 */
+	return 0;
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -69,6 +110,8 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
@@ -77,6 +120,7 @@ int misc_init_r (void)
 	unsigned long val;
 	int delay, flashcnt;
 	char *str;
+	char hw_rev[4];
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
@@ -121,14 +165,14 @@ int misc_init_r (void)
 	 */
 	str = getenv("bd_type"); /* this is only set on non prototype hardware */
 	if (str != NULL) {
-		if ((strcmp(str, "swch405") == 0) || (strcmp(str, "hub405") == 0)) {
+		if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
 			unsigned char led_reg_default = 0;
 			str = getenv("ap_pwr");
 			if (!str || (str && (str[0] == '1')))
 				led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
 
 			/*
-			 * Flash LEDs on SWCH405
+			 * Flash LEDs
 			 */
 			for (flashcnt = 0; flashcnt < 3; flashcnt++) {
 				*led_reg = led_reg_default;        /* LED_A..D off */
@@ -150,6 +194,11 @@ int misc_init_r (void)
 	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
 	udelay(1000); /* wait 1ms */
 
+	/*
+	 * Store hardware revision in environment for further processing
+	 */
+	sprintf(hw_rev, "1.%ld", gd->board_type);
+	setenv("hw_rev", hw_rev);
 	return (0);
 }
 
@@ -159,6 +208,8 @@ int misc_init_r (void)
  */
 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -170,7 +221,14 @@ int checkboard (void)
 		puts(str);
 	}
 
-	putc ('\n');
+	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld)\n", gd->board_type);
 
 	/*
 	 * Disable sleep mode in LXT971

board/evb4510/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= evb4510.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^

board/evb4510/lowlevel_init.S

@@ -31,7 +31,7 @@
  *
  * This memory map allows us to relocate from FLASH to SRAM.  After
  * power-on reset the CPU only knows about the FLASH memory at address
- * 0x00000000.	After memsetup completes the memory map will be:
+ * 0x00000000.	After lowlevel_init completes the memory map will be:
  *
  * Memory Addr
  * 0x00000000
@@ -54,8 +54,8 @@
  *
  ***********************************************************************/
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/* preserve the temp register (r12 AKA ip) and remap it. */
 	ldr r1, =SRAM_BASE+0xC

board/gcplus/Makefile

@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= gcplus.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/gcplus/lowlevel_init.S

@@ -29,11 +29,11 @@
 #include "version.h"
 
 
-	.globl	memsetup
-memsetup:
+	.globl	lowlevel_init
+lowlevel_init:
 	/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
 	 * However the darn thing leaves the MMU enabled before handing control
-	 * over to us. So we need to disable the MMU and we use memsetup
+	 * over to us. So we need to disable the MMU and we use lowlevel_init
 	 * to do it.
 	 */
 

board/hidden_dragon/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/hidden_dragon/README

@@ -0,0 +1,60 @@
+U-Boot for Hidden Dragon board
+------------------------------
+
+Hidden Dragon is a MPC824x-based board by Motorola. For the most
+part it is similar to Sandpoint8245 board. So unless otherwise
+mentioned, the codes in this directory are adapted from ../sandpoint
+directory.
+
+Apparently there are very few of this board out there. Even Motorola
+website does not have any info on it.
+
+RAM:
+  start = 0x0000 0000
+  size	= 0x0200 0000 (32 MB)
+
+Flash:
+  BANK ONE:
+    start = 0xFFE0 0000
+    size  = 0x0020 0000 (2 MB)
+    flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
+    flash sectors = 16K, 2x8K, 32K, 31x64K
+
+  BANK TWO:
+    NONE
+
+The processor interrupt vectors reside on the first 256 bytes
+starting from address 0xFFF00000. The "reset vector" (first
+instruction executed after reset) is located on 0xFFF0 0100.
+
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is located in flash separately from
+U-Boot, at the second sector of the first flash bank, starting from
+0xFFE04000 until 0xFFE06000 (8KB).
+
+Network:
+  - RTL8139 chip on the base board	  (SUPPORTED)
+  - RTL8129 chip on the processor board	  (NOT SUPPORTED)
+
+Serial:
+  - Two NS16550 compatible UART on the processor board	(SUPPORTED)
+  - One NS16550 compatible UART on the base board	(UNTESTED)
+
+Misc:
+  VIA686A PCI SuperIO peripheral controller
+  - 2 USB ports		    (UNTESTED)
+  - 2 PS2 ports		    (UNTESTED)
+  - Parallel port	    (UNTESTED)
+  - IDE & floppy interface  (UNTESTED)
+
+  S3 Savage4 video card	    (UNTESTED)
+
+TODO:
+-----
+- Support for the VIA686A based peripherals
+- The RTL8139 driver frequently gives rx error.
+- Support for RTL8129 network controller. (Why is the support removed from
+  rtl8139.c driver?)
+
+(C) Copyright 2004
+Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com

board/hidden_dragon/config.mk

@@ -1,7 +1,6 @@
 #
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -21,7 +20,11 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-mshort-load-bytes -msoft-float
 
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
+#
+# Hidden Dragon boards
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

board/hidden_dragon/early_init.S

@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
+		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CFG_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CFG_INIT_SP_OFFSET@h
+	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr

board/hidden_dragon/flash.c

@@ -0,0 +1,575 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <w83c553f.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+	__attribute__ ((const));
+
+typedef struct {
+	FLASH_WORD_SIZE extval;
+	unsigned short intval;
+} map_entry;
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B, FLASH_AM040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for (p = &chip_map[0];
+	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+		if (p->extval == chip) {
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+
+	/* find vendor id */
+	for (p = &mfct_map[0];
+	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+		if (p->extval == mfct) {
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+
+	return result;
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	/* Enable writes to Hidden Dragon flash */
+	{
+		register unsigned char temp;
+
+		CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				  temp);
+		temp &= ~0x20;	/* clear BIOSWP bit */
+		CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				   temp);
+	}
+
+	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE *const flash =
+			(FLASH_WORD_SIZE *) base_address;
+
+		flash[0xAAA << (3 * i)] = 0xaa;
+		flash[0x555 << (3 * i)] = 0x55;
+		flash[0xAAA << (3 * i)] = 0x90;
+		__asm__ __volatile__ ("sync");
+
+		pflinfo->flash_id =
+			flash_id (flash[0x0], flash[0x2 + 14 * i]);
+
+		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			pflinfo->size = 0x00080000;
+			pflinfo->sector_count = 8;
+			for (j = 0; j < 8; j++) {
+				pflinfo->start[j] =
+					base_address + 0x00010000 * j;
+				pflinfo->protect[j] = flash[(j << 16) | 0x2];
+			}
+			break;
+		case FLASH_STM800AB:
+			pflinfo->size = 0x00100000;
+			pflinfo->sector_count = 19;
+			pflinfo->start[0] = base_address;
+			pflinfo->start[1] = base_address + 0x4000;
+			pflinfo->start[2] = base_address + 0x6000;
+			pflinfo->start[3] = base_address + 0x8000;
+			for (j = 1; j < 16; j++) {
+				pflinfo->start[j + 3] =
+					base_address + 0x00010000 * j;
+			}
+			break;
+		default:
+			/* The chip used is not listed in flash_id
+			   TODO: Change this to explicitly detect the flash type
+			 */
+			{
+				int sector_addr = base_address;
+
+				pflinfo->size = 0x00200000;
+				pflinfo->sector_count = 35;
+				pflinfo->start[0] = sector_addr;
+				sector_addr += 0x4000;	/* 16K */
+				pflinfo->start[1] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[2] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[3] = sector_addr;
+				sector_addr += 0x8000;	/* 32K */
+
+				for (j = 4; j < 35; j++) {
+					pflinfo->start[j] = sector_addr;
+					sector_addr += 0x10000;	/* 64K */
+				}
+			}
+			break;
+		}
+		/* Protect monitor and environment sectors
+		 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE,
+			       CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			       &flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__ ("sync");
+	}
+
+	/* only have 1 bank */
+	return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+		"  Size: %lu KB in %d Sectors\n",
+		mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+		     (flash != (unsigned long *) info->start[i] + size)
+		     && erased; flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+			(i % 5) ? "" : "\n   ",
+			info->start[i],
+			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] +
+						    ((info->start[sect] -
+						      info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+						       info->
+						       start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+				     info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}

board/hidden_dragon/hidden_dragon.c

@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Hidden Dragon "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	/* TODO: Implement board test */
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_hidden_dragon_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_hidden_dragon_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}

board/hidden_dragon/speed.h

@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK	      		CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */

board/hidden_dragon/u-boot.lds

@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/impa7/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= impa7.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/impa7/lowlevel_init.S

@@ -39,8 +39,8 @@ memcfg2_val:	.long	0x00000000 @ upper 16 bits are reserved for CS7 + CS6
 drfpr_val:	.long	0x00000081
 /* setting up the memory */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 	/*
 	 * DRFPR
 	 * 64kHz DRAM refresh

board/incaip/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	= $(BOARD).o flash.o
-SOBJS	= memsetup.o
+SOBJS	= lowlevel_init.o
 
 $(LIB):	.depend $(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/incaip/lowlevel_init.S

@@ -269,9 +269,9 @@ sdram_init:
 	.end	sdram_init
 
 
-	.globl	memsetup
-	.ent	memsetup
-memsetup:
+	.globl	lowlevel_init
+	.ent	lowlevel_init
+lowlevel_init:
 
 	/* EBU, CGU and SDRAM Initialization.
 	 */
@@ -292,4 +292,4 @@ memsetup:
 	j	ra
 	nop
 
-	.end	memsetup
+	.end	lowlevel_init

board/inka4x0/inka4x0.c

@@ -43,13 +43,11 @@ static void sdram_start (int hi_addr)
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
 
 	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-		hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
 	__asm__ volatile ("sync");
 
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 	__asm__ volatile ("sync");
 
 #if SDRAM_DDR
@@ -63,13 +61,11 @@ static void sdram_start (int hi_addr)
 #endif
 
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 	__asm__ volatile ("sync");
 
 	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-		hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
 	__asm__ volatile ("sync");
 
 	/* set mode register */
@@ -177,15 +173,94 @@ void flash_preinit(void)
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
-#ifdef  CONFIG_PCI
+#define GPIO_PSC3_9	0x04000000UL
+
+int misc_init_f (void)
+{
+	uchar tmp[10];
+	int i, br;
+
+	i = getenv_r("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CFG_BRIGHTNESS;
+	if (br > 255)
+		br = 255;
+
+	/* Initialize GPIO output pins.
+	 */
+	/* Configure GPT as GPIO output */
+	*(vu_long *)MPC5XXX_GPT0_ENABLE =
+	*(vu_long *)MPC5XXX_GPT1_ENABLE =
+	*(vu_long *)MPC5XXX_GPT2_ENABLE =
+	*(vu_long *)MPC5XXX_GPT3_ENABLE =
+	*(vu_long *)MPC5XXX_GPT4_ENABLE =
+	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24;
+
+	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
+	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
+	*(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
+	*(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
+	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
+
+	/* Configure PSC3_6,7 as GPIO output */
+	*(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
+	*(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
+
+	/* Configure PSC3_8 as GPIO output, no interrupt */
+	*(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
+	*(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
+	*(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
+
+	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
+	*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
+	*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
+
+	/*
+	 * Reset Coral-P graphics controller
+	 */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC3_9;
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC3_9;
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
 static struct pci_controller hose;
 
 extern void pci_mpc5xxx_init(struct pci_controller *);
 
 void pci_init_board(void)
 {
-        pci_mpc5xxx_init(&hose);
+	pci_mpc5xxx_init(&hose);
 }
 #endif
 
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */

board/innokom/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= innokom.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/innokom/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -46,8 +46,8 @@ _TEXT_BASE:
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -429,9 +429,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc, lr

board/lart/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= lart.o flash.o
-SOBJS	:= flashasm.o memsetup.o
+SOBJS	:= flashasm.o lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/lart/lowlevel_init.S

@@ -53,8 +53,8 @@ mecr:		.long	0x00060006
 
 /* setting up the memory */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 	ldr	r0, MEM_BASE
 
 	/* Setup the flash memory */

board/logodl/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= logodl.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^

board/logodl/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -46,8 +46,8 @@ _TEXT_BASE:
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -429,9 +429,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc, lr

board/lpd7a40x/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= lpd7a40x.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/lpd7a40x/lowlevel_init.S

@@ -131,8 +131,8 @@
 _TEXT_BASE:
 	.word	TEXT_BASE
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 	mov	r9, lr	@ save return address
 
 	/* memory control configuration */

board/lubbock/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= lubbock.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/lubbock/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -43,8 +43,8 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -403,9 +403,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc, lr

board/modnet50/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= modnet50.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^

board/modnet50/lowlevel_init.S

@@ -51,8 +51,8 @@
 #define NETARM_MMAP_CS4_MASK	(~(PHYS_EXT_SIZE - 1))
 
 /* setting up the memory */
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 #if defined(CONFIG_MODNET50)
 	ldr	pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
@@ -187,7 +187,7 @@ memsetup_cs3:
 #endif /* CONFIG_MODNET50 */
 
 
-memsetup_end:
+lowlevel_init_end:
 	/*
 	 * manipulate address in lr and ip to match new
 	 * address space

board/mpc8260ads/config.mk

@@ -29,4 +29,9 @@
 # MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards
 #
 
-TEXT_BASE = 0xfff00000
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+endif

board/mpl/vcma9/Makefile

@@ -28,7 +28,7 @@ LIB	= lib$(BOARD).a
 OBJS	:= vcma9.o flash.o cmd_vcma9.o
 OBJS	+= ../common/common_util.o ../common/memtst.o
 
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/mpl/vcma9/lowlevel_init.S

@@ -130,8 +130,8 @@
 _TEXT_BASE:
 	.word	TEXT_BASE
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */

board/mx1ads/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= mx1ads.o syncflash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/mx1ads/lowlevel_init.S

@@ -1,5 +1,5 @@
 /*
- * board/mx1ads/memsetup.S
+ * board/mx1ads/lowlevel_init.S
  *
  * (c) Copyright 2004
  * Techware Information Technology, Inc.
@@ -33,8 +33,8 @@
 _TEXT_BASE:
 	.word	TEXT_BASE
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 /* memory controller init	 	*/
 
 	ldr  r1, =SDCTL0

board/mx1ads/mx1ads.c

@@ -25,7 +25,7 @@
 
 #include <common.h>
 /*#include <mc9328.h>*/
-#include <asm/arch-arm920t/imx-regs.h>
+#include <asm/arch/imx-regs.h>
 
 /* ------------------------------------------------------------------------- */
 

board/mx1fs2/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= mx1fs2.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^

board/mx1fs2/lowlevel_init.S

@@ -22,8 +22,8 @@
 #include <version.h>
 #include <asm/arch/imx-regs.h>
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	mov	r10, lr
 

board/nc650/nc650.c

@@ -70,6 +70,36 @@ const uint sdram_table[] = {
 	0x7ffffc07, _not_used_, _not_used_, _not_used_
 };
 
+const uint nand_flash_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
+	0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
+	0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
+};
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -182,6 +212,12 @@ long int initdram (int board_type)
 
 	udelay (10000);
 
+	/* Configure UPMB for NAND flash access */
+	upmconfig (UPMB, (uint *) nand_flash_table,
+			   sizeof (nand_flash_table) / sizeof (uint));
+
+	memctl->memc_mbmr = CFG_MBMR_NAND;
+
 	return (size_b0);
 }
 

board/ns9750dev/platform.S

@@ -34,7 +34,7 @@
 #include <version.h>
 
 #if defined(CONFIG_NS9750DEV)
-# ifdef CONFIG_INIT_CRITICAL
+# ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #  include <./ns9750_sys.h>
 #  include <./ns9750_mem.h>
 # endif
@@ -74,7 +74,7 @@ _PHYS_FLASH:
 _CAS_LATENCY:
 	.word	0x00022000	@ for CAS2 latency
 
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 .globl platformsetup
 platformsetup:
 
@@ -295,4 +295,4 @@ _AHB_MONITOR_START:
 		 NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
 _AHB_MONITOR_END:
 
-#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

board/ocotea/config.mk

@@ -30,7 +30,7 @@
 ifeq ($(ramsym),1)
 TEXT_BASE = 0x07FD0000
 else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1

board/ocotea/flash.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
@@ -43,7 +43,9 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */
 
-#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     BOOT_SMALL_FLASH        0x40 /* 01000000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
 #define     FLASH_ONBD_N            2	/* 00000010 */
 #define     FLASH_SRAM_SEL          1	/* 00000001 */
 
@@ -55,8 +57,8 @@
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
-	{0xFF800000, 0xFF900000, 0xFFC00000},	/* 0:000: configuraton 4 */
-	{0xFF900000, 0xFF800000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
 	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
@@ -131,6 +133,12 @@ unsigned long flash_init(void)
 		total_b += flash_info[i].size;
 	}
 
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[2]);
+
 	return total_b;
 }
 
@@ -153,6 +161,9 @@ void flash_print_info(flash_info_t * info)
 	case FLASH_MAN_AMD:
 		printf("AMD ");
 		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
 	case FLASH_MAN_FUJ:
 		printf("FUJITSU ");
 		break;
@@ -300,6 +311,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
+	case (FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
 	case (FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
@@ -312,8 +328,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040) ||
-	    (info->flash_id == FLASH_AMD016)) {
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * 0x00010000);
 	} else {
@@ -343,6 +359,15 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of	*
+		 * reading flash protection for upper 8 Mb of flash	*/
+		if ( i == 32 ) {
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+		}
+
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
 		else
@@ -432,7 +457,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-			printf("Erasing sector %p\n", addr2);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
 				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;

board/ocotea/ocotea.c

@@ -37,6 +37,15 @@ void fpga_init (void);
 int board_early_init_f (void)
 {
 	unsigned long mfr;
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned long cs0_base;
+	unsigned long cs0_size;
+	unsigned long cs0_twt;
+	unsigned long cs2_base;
+	unsigned long cs2_size;
+	unsigned long cs2_twt;
+
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC CONFIG
 	  +-------------------------------------------------------------------------*/
@@ -47,17 +56,49 @@ int board_early_init_f (void)
 	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
 
 	/*-------------------------------------------------------------------------+
-	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  | FPGA. Initialize bank 7 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
-	      EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	if (switch_status & 0x40) {
+		cs0_base = 0xFFE00000;
+		cs0_size = EBC_BXCR_BS_2MB;
+		cs0_twt = 8;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_4MB;
+		cs2_twt = 10;
+	} else {
+		cs0_base = 0xFFC00000;
+		cs0_size = EBC_BXCR_BS_4MB;
+		cs0_twt = 10;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_2MB;
+		cs2_twt = 8;
+	}
+
+	/*-------------------------------------------------------------------------+
+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 
 	/*-------------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -75,15 +116,15 @@ int board_early_init_f (void)
 	/*-------------------------------------------------------------------------+
 	  | 4 MB FLASH. Initialize bank 2 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
-	      EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 
 	/*-------------------------------------------------------------------------+
 	  | FPGA. Initialize bank 7 with default values.