Accelerate booting on TRAB board: read and check autoupdate image

headers first instead of always reading the whole images.
Fix typo in MPC5XXX code (pointed out by Victor Wren)
2003-12-06 11:20:01 +00:00 · 2003-12-05 21:08:38 +00:00 · 2003-12-03 23:53:42 +00:00 · 2003-11-25 16:55:19 +00:00 · 2003-11-17 21:45:27 +00:00 · 2003-11-17 21:14:37 +00:00
241 changed files with 18183 additions and 3719 deletions
@@ -1,7 +1,139 @@
+======================================================================
+Changes since U-Boot 1.0.0:
+======================================================================
+
+* Accelerate booting on TRAB board: read and check  autoupdate  image
+  headers first instead of always reading the whole images.
+
+* Fix type in MPC5XXX code (pointed out by Victor Wren)
+
+* Enabled password check on RMU board
+
+* Fix configuration problem with IceCube in LOWBOOT configuration:
+  envrionment got embedded, corrupting the image layout.
+
+* Fix NEC display names (it's 6440 [for 640x480], not 6640).
+
+* Added BMS2003 board
+  add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
+
+* Fix flash driver for TRAB board (must use Unlock Bypass Reset
+  command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
+  and CPLD
+
+* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
+  recent tools
+
+* Add checksum verification to 'imls' command
+
+* Add bd_info fields needed for 4xx Linux I2C driver
+
+* Patch by Martin Krause, 4 Nov. 2003:
+  Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
+
+* Print used network interface when CONFIG_NET_MULTI is set
+
+* Patch by Bernhard Kuhn, 28 Oct 2003:
+  Add low boot support for MPC5200
+
+* Fix problem with dual PCMCIA support (NSCU)
+
+* Fix MPC5200 I2C initialization function
+
 ======================================================================
 Changes for U-Boot 1.0.0:
 ======================================================================

+* Fix parameter passing to standalone images with bootm command
+
+* Patch by Kyle Harris, 30 Oct 2003:
+  Fix build errors for ixdp425 board
+
+* Patch by David M. Horn, 29 Oct 2003:
+  Fixes to build under CYGWIN
+
+* Get IceCube MGT5100 working (again)
+
+* Fix problems in memory test on some boards (which was not
+  non-destructive as intended)
+
+* Patch by Gary Jennejohn, 28 Oct 2003:
+  Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
+  to prevent stack overflow on ARM systems
+
+* Patch by Stephan Linz, 28 Oct 2003:
+  fix init sequence error for NIOS port
+
+* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
+
+* Add CONFIG_VERSION_VARIABLE to TRAB configuration
+
+* Patch by Xiao Xianghua, 23 Oct 2003:
+  small patch for mpc85xx
+
+* Fix small problem in MPC5200 I2C driver
+
+* Fix FCC3 support on ATC board
+
+* Correct header printing for multi-image files in do_bootm()
+
+* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
+
+* Fix PCI problems on PPChameleon board
+
+* Patch by Steven Scholz, 18 Oct 2003:
+  Fix AT91RM9200 ethernet driver
+
+* Patch by Nye Liu, 17 Oct 2003:
+  Fix typo in include/mpc8xx.h
+
+* Patch by Richard Woodruff, 16 Oct 03:
+  Fixes for cpu/arm925/interrupt.c
+  - Initialize timestamp & lastdec vars.
+  - fix timestamp overflows.
+  - fix lastdec overflow.
+  - smarter normalization to allow udelay() below 1ms to work.
+
+* Patch by Scott McNutt, 16 Oct
+  add networking support for the Altera Nios Development Kit,
+  Cyclone Edition (DK-1C20)
+
+* Patch by Jon Diekema, 14 Oct 2003:
+  add hint about doc/README.silent to README file
+
+* Add CompactFlash support for NSCU
+
+* Fix PCI problems on PPChameleonEVB
+
+* TRAB auto-update: Base decision if we have to strip the image
+  header on image type as encoded in the header
+  (include image type patch by Martin Krause, 17 Oct 2003)
+
+* Patches by Xianghua Xiao, 15 Oct 2003:
+
+  - Added Motorola CPU 8540/8560 support (cpu/85xx)
+  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
+  - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+
+* Fix flash timings on TRAB board
+
+* Make sure HUSH is initialized for running auto-update scripts
+
+* Make 5200 reset command _really_ reset the board, without running
+  any other code after it
+
+* Fix errors with flash erase when range spans  across banks
+  that are mapped in reverse order
+
+* Fix flash mapping and display on P3G4 board
+
+* Patch by Kyle Harris, 15 Jul 2003:
+  - add support for Intel IXP425 CPU
+  - add support for IXDP425 eval board
+
+* Added config option CONFIG_SILENT_CONSOLE.  See doc/README.silent
+  for more information
+
 * Patch by Steven Scholz, 10 Oct 2003
  - Add support for Altera FPGA ACEX1K

@@ -21,7 +153,7 @@ Changes for U-Boot 1.0.0:
 * Patch by Martin Krause, 09 Oct 2003:
  Fixes for TRAB board
  - /board/trab/rs485.c: correct baudrate
-  - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in 
+  - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
    udelay(); fix some timing problems with adc controller
  - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
    modify commands: touch and buzzer
@@ -71,7 +203,7 @@ Changes for U-Boot 1.0.0:
    link state to the fault LED.
  - In NetLoop, make the Fault LED reflect the link status.  The link
    status gets updated on entry, and on timeouts.
-     
+
 * Patch by Anders Larsen, 18 Sep 2003:
  allow mkimage to build and run on Cygwin-hosted systems

@@ -18,14 +18,14 @@ N: Dr. Bruno Achauer
 E: bruno@exet-ag.de
 D: Support for NetBSD (both as host and target system)

-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
 N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration

+N: Swen Anderson
+E: sand@peppercon.de
+D: ERIC Support
+
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA board support, ARTOS support.
@@ -190,6 +190,11 @@ N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)

+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+
 N: Thomas Lange
 E: thomas@corelatus.se
 D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
@@ -307,12 +312,6 @@ E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com

-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
-
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
@@ -112,10 +112,6 @@ Dave Ellis <DGE@sixnetio.com>

 	SXNI855T		MPC8xx

-Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
-
-	ADDERII			MPC852T
-
 Thomas Frieden <ThomasF@hyperion-entertainment.com>

 	AmigaOneG3SE		MPC7xx
@@ -158,6 +154,10 @@ Sangmoon Kim <dogoil@etinsys.com>

 	debris			MPC8245

+Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
+
+	ADDERII			MPC852T
+
 Nye Liu <nyet@zumanetworks.com>

 	ZUMA			MPC7xx_74xx
@@ -240,6 +240,11 @@ John Zhan <zhanz@sinovee.com>

 	svm_sc8xx		MPC8xx

+Xianghua Xiao <x.xiao@motorola.com>
+
+	MPC8540ADS		MPC8540
+	MPC8560ADS		MPC8560
+
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
@@ -289,6 +294,7 @@ Kyle Harris <kharris@nexus-tech.net>

 	lubbock			xscale
 	cradle			xscale
+	ixdp425			xscale

 Gary Jennejohn <gj@denx.de>

@@ -86,6 +86,14 @@ LIST_8260="	\
 	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
 "

+#########################################################################
+## MPC85xx Systems (includes 8540, 8560 etc.)
+#########################################################################
+
+LIST_85xx="	\
+	MPC8540ADS	MPC8560ADS					\
+"
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -102,6 +110,7 @@ LIST_7xx="	\
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
 	  ${LIST_8xx}  \
 	  ${LIST_824x} ${LIST_8260} \
+	  ${LIST_85xx}	\
 	  ${LIST_4xx}		    \
 	  ${LIST_74xx} ${LIST_7xx}"

@@ -133,8 +142,10 @@ LIST_ARM9="	\

 LIST_pxa="cradle csb226 innokom lubbock wepep250"

+LIST_ixp="ixdp425"

-LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
+
+LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"

 #########################################################################
 ## MIPS Systems
@@ -178,7 +189,10 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
+	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
+	arm|SA|ARM7|ARM9|pxa|ixp| \
+	mips| \
+	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}
@@ -106,6 +106,9 @@ endif
 ifeq ($(CPU),ppc4xx)
 OBJS +=	cpu/$(CPU)/resetvec.o
 endif
+ifeq ($(CPU),mpc85xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif

 LIBS  =	board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
@@ -200,14 +203,26 @@ cmi_mpc5xx_config:	unconfig
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
-IceCube_5200_config	\
+MPC5200LITE_config		\
+MPC5200LITE_LOWBOOT_config	\
+MPC5200LITE_LOWBOOT08_config	\
+icecube_5200_config		\
+IceCube_5200_config		\
 IceCube_5100_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _5200,$@)" ] || \
+	@[ -z "$(findstring LOWBOOT,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+		  echo "... with LOWBOOT configuration" ; \
+		}
+	@[ -z "$(findstring LOWBOOT08,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
+		  echo "... with 8 MB flash only" ; \
+		}
+	@[ -z "$(findstring 5200,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
 		  echo "... with MPC5200 processor" ; \
 		}
-	@[ -z "$(findstring _5100,$@)" ] || \
+	@[ -z "$(findstring 5100,$@)" ] || \
 		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
 		  echo "... with MGT5100 processor" ; \
 		}
@@ -226,6 +241,12 @@ ADS860_config:	unconfig
 AMX860_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel

+bms2003_config	:	unconfig
+	@echo "#define CONFIG_BMS2003" >include/config.h
+	@echo "#define CONFIG_LCD" >>include/config.h
+	@echo "#define CONFIG_NEC_NL6448BC33_54" >>include/config.h
+	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+
 c2mon_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx c2mon

@@ -458,7 +479,7 @@ TQM862M_100MHz_config:	unconfig
 		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
-		  echo "#define CONFIG_NEC_NL6648BC20"	>>include/config.h ; \
+		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
 		  echo "... with LCD display" ; \
 		}
 	@./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
@@ -774,6 +795,16 @@ TQM8265_AA_config:  unconfig
 ZPC1900_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900

+#########################################################################
+## MPC85xx Systems
+#########################################################################
+
+MPC8540ADS_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
+
+MPC8560ADS_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -888,6 +919,9 @@ csb226_config	:	unconfig
 innokom_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa innokom

+ixdp425_config	:	unconfig
+	@./mkconfig $(@:_config=) arm ixp ixdp425
+
 lubbock_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa lubbock

@@ -981,7 +1015,7 @@ clean:
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
-	rm -f board/trab/trab_fkt board/trab/config.tmp
+	rm -f board/trab/trab_fkt board/*/config.tmp

 clobber:	clean
 	find . -type f \
@@ -146,6 +146,7 @@ Directory Hierarchy:
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
 - cpu/mpc8260	Files specific to Motorola MPC8260 CPU
+- cpu/mpc85xx	Files specific to Motorola MPC85xx CPUs
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs


@@ -199,6 +200,10 @@ Directory Hierarchy:
 - board/mbx8xx	Files specific to MBX	     boards
 - board/mpc8260ads
 		Files specific to MPC8260ADS and PQ2FADS-ZU boards
+- board/mpc8540ads
+		Files specific to MPC8540ADS boards
+- board/mpc8560ads
+		Files specific to MPC8560ADS boards
 - board/mpl/	Files specific to boards manufactured by MPL
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
@@ -210,7 +215,7 @@ Directory Hierarchy:
 - board/oxc	Files specific to OXC        boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
- board/omap1610inn  
+- board/omap1610inn
 		Files specific to OMAP 1610 Innovator boards
 - board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
 - board/pm826	Files specific to PM826      boards
@@ -306,6 +311,7 @@ The following options need to be configured:
 		CONFIG_MPC823,	CONFIG_MPC850,	CONFIG_MPC855,	CONFIG_MPC860
 	or	CONFIG_MPC5xx
 	or	CONFIG_MPC824X, CONFIG_MPC8260
+	or	CONFIG_MPC85xx
 	or	CONFIG_IOP480
 	or	CONFIG_405GP
 	or	CONFIG_405EP
@@ -356,7 +362,8 @@ The following options need to be configured:
 		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
 		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
 		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,     CONFIG_RBC823,     CONFIG_ZPC1900
+		CONFIG_NETVIA,     CONFIG_RBC823,     CONFIG_ZPC1900,
+		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS

 		ARM based boards:
 		-----------------
@@ -480,6 +487,11 @@ The following options need to be configured:
 		default i/o. Serial console can be forced with
 		environment 'console=serial'.

+                When CONFIG_SILENT_CONSOLE is defined, all console
+                messages (by U-Boot and Linux!) can be silenced with
+                the "silent" environment variable. See
+                doc/README.silent for more information.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
@@ -591,7 +603,7 @@ The following options need to be configured:
 		CFG_CMD_DHCP	  DHCP support
 		CFG_CMD_DIAG    * Diagnostics
 		CFG_CMD_DOC     * Disk-On-Chip Support
-		CFG_CMD_DTT       Digital Therm and Thermostat 
+		CFG_CMD_DTT       Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -838,13 +850,18 @@ The following options need to be configured:
 		display); also select one of the supported displays
 		by defining one of these:

-		CONFIG_NEC_NL6648AC33:
+		CONFIG_NEC_NL6448AC33:

-			NEC NL6648AC33-18. Active, color, single scan.
+			NEC NL6448AC33-18. Active, color, single scan.

-		CONFIG_NEC_NL6648BC20
+		CONFIG_NEC_NL6448BC20

-			NEC NL6648BC20-08. 6.5", 640x480.
+			NEC NL6448BC20-08. 6.5", 640x480.
+			Active, color, single scan.
+
+		CONFIG_NEC_NL6448BC33_54
+
+			NEC NL6448BC33-54. 10.4", 640x480.
 			Active, color, single scan.

 		CONFIG_SHARP_16x9
@@ -893,9 +910,9 @@ The following options need to be configured:
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.

-                NOTE: the bzip2 algorithm requires a lot of RAM, so
-                the malloc area (as defined by CFG_MALLOC_LEN) should
-                be at least 4MB.
+		NOTE: the bzip2 algorithm requires a lot of RAM, so
+		the malloc area (as defined by CFG_MALLOC_LEN) should
+		be at least 4MB.

 - Ethernet address:
 		CONFIG_ETHADDR
@@ -1757,13 +1774,13 @@ the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.

 - CFG_FAULT_ECHO_LINK_DOWN:
-	        Echo the inverted Ethernet link state to the fault LED.
+		Echo the inverted Ethernet link state to the fault LED.

 		Note: If this option is active, then CFG_FAULT_MII_ADDR
 		      also needs to be defined.

 - CFG_FAULT_MII_ADDR:
-	        MII address of the PHY to check for the Ethernet link state.
+		MII address of the PHY to check for the Ethernet link state.

 Low Level (hardware related) configuration options:
 ---------------------------------------------------
@@ -1774,9 +1791,9 @@ Low Level (hardware related) configuration options:
 - CFG_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.

-                Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
-                and RPXsuper) to be able to adjust the position of
-                the IMMR register after a reset.
+		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
+		and RPXsuper) to be able to adjust the position of
+		the IMMR register after a reset.

 - Floppy Disk Support:
 		CFG_FDC_DRIVE_NUMBER
@@ -1950,7 +1967,8 @@ configurations; the following names are supported:
    GEN860T_config	  EBONY_config		FPS860L_config
    ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
    at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
-    omap1610inn_config	  ZPC1900_config
+    omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
+    MPC8560ADS_config

 Note: for some board special configuration names may exist; check  if
      additional  information is available from the board vendor; for
@@ -2317,8 +2335,8 @@ defines the following image properties:
  LynxOS, pSOS, QNX, RTEMS, ARTOS;
  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
-  IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: PowerPC).
+  IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -63,7 +63,7 @@ $(TARGETDEBUGLIB): $(DEBUGOBJS)
 	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)

 INCS   = -I. -Ix86emu -I../../include
-CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
 CDEBUGFLAGS = -DDEBUG

 .c.o:
@@ -61,7 +61,7 @@ $(TARGETDEBUGLIB): $(DEBUGOBJS)
 	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)

 INCS   = -I. -Ix86emu -I../../include
-CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
 CDEBUGFLAGS = -DDEBUG

 .c.o:
@@ -230,8 +230,8 @@ static long int dram_size (long int mamr_value, long int *base,
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
+ 	ulong cnt, val, size;
+ 	ulong save[32];			/* to make test non-destructive */
 	unsigned char i = 0;

 	memctl->memc_mamr = mamr_value;
@@ -250,7 +250,13 @@ static long int dram_size (long int mamr_value, long int *base,

 	/* check at base address */
 	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
 		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
 		return (0);
 	}

@@ -261,7 +267,14 @@ static long int dram_size (long int mamr_value, long int *base,
 		*addr = save[--i];

 		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
 		}
 	}
 	return (maxsize);
@@ -41,5 +41,3 @@
 * | 			   |
 * | ...                   |
 *****************************************************************************/
-
-
@@ -26,4 +26,3 @@
 #

 TEXT_BASE = 0xFE000000
-
@@ -144,4 +144,3 @@ SECTIONS
  _end = . ;
  PROVIDE (end = .);
 }
-
@@ -92,20 +92,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
 	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
 	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
 	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
@@ -128,8 +128,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
 	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
 	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
 #if 0
 	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
 #else
@@ -269,7 +269,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 			  ulong orx, volatile uchar * base)
 {
 	volatile uchar c = 0xff;
-	ulong cnt, val;
+	ulong cnt, val, size;
 	volatile ulong *addr;
 	volatile uint *sdmr_ptr;
 	volatile uint *orx_ptr;
@@ -344,7 +344,13 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	*addr = 0;

 	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
 		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
 		return (0);
 	}

@@ -353,10 +359,17 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 		val = *addr;
 		*addr = save[--i];
 		if (val != ~cnt) {
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
 			/* Write the actual size to ORx
 			 */
-			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
-			return (cnt * sizeof (long));
+			*orx_ptr = orx | ~(size - 1);
+			return (size);
 		}
 	}
 	return (maxsize);
@@ -228,8 +228,8 @@ static long int dram_size (long int mamr_value, long int *base,
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
+ 	ulong cnt, val, size;
+ 	ulong save[32];			/* to make test non-destructive */
 	unsigned char i = 0;

 	memctl->memc_mamr = mamr_value;
@@ -248,7 +248,13 @@ static long int dram_size (long int mamr_value, long int *base,

 	/* check at base address */
 	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
 		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
 		return (0);
 	}

@@ -259,7 +265,14 @@ static long int dram_size (long int mamr_value, long int *base,
 		*addr = save[--i];

 		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
 		}
 	}
 	return (maxsize);
@@ -51,7 +51,7 @@ int gunzip(void *, int, unsigned char *, int *);
 int board_pre_init (void)
 {
 	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
-        out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */
+	out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */

 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -68,7 +68,7 @@ int board_pre_init (void)
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
 	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
 	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
@@ -46,8 +46,8 @@ unsigned long flash_init (void)
 #else
 	unsigned long size_b0;
 	int i;
-        uint pbcr;
-        unsigned long base_b0;
+	uint pbcr;
+	unsigned long base_b0;
 	int size_val = 0;

 	/* Init: no FLASHes known */
@@ -64,14 +64,14 @@ unsigned long flash_init (void)
 			size_b0, size_b0<<20);
 	}

-        /* Setup offsets */
-        flash_get_offsets (-size_b0, &flash_info[0]);
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);

-        /* Re-do sizing to get full correct info */
-        mtdcr(ebccfga, pb0cr);
-        pbcr = mfdcr(ebccfgd);
-        mtdcr(ebccfga, pb0cr);
-        base_b0 = -size_b0;
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
 	switch (size_b0) {
 	case 1 << 20:
 		size_val = 0;
@@ -90,15 +90,15 @@ unsigned long flash_init (void)
 		break;
 	}
 	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
-        mtdcr(ebccfgd, pbcr);
+	mtdcr(ebccfgd, pbcr);

-        /* Monitor protection ON by default */
-        (void)flash_protect(FLAG_PROTECT_SET,
-                            -CFG_MONITOR_LEN,
-                            0xffffffff,
-                            &flash_info[0]);
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);

-        flash_info[0].size = size_b0;
+	flash_info[0].size = size_b0;

 	return (size_b0);
 #endif
@@ -40,11 +40,11 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 	short n;

 	/* set up sector start address table */
-        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
 	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
 	    for (i = 0; i < info->sector_count; i++)
 		info->start[i] = base + (i * 0x00010000);
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@@ -58,7 +58,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 			base += 64 << 10;
 			++i;
 		}
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@@ -75,7 +75,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-        } else {
+	} else {
 	    if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
@@ -103,10 +103,10 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 void flash_print_info  (flash_info_t *info)
 {
 	int i;
-        int k;
-        int size;
-        int erased;
-        volatile unsigned long *flash;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;

 	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("missing or unknown FLASH type\n");
@@ -164,28 +164,28 @@ void flash_print_info  (flash_info_t *info)
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
 #ifdef CFG_FLASH_EMPTY_INFO
-                /*
-                 * Check if whole sector is erased
-                 */
-                if (i != (info->sector_count-1))
-                  size = info->start[i+1] - info->start[i];
-                else
-                  size = info->start[0] + info->size - info->start[i];
-                erased = 1;
-                flash = (volatile unsigned long *)info->start[i];
-                size = size >> 2;        /* divide by 4 for longword access */
-                for (k=0; k<size; k++)
-                  {
-                    if (*flash++ != 0xffffffff)
-                      {
-                        erased = 0;
-                        break;
-                      }
-                  }
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }

 		if ((i % 5) == 0)
 			printf ("\n   ");
-                /* print empty and read-only info */
+		/* print empty and read-only info */
 		printf (" %08lX%s%s",
 			info->start[i],
 			erased ? " E" : "  ",
@@ -219,7 +219,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	short n;
 	CFG_FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-        volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;

 	/* Write auto select command: read Manufacturer ID */
 	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
@@ -288,42 +288,42 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		break;				/* => 2 MB		*/

 	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
-	        info->flash_id += FLASH_STMW320DT;
-	        info->sector_count = 67;
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
-	        info->flash_id += FLASH_AM320T;
-	        info->sector_count = 71;
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
-	        info->flash_id += FLASH_AM320B;
+		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
-	        info->flash_id += FLASH_AMDL322T;
-	        info->sector_count = 71;
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
-	        info->flash_id += FLASH_AMDL322B;
+		info->flash_id += FLASH_AMDL322B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
-	        info->flash_id += FLASH_AMDL323T;
+		info->flash_id += FLASH_AMDL323T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
-	        info->flash_id += FLASH_AMDL323B;
+		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
-	        info->flash_id += FLASH_AM640U;
+		info->flash_id += FLASH_AM640U;
 		info->sector_count = 128;
 		info->size = 0x00800000;  break;	/* => 8 MB	*/

@@ -346,11 +346,11 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	}

 	/* set up sector start address table */
-        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
 	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
 	    for (i = 0; i < info->sector_count; i++)
 		info->start[i] = base + (i * 0x00010000);
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@@ -364,7 +364,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			base += 64 << 10;
 			++i;
 		}
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@@ -381,13 +381,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-        } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
 		/* set sector offsets for top boot block type		*/
 		base += info->size;
 		i = info->sector_count;
-                /*  1 x 16k boot sector */
+		/*  1 x 16k boot sector */
 		base -= 16 << 10;
-                --i;
+		--i;
 		info->start[i] = base;
 		/*  2 x 8k  boot sectors */
 		for (n=0; n<2; ++n) {
@@ -395,9 +395,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-                /*  1 x 32k boot sector */
+		/*  1 x 32k boot sector */
 		base -= 32 << 10;
-                --i;
+		--i;
 		info->start[i] = base;

 		while (i > 0) {			/* 64k regular sectors	*/
@@ -405,7 +405,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-        } else {
+	} else {
 	    if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
@@ -432,10 +432,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
-                if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-                  info->protect[i] = 0;
-                else
-                  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
 	}

 	/*
@@ -459,7 +459,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	volatile CFG_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
-        int i;
+	int i;

 	if ((s_first < 0) || (s_first > s_last)) {
 		if (info->flash_id == FLASH_UNKNOWN) {
@@ -498,25 +498,25 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
-                    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                        addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                        addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                        addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
-                        for (i=0; i<50; i++)
-                          udelay(1000);  /* wait 1 ms */
-                    } else {
-                        if (sect == s_first) {
-                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                            addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                            addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                        }
-                        addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-                    }
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
 		    l_sect = sect;
 		}
 	}
@@ -637,42 +637,42 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-        volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-        volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
-        volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
-        int i;
+	int i;

 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
-             (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+	     (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();

-        for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
-          {
-            addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-            addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-            addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;

-            dest2[i] = data2[i];
+	    dest2[i] = data2[i];

-            /* re-enable interrupts if necessary */
-            if (flag)
-              enable_interrupts();
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();

-            /* data polling for D7 */
-            start = get_timer (0);
-            while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-                   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
-              if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-                return (1);
-              }
-            }
-          }
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }

 	return (0);
 }
@@ -57,16 +57,16 @@
 #define SET_FPGA(data)         out32(GPIO0_OR, data)

 #define FPGA_WRITE_1 {                                                    \
-        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
-        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */

 #define FPGA_WRITE_0 {                                                    \
-        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
-        SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */

 #if 0
 static int fpga_boot (unsigned char *fpgadata, int size)
@@ -9,17 +9,17 @@
 memsetup:
 	/* First setup pll:s to make serial work ok */
 	/* We have a 12 MHz crystal */
-        li              t0, SYS_CPUPLL
-        li              t1, 0x21 /* 396 MHz */
-        sw              t1, 0(t0)
-        sync
-        nop
+	li              t0, SYS_CPUPLL
+	li              t1, 0x21 /* 396 MHz */
+	sw              t1, 0(t0)
+	sync
+	nop

-        /* Setup AUX PLL */
+	/* Setup AUX PLL */
 	li              t0, SYS_AUXPLL
 	li              t1, 8 /* 96 MHz */
-        sw              t1, 0(t0) /* aux pll */
-        sync
+	sw              t1, 0(t0) /* aux pll */
+	sync

 /* SDCS 0,1 SDRAM */
 	li		t0, MEM_SDMODE0
@@ -27,4 +27,3 @@ TEXT_BASE = 0x018c0000
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
 endif
-
@@ -33,17 +33,17 @@ SECTIONS
 	  cpu/nios/start.o (.text)
 	  *(.text)
 	}
-        __text_end = .;
+	__text_end = .;

-        . = ALIGN(4);
-        .rodata :
+	. = ALIGN(4);
+	.rodata :
 	{
 		*(.rodata)
 	}
 	__rodata_end = .;

-        . = ALIGN(4);
-        .data :
+	. = ALIGN(4);
+	.data :
 	{
 		*(.data)
 	}
@@ -59,12 +59,11 @@ SECTIONS
 	__u_boot_cmd_end = .;

 	__bss_start = .;
-        . = ALIGN(4);
-        .bss :
+	. = ALIGN(4);
+	.bss :
 	{
 		*(.bss)
 	}
 	. = ALIGN(4);
 	__bss_end = .;
 }
-
@@ -120,5 +120,3 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 61 */
 	.long	_def_xhandler@h		/* Vector 62 */
 	.long	_def_xhandler@h		/* Vector 63 */
-
-
@@ -64,7 +64,7 @@ long value( lenVal*     plvValue )
 * Returns:      void.
 *****************************************************************************/
 void initLenVal( lenVal*    plv,
-                 long       lValue )
+		 long       lValue )
 {
 	plv->len    = 1;
 	plv->val[0] = (unsigned char)lValue;
@@ -79,8 +79,8 @@ void initLenVal( lenVal*    plv,
 * Returns:      short   - 0 = mismatch; 1 = equal.
 *****************************************************************************/
 short EqualLenVal( lenVal*  plvTdoExpected,
-                   lenVal*  plvTdoCaptured,
-                   lenVal*  plvTdoMask )
+		   lenVal*  plvTdoCaptured,
+		   lenVal*  plvTdoMask )
 {
 	short           sEqual;
 	short           sIndex;
@@ -120,8 +120,8 @@ short EqualLenVal( lenVal*  plvTdoExpected,
 * Returns:      short   - the bit value.
 *****************************************************************************/
 short RetBit( lenVal*   plv,
-              int       iByte,
-              int       iBit )
+	      int       iByte,
+	      int       iBit )
 {
 	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
 	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
@@ -139,9 +139,9 @@ short RetBit( lenVal*   plv,
 * Returns:      void.
 *****************************************************************************/
 void SetBit( lenVal*    plv,
-             int        iByte,
-             int        iBit,
-             short      sVal )
+	     int        iByte,
+	     int        iBit,
+	     short      sVal )
 {
 	unsigned char   ucByteVal;
 	unsigned char   ucBitMask;
@@ -166,8 +166,8 @@ void SetBit( lenVal*    plv,
 * Returns:      void.
 *****************************************************************************/
 void addVal( lenVal*    plvResVal,
-             lenVal*    plvVal1,
-             lenVal*    plvVal2 )
+	     lenVal*    plvVal1,
+	     lenVal*    plvVal2 )
 {
 	unsigned char   ucCarry;
 	unsigned short  usSum;
@@ -204,7 +204,7 @@ void addVal( lenVal*    plvResVal,
 * Returns:      void.
 *****************************************************************************/
 void readVal( lenVal*   plv,
-              short     sNumBytes )
+	      short     sNumBytes )
 {
 	unsigned char*  pucVal;

@@ -114,20 +114,20 @@ extern int filesize;

 #ifdef  DEBUG_MODE
 #define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat ); }
 #define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat, arg1 ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1 ); }
 #define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat, arg1, arg2 ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2 ); }
 #define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat, arg1, arg2, arg3 ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2, arg3 ); }
 #define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    xsvfPrintLenVal(plenVal); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    xsvfPrintLenVal(plenVal); }
 #else   /* !DEBUG_MODE */
 #define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
 #define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
@@ -327,68 +327,68 @@ TXsvfDoCmdFuncPtr   xsvf_pfDoCmd[]  =
 #ifdef  DEBUG_MODE
 char* xsvf_pzCommandName[]  =
 {
-        "XCOMPLETE",
-        "XTDOMASK",
-        "XSIR",
-        "XSDR",
-        "XRUNTEST",
-        "Reserved5",
-        "Reserved6",
-        "XREPEAT",
-        "XSDRSIZE",
-        "XSDRTDO",
-        "XSETSDRMASKS",
-        "XSDRINC",
-        "XSDRB",
-        "XSDRC",
-        "XSDRE",
-        "XSDRTDOB",
-        "XSDRTDOC",
-        "XSDRTDOE",
-        "XSTATE",
-        "XENDIR",
-        "XENDDR",
-        "XSIR2",
-        "XCOMMENT",
-        "XWAIT"
+	"XCOMPLETE",
+	"XTDOMASK",
+	"XSIR",
+	"XSDR",
+	"XRUNTEST",
+	"Reserved5",
+	"Reserved6",
+	"XREPEAT",
+	"XSDRSIZE",
+	"XSDRTDO",
+	"XSETSDRMASKS",
+	"XSDRINC",
+	"XSDRB",
+	"XSDRC",
+	"XSDRE",
+	"XSDRTDOB",
+	"XSDRTDOC",
+	"XSDRTDOE",
+	"XSTATE",
+	"XENDIR",
+	"XENDDR",
+	"XSIR2",
+	"XCOMMENT",
+	"XWAIT"
 };

 char*   xsvf_pzErrorName[]  =
 {
-        "No error",
-        "ERROR:  Unknown",
-        "ERROR:  TDO mismatch",
-        "ERROR:  TDO mismatch and exceeded max retries",
-        "ERROR:  Unsupported XSVF command",
-        "ERROR:  Illegal state specification",
-        "ERROR:  Data overflows allocated MAX_LEN buffer size"
+	"No error",
+	"ERROR:  Unknown",
+	"ERROR:  TDO mismatch",
+	"ERROR:  TDO mismatch and exceeded max retries",
+	"ERROR:  Unsupported XSVF command",
+	"ERROR:  Illegal state specification",
+	"ERROR:  Data overflows allocated MAX_LEN buffer size"
 };

 char*   xsvf_pzTapState[] =
 {
-        "RESET",        /* 0x00 */
-        "RUNTEST/IDLE", /* 0x01 */
-        "DRSELECT",     /* 0x02 */
-        "DRCAPTURE",    /* 0x03 */
-        "DRSHIFT",      /* 0x04 */
-        "DREXIT1",      /* 0x05 */
-        "DRPAUSE",      /* 0x06 */
-        "DREXIT2",      /* 0x07 */
-        "DRUPDATE",     /* 0x08 */
-        "IRSELECT",     /* 0x09 */
-        "IRCAPTURE",    /* 0x0A */
-        "IRSHIFT",      /* 0x0B */
-        "IREXIT1",      /* 0x0C */
-        "IRPAUSE",      /* 0x0D */
-        "IREXIT2",      /* 0x0E */
-        "IRUPDATE"      /* 0x0F */
+	"RESET",        /* 0x00 */
+	"RUNTEST/IDLE", /* 0x01 */
+	"DRSELECT",     /* 0x02 */
+	"DRCAPTURE",    /* 0x03 */
+	"DRSHIFT",      /* 0x04 */
+	"DREXIT1",      /* 0x05 */
+	"DRPAUSE",      /* 0x06 */
+	"DREXIT2",      /* 0x07 */
+	"DRUPDATE",     /* 0x08 */
+	"IRSELECT",     /* 0x09 */
+	"IRCAPTURE",    /* 0x0A */
+	"IRSHIFT",      /* 0x0B */
+	"IREXIT1",      /* 0x0C */
+	"IRPAUSE",      /* 0x0D */
+	"IREXIT2",      /* 0x0E */
+	"IRUPDATE"      /* 0x0F */
 };
 #endif  /* DEBUG_MODE */

-//#ifdef DEBUG_MODE
-//    FILE* in;   /* Legacy DEBUG_MODE file pointer */
+/*#ifdef DEBUG_MODE	*/
+/*    FILE* in;   /XXX* Legacy DEBUG_MODE file pointer */
 int xsvf_iDebugLevel;
-//#endif /* DEBUG_MODE */
+/*#endif /XXX* DEBUG_MODE */

 /*============================================================================
 * Utility Functions
@@ -493,7 +493,7 @@ void xsvfTmsTransition( short sTms )
 * Returns:      int             - 0 = success; otherwise error.
 *****************************************************************************/
 int xsvfGotoTapState( unsigned char*   pucTapState,
-                      unsigned char    ucTargetState )
+		      unsigned char    ucTargetState )
 {
 	int i;
 	int iErrorCode;
@@ -708,9 +708,9 @@ int xsvfGotoTapState( unsigned char*   pucTapState,
 * Returns:      void.
 *****************************************************************************/
 void xsvfShiftOnly( long    lNumBits,
-                    lenVal* plvTdi,
-                    lenVal* plvTdoCaptured,
-                    int     iExitShift )
+		    lenVal* plvTdi,
+		    lenVal* plvTdoCaptured,
+		    int     iExitShift )
 {
 	unsigned char*  pucTdi;
 	unsigned char*  pucTdo;
@@ -796,15 +796,15 @@ void xsvfShiftOnly( long    lNumBits,
 *               is NOT all zeros and sMatch==1.
 *****************************************************************************/
 int xsvfShift( unsigned char*   pucTapState,
-               unsigned char    ucStartState,
-               long             lNumBits,
-               lenVal*          plvTdi,
-               lenVal*          plvTdoCaptured,
-               lenVal*          plvTdoExpected,
-               lenVal*          plvTdoMask,
-               unsigned char    ucEndState,
-               long             lRunTestTime,
-               unsigned char    ucMaxRepeat )
+	       unsigned char    ucStartState,
+	       long             lNumBits,
+	       lenVal*          plvTdi,
+	       lenVal*          plvTdoCaptured,
+	       lenVal*          plvTdoExpected,
+	       lenVal*          plvTdoMask,
+	       unsigned char    ucEndState,
+	       long             lRunTestTime,
+	       unsigned char    ucMaxRepeat )
 {
 	int             iErrorCode;
 	int             iMismatch;
@@ -935,15 +935,15 @@ int xsvfShift( unsigned char*   pucTapState,
 * Returns:      int                 - 0 = success; otherwise TDO mismatch.
 *****************************************************************************/
 int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
-                      long              lShiftLengthBits,
-                      short             sShiftLengthBytes,
-                      lenVal*           plvTdi,
-                      lenVal*           plvTdoCaptured,
-                      lenVal*           plvTdoExpected,
-                      lenVal*           plvTdoMask,
-                      unsigned char     ucEndState,
-                      long              lRunTestTime,
-                      unsigned char     ucMaxRepeat )
+		      long              lShiftLengthBits,
+		      short             sShiftLengthBytes,
+		      lenVal*           plvTdi,
+		      lenVal*           plvTdoCaptured,
+		      lenVal*           plvTdoExpected,
+		      lenVal*           plvTdoMask,
+		      unsigned char     ucEndState,
+		      long              lRunTestTime,
+		      unsigned char     ucMaxRepeat )
 {
 	readVal( plvTdi, sShiftLengthBytes );
 	if ( plvTdoExpected )
@@ -968,9 +968,9 @@ int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
 *****************************************************************************/
 #ifdef  XSVF_SUPPORT_COMPRESSION
 void xsvfDoSDRMasking( lenVal*  plvTdi,
-                       lenVal*  plvNextData,
-                       lenVal*  plvAddressMask,
-                       lenVal*  plvDataMask )
+		       lenVal*  plvNextData,
+		       lenVal*  plvAddressMask,
+		       lenVal*  plvDataMask )
 {
 	int             i;
 	unsigned char   ucTdi;
@@ -1,64 +1,64 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*****************************************************************************
- * File:         micro.h
- * Description:  This header file contains the function prototype to the
- *               primary interface function for the XSVF player.
- * Usage:        FIRST - PORTS.C
- *               Customize the ports.c function implementations to establish
- *               the correct protocol for communicating with your JTAG ports
- *               (setPort() and readTDOBit()) and tune the waitTime() delay
- *               function.  Also, establish access to the XSVF data source
- *               in the readByte() function.
- *               FINALLY - Call xsvfExecute().
- *****************************************************************************/
-#ifndef XSVF_MICRO_H
-#define XSVF_MICRO_H
-
-/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
-#define XSVF_LEGACY_SUCCESS 1
-#define XSVF_LEGACY_ERROR   0
-
-/* 4.04 [NEW] Error codes for xsvfExecute. */
-/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
-#define XSVF_ERROR_NONE         0
-#define XSVF_ERROR_UNKNOWN      1
-#define XSVF_ERROR_TDOMISMATCH  2
-#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
-#define XSVF_ERROR_ILLEGALCMD   4
-#define XSVF_ERROR_ILLEGALSTATE 5
-#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
-/* Insert new errors here */
-#define XSVF_ERROR_LAST         7
-
-/*****************************************************************************
- * Function:     xsvfExecute
- * Description:  Process, interpret, and apply the XSVF commands.
- *               See port.c:readByte for source of XSVF data.
- * Parameters:   none.
- * Returns:      int - For error codes see above.
- *****************************************************************************/
-int xsvfExecute(void);
-
-#endif  /* XSVF_MICRO_H */
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File:         micro.h
+ * Description:  This header file contains the function prototype to the
+ *               primary interface function for the XSVF player.
+ * Usage:        FIRST - PORTS.C
+ *               Customize the ports.c function implementations to establish
+ *               the correct protocol for communicating with your JTAG ports
+ *               (setPort() and readTDOBit()) and tune the waitTime() delay
+ *               function.  Also, establish access to the XSVF data source
+ *               in the readByte() function.
+ *               FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR   0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE         0
+#define XSVF_ERROR_UNKNOWN      1
+#define XSVF_ERROR_TDOMISMATCH  2
+#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD   4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST         7
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif  /* XSVF_MICRO_H */
@@ -97,7 +97,7 @@ int checkboard (void)
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 	unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
-                                   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+				   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
 	unsigned char id1, id2;

 	puts ("Board: ");
@@ -321,8 +321,8 @@ static long int dram_size (long int mamr_value, long int *base,
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
+ 	ulong cnt, val, size;
+ 	ulong save[32];			/* to make test non-destructive */
 	unsigned char i = 0;

 	memctl->memc_mamr = mamr_value;
@@ -341,7 +341,13 @@ static long int dram_size (long int mamr_value, long int *base,

 	/* check at base address */
 	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
 		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
 		return (0);
 	}

@@ -352,7 +358,14 @@ static long int dram_size (long int mamr_value, long int *base,
 		*addr = save[--i];

 		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
 		}
 	}
 	return (maxsize);
@@ -79,7 +79,11 @@ flash_init (void)
 	size_b0 = flash_get_size(CFG_BOOT_FLASH_WIDTH, (vu_long *)base,
 	                         &flash_info[0]);

-	printf("[%ldkB@%lx] ", size_b0/1024, base);
+#ifndef CONFIG_P3G4
+	printf("[");
+	print_size (size_b0, "");
+	printf("@%08lX] ", base);
+#endif

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
@@ -90,7 +94,11 @@ flash_init (void)
 	for(i=1;i<CFG_MAX_FLASH_BANKS;i++) {
 	    unsigned long size = flash_get_size(CFG_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);

-	    printf("[%ldMB@%lx] ", size>>20, base);
+#ifndef CONFIG_P3G4
+	    printf("[");
+	    print_size (size, "");
+	    printf("@%08lX] ", base);
+#endif

 	    if (flash_info[i].flash_id == FLASH_UNKNOWN) {
 		if(i==1) {
@@ -22,10 +22,23 @@
 #

 #
-# IceCube board
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
 #

-TEXT_BASE = 0xfff00000
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
 # TEXT_BASE = 0x00100000
+endif

 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
@@ -123,7 +123,7 @@ static flash_info_t *flash_get_info(ulong base)

 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
-		if (info->size && 
+		if (info->size &&
 			info->start[0] <= base && base <= info->start[0] + info->size - 1)
 			break;
 	}
@@ -260,7 +260,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 	addr2 = (FPW *)((ulong)addr | 0x800000);
 	if (addr2 != addr &&
 		((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
-		/* Seems 2 banks are the same space (8Mb chip is installed, 
+		/* Seems 2 banks are the same space (8Mb chip is installed,
 		 * J24 in default position (CS0)). Disable this (first) bank.
 		 */
 		info->flash_id = FLASH_UNKNOWN;
@@ -134,7 +134,7 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 #endif

-#else
+#else	/* CFG_RAMBOOT */
 #ifdef CONFIG_MGT5100
 	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
@@ -174,9 +174,9 @@ void flash_preinit(void)
 void flash_afterinit(ulong size)
 {
 	if (size == 0x800000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = 
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 			START_REG(CFG_BOOTCS_START | size);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = 
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 			STOP_REG(CFG_BOOTCS_START | size, size);
 	}
 }
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ixdp425.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
@@ -0,0 +1,2 @@
+#TEXT_BASE = 0x00100000
+TEXT_BASE = 0x00f00000
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               		x
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               		__swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/ixp425.h>
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/* local prototypes */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_post_init (void)
+/**********************************************************/
+{
+	return (0);
+}
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = 245;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	return 0;
+}
+
+int
+/**********************************************************/
+dram_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/ixp/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	bss_start = .;
+	.bss : { *(.bss) }
+	bss_end = .;
+
+	armboot_end = .;
+}
@@ -562,13 +562,13 @@ long int initdram(int board_type)
    printf(", Using Bank Based Interleave\n");
 #else
    printf(", Using Page Based Interleave\n");
-#endif    
+#endif
 	printf("\tTotal size: ");

-    /* this delay only needed for original 16MB DIMM... 
+    /* this delay only needed for original 16MB DIMM...
     * Not needed for any other memory configuration */
    if ((sdram_size * chipselects) == (16 *1024 *1024))
-        udelay (250000);
+	udelay (250000);
    return (sdram_size * chipselects);
 	/*return (16 * 1024 * 1024);*/
 }
@@ -584,4 +584,3 @@ void pci_init_board(void)
 	pci_mpc8250_init(&hose);
 }
 #endif
-
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	case FLASH_28F640J3A:   printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+	value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1] & 0x00FF00FF;             /* device ID            */
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case (INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		sector_offset = 0x40000;
+		break;                          /* => 2x8 MB             */
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			asm("sync");
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			asm("sync");
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			asm("sync");
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			asm("sync");
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			asm("sync");
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			    asm("sync");
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if(*addr & 0x00200020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+			asm("sync");
+		}
+	}
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+	asm("sync");
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	asm("sync");
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+	asm("sync");
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+	start = get_timer (0);
+	while((*addr & 0x00800080) != 0x00800080){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if defined(CFG_FLASH_PORT_WIDTH_16)
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+  #if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+  #if defined(CONFIG_RAM_AS_FLASH)
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+  #else
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+  #ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+  #else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,8,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,9,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+	entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+long int fixed_sdram (void);
+
+/* MPC8540ADS Board Status & Control Registers */
+#if 0
+typedef struct bscr_ {
+	unsigned long bcsr0;
+	unsigned long bcsr1;
+	unsigned long bcsr2;
+	unsigned long bcsr3;
+	unsigned long bcsr4;
+	unsigned long bcsr5;
+	unsigned long bcsr6;
+	unsigned long bcsr7;
+} bcsr_t;
+#endif
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Motorola MPC8540ADS Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8540ads/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8540ads/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	case FLASH_28F640J3A:   printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+	value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1] & 0x00FF00FF;             /* device ID            */
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case (INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		sector_offset = 0x40000;
+		break;                          /* => 8 MB             */
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			asm("sync");
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			asm("sync");
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			asm("sync");
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			asm("sync");
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			asm("sync");
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			    asm("sync");
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if(*addr & 0x00200020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+			asm("sync");
+		}
+	}
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+	asm("sync");
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	asm("sync");
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+	asm("sync");
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+	start = get_timer (0);
+	while((*addr & 0x00800080) != 0x00800080){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if defined(CFG_FLASH_PORT_WIDTH_16)
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+  #if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+  #if defined(CONFIG_RAM_AS_FLASH)
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+  #else
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+  #ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+  #else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,8,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,9,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+	entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+	.section .bootpg, "ax"
+	.globl  law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* MPC8560ADS Board Status & Control Registers */
+typedef struct bscr_ {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+} bcsr_t;
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	miiphy_reset(0x0);	/* reset PHY */
+	miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
+	miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Motorola MPC8560ADS Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return ( CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8560ads/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8560ads/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/i2c.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
@@ -86,14 +86,14 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
 * The first thing we do is to map the Flash CS to the Flash area and
 * the MPS CS to the MPS area. Since the flash size is unknown at this
 * point, we use the max flash size and the lowest flash address as base.
- * 
+ *
 * After flash detection we adjust the size of the CS area accordingly.
 * The board_init_r will fill in wrong values in the board init structure,
 * but this will be fixed in the misc_init_r routine:
 * bd->bi_flashstart=0-flash_info[0].size
 * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
 * bd->bi_flashoffset=0
- * 
+ *
 */
 int get_boot_mode(void)
 {
@@ -152,7 +152,6 @@ void setup_cs_reloc(void)
 }


-
 unsigned long flash_init (void)
 {
 	unsigned long size_b0, size_b1,flashcr, size_reg;
@@ -207,7 +206,7 @@ unsigned long flash_init (void)
 		case 32: i=5; break; /* = 32MB */
 		case 64: i=6; break; /* = 64MB */
 		case 128: i=7; break; /*= 128MB */
-		default: 
+		default:
 			printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
 			while(1);
 	}
@@ -345,7 +344,7 @@ void flash_print_info  (flash_info_t *info)


 /*-----------------------------------------------------------------------
- 
+
 */

 /*
@@ -178,4 +178,3 @@ U_BOOT_CMD(
 	"vcma9   - VCMA9 specific commands\n",
 	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory\n"
 );
-
@@ -153,14 +153,14 @@ memsetup:
 	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
 	mov	r4, #SDRAMDATA1_END-SDRAMDATA
 	/* calculate start and end point */
-	mla	r0, r3, r4, r0 
+	mla	r0, r3, r4, r0
 	add     r2, r0, r4
 0:
 	ldr     r3, [r0], #4
 	str     r3, [r1], #4
 	cmp     r2, r0
 	bne     0b
-	
+
 	/* everything is fine now */
 	mov	pc, lr

@@ -194,7 +194,7 @@ SDRAMDATA1_END:
    .word 0x32 + BURST_EN
    .word 0x30
    .word 0x30
-    
+
 /* 2Mx8x4 (not implemented yet) */
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
@@ -202,7 +202,7 @@ SDRAMDATA1_END:
    .word 0x32 + BURST_EN
    .word 0x30
    .word 0x30
-    
+
 /* 4Mx8x2 (not implemented yet) */
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
@@ -190,21 +190,21 @@ nand_init(void)
 static u8 Get_PLD_ID(void)
 {
 	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-	
+
 	return(pld->ID);
 }

 static u8 Get_PLD_BOARD(void)
 {
 	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-	
+
 	return(pld->BOARD);
 }

 static u8 Get_PLD_SDRAM(void)
 {
 	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-	
+
 	return(pld->SDRAM);
 }

@@ -253,7 +253,7 @@ static ulong Get_SDRAM_ChipSize(void)
 		case 2: return  8 * (1024*1024);
 		case 3: return  8 * (1024*1024);
 		default: return 0;
-	}	
+	}
 }
 static const char * Get_SDRAM_ChipGeom(void)
 {
@@ -339,10 +339,10 @@ int overwrite_console(void)
 * Print VCMA9 Info
 ************************************************************************/
 void print_vcma9_info(void)
-{	
+{
 	unsigned char s[50];
 	int i;
-	
+
 	if ((i = getenv_r("serial#", s, 32)) < 0) {
 		puts ("### No HW ID - assuming VCMA9");
 		printf("i %d", i*24);
@@ -54,7 +54,6 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 #define mb() __asm__ __volatile__ ("" : : : "memory")


-
 /* Flash Organization Structure */
 typedef struct OrgDef {
 	unsigned int sector_number;
@@ -240,8 +239,6 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 }


-
-
 /* unprotects a sector for write and erase
 * on some intel parts, this unprotects the entire chip, but it
 * wont hurt to call this additional times per sector...
@@ -298,8 +295,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	}


-
-
 	start = get_timer (0);
 	last = start;

@@ -326,7 +321,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 			while (((status =
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
-					if (get_timer_masked () > 
+					if (get_timer_masked () >
 					CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
@@ -132,8 +132,6 @@ watch2Wait:
 	bne	watch2Wait


-
-
 	/* Set memory timings corresponding to the new clock speed */

 	/* Check execution location to determine current execution location
@@ -275,7 +273,7 @@ REG_ARM_CKCTL:			/* 16 bits */
 REG_ARM_IDLECT3:		/* 16 bits */
 	.word 0xfffece24
 REG_ARM_IDLECT2:		/* 16 bits */
-	.word 0xfffece08        
+	.word 0xfffece08
 REG_ARM_IDLECT1:		/* 16 bits */
 	.word 0xfffece04

@@ -293,7 +291,7 @@ REG_WSPRDOG:
 	.word 0xfffeb048
 /* watchdog write pending */
 REG_WWPSDOG:
-	.word 0xfffeb034 
+	.word 0xfffeb034

 WSPRDOG_VAL1:
 	.word 0x0000aaaa
@@ -342,7 +340,7 @@ REG_WATCHDOG:

 /* 96 MHz Samsung Mobile DDR */
 SDRAM_CONFIG_VAL:
-	.word 0x001200f4 
+	.word 0x001200f4

 DLL_LRD_CONTROL_VAL:
 	.word 0x00800002
@@ -39,11 +39,11 @@ SECTIONS
 	.data : { *(.data) }
 	. = ALIGN(4);
 	.got : { *(.got) }
-	
+
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
-	
+
 	armboot_end_data = .;
 	. = ALIGN(4);
 	.bss : { *(.bss) }
@@ -94,39 +94,41 @@ int checkboard (void)

 long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int size9 ;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;

-    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));

 	/* Refresh clock prescalar */
-    memctl->memc_mptpr = CFG_MPTPR ;
+	memctl->memc_mptpr = CFG_MPTPR;

-    memctl->memc_mar  = 0x00000088;
+	memctl->memc_mar = 0x00000088;

 	/* Map controller banks 1 to the SDRAM bank */
-    memctl->memc_or1 = CFG_OR1_PRELIM;
-    memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;

-    memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */

-    udelay(200);
+	udelay (200);

-    /* perform SDRAM initializsation sequence */
+	/* perform SDRAM initializsation sequence */

-	memctl->memc_mcr  = 0x80002136 ; /* SDRAM bank 0 */
-    udelay(1);
+	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
+	udelay (1);

-    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

-    udelay (1000);
+	udelay (1000);

 	/* Check Bank 0 Memory Size,
 	 * 9 column mode
 	 */

-	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+			   SDRAM_MAX_SIZE);

 	/*
 	 * Final mapping:
@@ -135,7 +137,7 @@ long int initdram (int board_type)
 	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 	udelay (1000);

-    return (size9);
+	return (size9);
 }

 /* ------------------------------------------------------------------------- */
@@ -148,44 +150,58 @@ long int initdram (int board_type)
 * - short between data lines
 */

-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    volatile long int	 *addr;
-    ulong		  cnt, val;
-    ulong		  save[32];	/* to make test non-destructive */
-    unsigned char	  i = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val, size;
+	ulong save[32];		/* to make test non-destructive */
+	unsigned char i = 0;

-    memctl->memc_mamr = mamr_value;
+	memctl->memc_mamr = mamr_value;

-    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
-	addr = base + cnt;	/* pointer arith! */
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */

-	save[i++] = *addr;
-	*addr = ~cnt;
-    }
-
-    /* write 0 to base address */
-    addr = base;
-    save[i] = *addr;
-    *addr = 0;
-
-    /* check at base address */
-    if ((val = *addr) != 0) {
-	*addr = save[i];
-	return (0);
-    }
-
-    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
-	addr = base + cnt;	/* pointer arith! */
-
-	val = *addr;
-	*addr = save[--i];
-
-	if (val != (~cnt)) {
-	    return (cnt * sizeof(long));
+		save[i++] = *addr;
+		*addr = ~cnt;
 	}
-    }
-    return (maxsize);
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
+		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
+		}
+	}
+	return (maxsize);
 }
@@ -533,11 +533,11 @@ int misc_init_r(void)
 	setenv("Daq128xSampling", "1");
    }

-    /* 
-     * Display the ADC/DAC clocking information 
+    /*
+     * Display the ADC/DAC clocking information
     */
    if (!quiet) {
-        Daq_Display_Clocks();
+	Daq_Display_Clocks();
    }

    /*
@@ -572,9 +572,9 @@ int misc_init_r(void)
     * 3) Write the I2C address to register 6
     * 4) Enable address matching by setting the MSB in register 7
     */
-    
+
    if (!quiet) {
-        printf("Initializing the ADC...\n");
+	printf("Initializing the ADC...\n");
    }
    udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */

@@ -720,7 +720,7 @@ int misc_init_r(void)
    I2C_TRISTATE;

    if (!quiet) {
-        printf("\n");
+	printf("\n");
    }

 #ifdef CONFIG_ETHER_LOOPBACK_TEST
@@ -795,14 +795,14 @@ void show_boot_progress (int status)
    if(status > 0) {
 	last_boot_progress = status;
    } else {
-        /* 
+	/*
 	 * If a specific failure code is given, flash this code
 	 * else just use the last success code we've seen
 	 */
 	if(status < -1)
 	    last_boot_progress = -status;
-	
-	/* 
+
+	/*
 	 * Flash this code 5 times
 	 */
 	for(j=0; j<5; j++) {
@@ -813,15 +813,15 @@ void show_boot_progress (int status)
 	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
 	    flash_code(last_boot_progress, 5, 3);

-	    /* 
-	     * Delay 5 seconds between repetitions, 
-	     * with the fault LED blinking 
+	    /*
+	     * Delay 5 seconds between repetitions,
+	     * with the fault LED blinking
 	     */
 	    for(i=0; i<5; i++) {
-	    	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
-	    	udelay(500000);
-	    	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-	    	udelay(500000);
+		status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+		udelay(500000);
+		status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+		udelay(500000);
 	    }
 	}

@@ -92,4 +92,3 @@ void pci_init_board(void)
 {
 	pci_mpc824x_init(&hose);
 }
-
@@ -230,7 +230,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	volatile uint *orx_ptr;
 	int i;
 	ulong save[32];				/* to make test non-destructive */
-	ulong maxsize;
+	ulong maxsize, size;

 	/* We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
@@ -299,7 +299,13 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	*addr = 0;

 	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
 		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
 		return (0);
 	}

@@ -308,10 +314,17 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 		val = *addr;
 		*addr = save[--i];
 		if (val != ~cnt) {
+			size = cnt * sizeof (long);
+			/* Restore the original data before leaving the function.
+			 */ 
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
 			/* Write the actual size to ORx
 			 */
-			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
-			return (cnt * sizeof (long));
+			*orx_ptr = orx | ~(size - 1);
+			return (size);
 		}
 	}
 	return (maxsize);
@@ -328,7 +328,7 @@ long int initdram (int board_type)
 	memctl->memc_br3 = CFG_BR3_CAN;

 	/* Initialize MBMR */
-	memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */

 	/* Initialize UPMB for CAN: single read */
 	memctl->memc_mdr = 0xFFFFC004;
@@ -368,8 +368,8 @@ long int initdram (int board_type)
 	memctl->memc_or5 = CFG_OR5_ISP1362;
 	memctl->memc_br5 = CFG_BR5_ISP1362;
 #endif							/* CONFIG_ISP1362_USB */
-	    
-	    
+
+
 	return (size_b0 + size_b1);
 }

@@ -389,8 +389,8 @@ static long int dram_size (long int mamr_value, long int *base,
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];				/* to make test non-destructive */
+	ulong cnt, val, size;
+	ulong save[32];			/* to make test non-destructive */
 	unsigned char i = 0;

 	memctl->memc_mamr = mamr_value;
@@ -409,7 +409,13 @@ static long int dram_size (long int mamr_value, long int *base,

 	/* check at base address */
 	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
 		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
+			addr  = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
 		return (0);
 	}

@@ -420,7 +426,14 @@ static long int dram_size (long int mamr_value, long int *base,
 		*addr = save[--i];

 		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+				addr  = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
 		}
 	}
 	return (maxsize);
@@ -204,9 +204,35 @@ extern int flash_write (uchar *, ulong, ulong);
 extern int i2c_write_multiple (uchar, uint, int, void *, int);
 extern int i2c_read_multiple (uchar, uint, int, void *, int);
 extern block_dev_desc_t *get_dev (char*, int);
+extern int u_boot_hush_start(void);

 int
-au_check_valid(int idx, long nbytes)
+au_check_cksum_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size)))
+	{
+		printf ("Image %s bad total SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+		!= checksum)
+	{
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int
+au_check_header_valid(int idx, long nbytes)
 {
 	image_header_t *hdr;
 	unsigned long checksum;
@@ -221,11 +247,14 @@ au_check_valid(int idx, long nbytes)
 	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
 	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
 #endif
-	if (ntohl(hdr->ih_magic) != IH_MAGIC ||
-	    hdr->ih_arch != IH_CPU_ARM ||
-	    nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size)))
+	if (nbytes < sizeof(*hdr))
 	{
-		printf ("Image %s bad MAGIC or ARCH or SIZE\n", aufile[idx]);
+		printf ("Image %s bad header SIZE\n", aufile[idx]);
+		return -1;
+	}
+	if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_ARM)
+	{
+		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
 		return -1;
 	}
 	/* check the hdr CRC */
@@ -237,15 +266,6 @@ au_check_valid(int idx, long nbytes)
 		return -1;
 	}
 	hdr->ih_hcrc = htonl(checksum);
-	/* check the data CRC */
-	checksum = ntohl(hdr->ih_dcrc);
-
-	if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
-		!= checksum)
-	{
-		printf ("Image %s bad data checksum\n", aufile[idx]);
-		return -1;
-	}
 	/* check the type - could do this all in one gigantic if() */
 	if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
 		printf ("Image %s wrong type\n", aufile[idx]);
@@ -259,7 +279,8 @@ au_check_valid(int idx, long nbytes)
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
-	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK)) {
+	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK) 
+            && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
@@ -351,8 +372,12 @@ au_do_update(int idx, long sz)
 	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
 	flash_sect_erase(start, end);
 	wait_ms(100);
-	/* strip the header - except for the kernel and app */
-	if (idx == IDX_FIRMWARE || idx == IDX_DISK) {
+	/* strip the header - except for the kernel and ramdisk */
+	if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	} else {
 		addr = (char *)((char *)hdr + sizeof(*hdr));
 #ifdef AU_UPDATE_TEST
 		/* copy it to where Linux goes */
@@ -361,10 +386,6 @@ au_do_update(int idx, long sz)
 #endif
 		off = 0;
 		nbytes = ntohl(hdr->ih_size);
-	} else {
-		addr = (char *)hdr;
-		off = sizeof(*hdr);
-		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
 	}

 	/* copy the data from RAM to FLASH */
@@ -538,12 +559,26 @@ do_auto_update(void)
 		aufl_layout[3].start = start;
 		aufl_layout[3].end = end;
 	}
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
 	/* make sure that we see CTRL-C and save the old state */
 	old_ctrlc = disable_ctrlc(0);

 	bitmap_first = 0;
 	/* just loop thru all the possible files */
 	for (i = 0; i < AU_MAXFILES; i++) {
+		/* just read the header */
+		sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t));
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz < sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_header_valid(i, sz) < 0) {
+			debug ("%s header not valid\n", aufile[i]);
+			continue;
+		}
 		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
 		debug ("read %s sz %ld hdr %d\n",
 			aufile[i], sz, sizeof(image_header_t));
@@ -551,8 +586,8 @@ do_auto_update(void)
 			debug ("%s not found\n", aufile[i]);
 			continue;
 		}
-		if (au_check_valid(i, sz) < 0) {
-			debug ("%s not valid\n", aufile[i]);
+		if (au_check_cksum_valid(i, sz) < 0) {
+			debug ("%s checksum not valid\n", aufile[i]);
 			continue;
 		}
 #ifdef CONFIG_VFD
@@ -39,7 +39,10 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 #define CMD_PROGRAM		0x00A000A0
 #define CMD_UNLOCK_BYPASS	0x00200020
 #define CMD_READ_MANF_ID	0x00900090
+#define CMD_UNLOCK_BYPASS_RES1	0x00900090
+#define CMD_UNLOCK_BYPASS_RES2	0x00000000

+#define MEM_FLASH_ADDR		(*(volatile u32 *)CFG_FLASH_BASE)
 #define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
 #define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))

@@ -331,9 +334,6 @@ volatile static int write_word (flash_info_t * info, ulong dest,
 #endif
 	iflag = disable_interrupts ();

-	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
 	*addr = CMD_PROGRAM;
 	*addr = data;

@@ -402,6 +402,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	int l;
 	int i, rc;

+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+
 	wp = (addr & ~3);	/* get lower word aligned address */

 	/*
@@ -422,7 +426,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 		}

 		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
+			goto Done;
 		}
 		wp += 4;
 	}
@@ -441,7 +445,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 		}

 		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
+			goto Done;
 		}
 		src += 4;
 		wp += 4;
@@ -449,7 +453,8 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	}

 	if (cnt == 0) {
-		return ERR_OK;
+		rc = ERR_OK;
+		goto Done;
 	}

 	/*
@@ -464,7 +469,14 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 		data = (data >> 8) | (*(uchar *) cp << 24);
 	}

-	return write_word (info, wp, data);
+	rc = write_word (info, wp, data);
+
+	Done:
+
+	MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1;
+	MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2;
+
+	return (rc);
 }

 /*-----------------------------------------------------------------------
@@ -48,29 +48,29 @@
 #define BWSCON 0x14000000

 /* Bank0 */
-#define B0_Tacs	0x0	/* 0 clk */
-#define B0_Tcos	0x0	/* 0 clk */
-#define B0_Tacc	0x7	/* 14 clk */
-#define B0_Tcoh	0x0	/* 0 clk */
-#define B0_Tah	0x0	/* 0 clk */
+#define B0_Tacs	0x1	/* 1 clk */
+#define B0_Tcos	0x1	/* 1 clk */
+#define B0_Tacc	0x5	/* 8 clk */
+#define B0_Tcoh	0x1	/* 1 clk */
+#define B0_Tah	0x1	/* 1 clk */
 #define B0_Tacp	0x0
 #define B0_PMC	0x0	/* normal */

 /* Bank1 - SRAM */
-#define B1_Tacs	0x0	/* 0 clk */
-#define B1_Tcos	0x0	/* 0 clk */
-#define B1_Tacc	0x7	/* 14 clk */
-#define B1_Tcoh	0x0	/* 0 clk */
-#define B1_Tah	0x0	/* 0 clk */
+#define B1_Tacs	0x1	/* 1 clk */
+#define B1_Tcos	0x1	/* 1 clk */
+#define B1_Tacc	0x5	/* 8 clk */
+#define B1_Tcoh	0x1	/* 1 clk */
+#define B1_Tah	0x1	/* 1 clk */
 #define B1_Tacp	0x0
 #define B1_PMC	0x0	/* normal */

 /* Bank2 - CPLD */
-#define B2_Tacs	0x0	/* 0 clk */
-#define B2_Tcos	0x4	/* 4 clk */
-#define B2_Tacc	0x7	/* 14 clk */
-#define B2_Tcoh	0x4	/* 4 clk */
-#define B2_Tah	0x0	/* 0 clk */
+#define B2_Tacs	0x1	/* 1 clk */
+#define B2_Tcos	0x1	/* 1 clk */
+#define B2_Tacc	0x5	/* 8 clk */
+#define B2_Tcoh	0x1	/* 1 clk */
+#define B2_Tah	0x1	/* 1 clk */
 #define B2_Tacp	0x0
 #define B2_PMC	0x0	/* normal */

@@ -885,7 +885,6 @@ int do_thermo (char **argv)
 }


-
 int do_touch (char **argv)
 {
 	int     x, y;
@@ -1039,7 +1038,6 @@ static void touch_read_x_y (int *px, int *py)
 }


-
 int do_rs485 (char **argv)
 {
 	int timeout;
@@ -38,7 +38,7 @@ void spi_init(void)
 	int i;

 	/* Configure I/O ports. */
- 	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
 	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
 	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
 	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
@@ -48,7 +48,7 @@ void spi_init(void)
 	spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
 	spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
 	spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
-                                    CPHA=1 */
+				    CPHA=1 */

 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
@@ -73,7 +73,7 @@ void tsc2000_write(unsigned short reg, unsigned short data)

 	SET_CS_TOUCH();
 	command = reg;
-        spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
 	spi->ch[0].SPTDAT = (command & 0x00FF);
 	spi_wait_transmit_done();
@@ -94,12 +94,12 @@ unsigned short tsc2000_read (unsigned short reg)
 	SET_CS_TOUCH();
 	command = 0x8000 | reg;

-        spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
 	spi->ch[0].SPTDAT = (command & 0x00FF);
 	spi_wait_transmit_done();

-        spi->ch[0].SPTDAT = 0xFF;
+	spi->ch[0].SPTDAT = 0xFF;
 	spi_wait_transmit_done();
 	data = spi->ch[0].SPRDAT;
 	spi->ch[0].SPTDAT = 0xFF;
@@ -112,7 +112,7 @@ unsigned short tsc2000_read (unsigned short reg)

 void tsc2000_set_mux (unsigned int channel)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

 	CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
 	CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
@@ -189,7 +189,7 @@ void tsc2000_set_mux (unsigned int channel)

 void tsc2000_set_range (unsigned int range)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

 	switch (range) {
 	case 1:
@@ -216,8 +216,8 @@ u16 tsc2000_read_channel (unsigned int channel)
 	udelay(3 * TSC2000_DELAY_BASE);

 	tsc2000_write(TSC2000_REG_ADC, 0x2036);
-        adc_wait_conversion_done ();
-        res = tsc2000_read(TSC2000_REG_AUX1);
+	adc_wait_conversion_done ();
+	res = tsc2000_read(TSC2000_REG_AUX1);
 	return res;
 }

@@ -225,36 +225,36 @@ u16 tsc2000_read_channel (unsigned int channel)
 s32 tsc2000_contact_temp (void)
 {
 	long adc_pt1000, offset;
-        long u_pt1000;
+	long u_pt1000;
 	long contact_temp;


-        tsc2000_reg_init ();
+	tsc2000_reg_init ();
 	tsc2000_set_range (3);

-        adc_pt1000 = tsc2000_read_channel (14);
-        debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+	adc_pt1000 = tsc2000_read_channel (14);
+	debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);

-        offset = tsc2000_read_channel (15);
-        debug ("read channel 15 (offset): %ld\n", offset);
+	offset = tsc2000_read_channel (15);
+	debug ("read channel 15 (offset): %ld\n", offset);

-        /*
-         * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
-         * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
-         * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
-         * error correction Values err_vref and err_amp3 are assumed as 0 in
-         * u-boot, because this could cause only a very small error (< 1%).
-         */
-        u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
-        debug ("u_pt1000: %ld\n", u_pt1000);
+	/*
+	 * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+	 * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+	 * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+	 * error correction Values err_vref and err_amp3 are assumed as 0 in
+	 * u-boot, because this could cause only a very small error (< 1%).
+	 */
+	u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+	debug ("u_pt1000: %ld\n", u_pt1000);

-        if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
-                                &contact_temp) == -1) {
-                printf ("%s: error interpolating PT1000 vlaue\n",
-                         __FUNCTION__);
-                return (-1000);
-        }
-        debug ("contact_temp: %ld\n", contact_temp);
+	if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+				&contact_temp) == -1) {
+		printf ("%s: error interpolating PT1000 vlaue\n",
+			 __FUNCTION__);
+		return (-1000);
+	}
+	debug ("contact_temp: %ld\n", contact_temp);

 	return contact_temp;
 }
@@ -262,7 +262,7 @@ s32 tsc2000_contact_temp (void)

 void tsc2000_reg_init (void)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

 	tsc2000_write(TSC2000_REG_ADC, 0x2036);
 	tsc2000_write(TSC2000_REG_REF, 0x0011);
@@ -315,5 +315,5 @@ int tsc2000_interpolate(long value, long data[][2], long *result)

 void adc_wait_conversion_done(void)
 {
-        while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+	while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
 }
@@ -112,7 +112,7 @@
 #define TSC2000_NO_SENSOR	-0x10000

 #define ERROR_BATTERY   220     /* must be adjusted, if R68 is changed on
-                                 * TRAB */
+				 * TRAB */

 void tsc2000_write(unsigned short, unsigned short);
 unsigned short tsc2000_read (unsigned short);
@@ -55,7 +55,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_num ("flashoffset",   bd->bi_flashoffset	);
 	print_num ("sramstart",	    bd->bi_sramstart	);
 	print_num ("sramsize",	    bd->bi_sramsize	);
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_E500)
 	print_num ("immr_base",	    bd->bi_immr_base	);
 #endif
 	print_num ("bootflags",	    bd->bi_bootflags	);
@@ -66,13 +66,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_str ("pci_busfreq",	    strmhz(buf, bd->bi_pci_busfreq));
 #endif
 #else	/* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
 	print_str ("vco",	    strmhz(buf, bd->bi_vco));
 	print_str ("sccfreq",	    strmhz(buf, bd->bi_sccfreq));
 	print_str ("brgfreq",	    strmhz(buf, bd->bi_brgfreq));
 #endif
 	print_str ("intfreq",	    strmhz(buf, bd->bi_intfreq));
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
 	print_str ("cpmfreq",	    strmhz(buf, bd->bi_cpmfreq));
 #endif
 	print_str ("busfreq",	    strmhz(buf, bd->bi_busfreq));
@@ -81,12 +81,19 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
-#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB)
+#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
+    || (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
 	printf ("\neth1addr    =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
 	}
 #endif /* CONFIG_PN62 */
+#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
+       printf ("\neth2addr    =");
+       for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
+	}
+#endif
 #ifdef CONFIG_HERMES
 	print_str ("ethspeed",	    strmhz(buf, bd->bi_ethspeed));
 #endif
@@ -117,6 +117,9 @@ static boot_os_Fcn do_bootm_linux;
 #else
 extern boot_os_Fcn do_bootm_linux;
 #endif
+#ifdef CONFIG_SILENT_CONSOLE
+static void fixup_silent_linux (void);
+#endif
 static boot_os_Fcn do_bootm_netbsd;
 static boot_os_Fcn do_bootm_rtems;
 #if (CONFIG_COMMANDS & CFG_CMD_ELF)
@@ -146,7 +149,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	uint	unc_len = 0x400000;
 	int	i, verify;
 	char	*name, *s;
-	int	(*appl)(cmd_tbl_t *, int, int, char *[]);
+	int	(*appl)(int, char *[]);
 	image_header_t *hdr = &header;

 	s = getenv ("verify");
@@ -202,7 +205,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	SHOW_BOOT_PROGRESS (3);

 	/* for multi-file images we need the data part, too */
-	print_image_hdr (hdr);
+	print_image_hdr ((image_header_t *)addr);

 	data = addr + sizeof(image_header_t);
 	len  = ntohl(hdr->ih_size);
@@ -248,21 +251,24 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	SHOW_BOOT_PROGRESS (5);

 	switch (hdr->ih_type) {
-	case IH_TYPE_STANDALONE:	name = "Standalone Application";
-					/* A second argument overwrites the load address */
-					if (argc > 2) {
-						hdr->ih_load = simple_strtoul(argv[2], NULL, 16);
-					}
-					break;
-	case IH_TYPE_KERNEL:		name = "Kernel Image";
-					break;
-	case IH_TYPE_MULTI:		name = "Multi-File Image";
-					len  = ntohl(len_ptr[0]);
-					/* OS kernel is always the first image */
-					data += 8; /* kernel_len + terminator */
-					for (i=1; len_ptr[i]; ++i)
-						data += 4;
-					break;
+	case IH_TYPE_STANDALONE:
+		name = "Standalone Application";
+		/* A second argument overwrites the load address */
+		if (argc > 2) {
+			hdr->ih_load = simple_strtoul(argv[2], NULL, 16);
+		}
+		break;
+	case IH_TYPE_KERNEL:
+		name = "Kernel Image";
+		break;
+	case IH_TYPE_MULTI:	
+		name = "Multi-File Image";
+		len  = ntohl(len_ptr[0]);
+		/* OS kernel is always the first image */
+		data += 8; /* kernel_len + terminator */
+		for (i=1; len_ptr[i]; ++i)
+			data += 4;
+		break;
 	default: printf ("Wrong Image Type for %s command\n", cmdtp->name);
 		SHOW_BOOT_PROGRESS (-5);
 		return 1;
@@ -359,8 +365,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			setenv("filesize", buf);
 			return 0;
 		}
-		appl = (int (*)(cmd_tbl_t *, int, int, char *[]))ntohl(hdr->ih_ep);
-		(*appl)(cmdtp, flag, argc-1, &argv[1]);
+		appl = (int (*)(int, char *[]))ntohl(hdr->ih_ep);
+		(*appl)(argc-1, &argv[1]);
 		return 0;
 	case IH_TYPE_KERNEL:
 	case IH_TYPE_MULTI:
@@ -378,6 +384,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	switch (hdr->ih_os) {
 	default:			/* handled by (original) Linux case */
 	case IH_OS_LINUX:
+#ifdef CONFIG_SILENT_CONSOLE
+	    fixup_silent_linux();
+#endif
 	    do_bootm_linux  (cmdtp, flag, argc, argv,
 			     addr, len_ptr, verify);
 	    break;
@@ -432,6 +441,40 @@ U_BOOT_CMD(
 	"        'arg' can be the address of an initrd image\n"
 );

+#ifdef CONFIG_SILENT_CONSOLE
+static void
+fixup_silent_linux ()
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	char buf[256], *start, *end;
+	char *cmdline = getenv ("bootargs");
+
+	/* Only fix cmdline when requested */
+	if (!(gd->flags & GD_FLG_SILENT))
+		return;
+
+	debug ("before silent fix-up: %s\n", cmdline);
+	if (cmdline) {
+		if ((start = strstr (cmdline, "console=")) != NULL) {
+			end = strchr (start, ' ');
+			strncpy (buf, cmdline, (start - cmdline + 8));
+			if (end)
+				strcpy (buf + (start - cmdline + 8), end);
+			else
+				buf[start - cmdline + 8] = '\0';
+		} else {
+			strcpy (buf, cmdline);
+			strcat (buf, " console=");
+		}
+	} else {
+		strcpy (buf, "console=");
+	}
+
+	setenv ("bootargs", buf);
+	debug ("after silent fix-up: %s\n", buf);
+}
+#endif /* CONFIG_SILENT_CONSOLE */
+
 #ifdef CONFIG_PPC
 static void
 do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
@@ -518,16 +561,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		/* convert all clock information to MHz */
 		kbd->bi_intfreq /= 1000000L;
 		kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
 		kbd->bi_cpmfreq /= 1000000L;
 		kbd->bi_brgfreq /= 1000000L;
 		kbd->bi_sccfreq /= 1000000L;
 		kbd->bi_vco     /= 1000000L;
 #endif /* CONFIG_8260 */
-#if defined(CONFIG_MPC5XXXX)
+#if defined(CONFIG_MPC5XXX)
 		kbd->bi_ipbfreq /= 1000000L;
 		kbd->bi_pcifreq /= 1000000L;
-#endif /* CONFIG_MPC5XXXX */
+#endif /* CONFIG_MPC5XXX */
 	}

 	kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep;
@@ -718,7 +761,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,

 	SHOW_BOOT_PROGRESS (15);

-#ifdef CFG_INIT_RAM_LOCK
+#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
 	unlock_ram_in_cache();
 #endif
 	/*
@@ -1013,7 +1056,7 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	flash_info_t *info;
 	int i, j;
 	image_header_t *hdr;
-	ulong checksum;
+	ulong data, len, checksum;

 	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
 		if (info->flash_id == FLASH_UNKNOWN)
@@ -1036,7 +1079,15 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

 			printf ("Image at %08lX:\n", (ulong)hdr);
 			print_image_hdr( hdr );
-			putc ('\n');
+
+			data = (ulong)hdr + sizeof(image_header_t);
+			len  = ntohl(hdr->ih_size);
+
+			printf ("   Verifying Checksum ... ");
+			if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+				printf ("   Bad Data CRC\n");
+			}
+			printf ("OK\n");
 next_sector:		;
 		}
 next_bank:	;
@@ -1301,4 +1352,3 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag,
 }

 #endif /* CONFIG_LYNXKDI */
-
@@ -37,8 +37,6 @@
 #include <fat.h>


-
-
 block_dev_desc_t *get_dev (char* ifname, int dev)
 {
 #if (CONFIG_COMMANDS & CFG_CMD_IDE)
@@ -121,8 +119,6 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }


-
-
 U_BOOT_CMD(
 	fatload,	6,	0,	do_fat_fsload,
 	"fatload - load binary file from a dos filesystem\n",
@@ -164,6 +164,11 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
 			sect = s_last[bank];
 			addr_first = (sect == s_end) ? b_end + 1: info->start[sect + 1];
 			(*s_count) += s_last[bank] - s_first[bank] + 1;
+		} else if (s_last[bank] >= 0) {
+			printf("Error: cannot span across banks when they are"
+			       " mapped in reverse order\n");
+			rcode = 1;
+			break;
 		}
 	}

@@ -631,6 +631,7 @@ void ide_init (void)
 #ifdef CONFIG_IDE_LED
 		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
 #endif
+		ide_dev_desc[i].type=DEV_TYPE_UNKNOWN;
 		ide_dev_desc[i].if_type=IF_TYPE_IDE;
 		ide_dev_desc[i].dev=i;
 		ide_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
@@ -991,11 +992,9 @@ static void ide_ident (block_dev_desc_t *dev_desc)
 		if (retries == 0) {
 			do_retry = 1;
 		} else {
-			dev_desc->type=DEV_TYPE_UNKNOWN;
 			return;
 		}
 #else
-		dev_desc->type=DEV_TYPE_UNKNOWN;
 		return;
 #endif	/* CONFIG_AMIGAONEG3SE */
 	}
@@ -160,7 +160,7 @@ int pcmcia_on (void)
 }
 #else

-#if defined(CONFIG_LWMON)
+#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
 #else
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(2) | PCMCIA_SST(4) | PCMCIA_SL(9))
@@ -594,8 +594,8 @@ static int hardware_enable(int slot)
 	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */

 	/* clear interrupt state, and disable interrupts */
-	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
-	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+	pcmp->pcmc_pscr =  PCMCIA_MASK(slot);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(slot);

 	/*
 	 * Disable interrupts, DMA, and PCMCIA buffers
@@ -604,10 +604,13 @@ static int hardware_enable(int slot)
 	debug ("Disable PCMCIA buffers and assert RESET\n");
 	reg  = 0;
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);

+#ifndef CONFIG_NSCU
 	/*
 	 * Configure Port C pins for
 	 * 5 Volts Enable and 3 Volts enable
@@ -617,6 +620,7 @@ static int hardware_enable(int slot)
 	/* remove all power */

 	immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
+#endif

 	/*
 	 * Make sure there is a card in the slot, then configure the interface.
@@ -639,6 +643,7 @@ static int hardware_enable(int slot)
 		reg,
 		(reg&PCMCIA_VS1(slot))?"n":"ff",
 		(reg&PCMCIA_VS2(slot))?"n":"ff");
+#ifndef CONFIG_NSCU
 	if ((reg & mask) == mask) {
 		immap->im_ioport.iop_pcdat |= 0x0004;
 		puts (" 5.0V card found: ");
@@ -647,6 +652,13 @@ static int hardware_enable(int slot)
 		puts (" 3.3V card found: ");
 	}
 	immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+#else
+	if ((reg & mask) == mask) {
+		puts (" 5.0V card found: ");
+	} else {
+		puts (" 3.3V card found: ");
+	}
+#endif
 #if 0
 	/*  VCC switch error flag, PCMCIA slot INPACK_ pin */
 	cp->cp_pbdir &= ~(0x0020 | 0x0010);
@@ -655,10 +667,14 @@ static int hardware_enable(int slot)
 #endif
 	udelay(1000);
 	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
+	reg  =  PCMCIA_PGCRX(slot);
 	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#else
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+#endif
+	PCMCIA_PGCRX(slot) = reg;

 	udelay(250000);	/* some cards need >150 ms to come up :-( */

@@ -680,14 +696,18 @@ static int hardware_disable(int slot)
 	immap = (immap_t *)CFG_IMMR;
 	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));

+#ifndef CONFIG_NSCU
 	/* remove all power */
 	immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
+#endif

 	debug ("Disable PCMCIA buffers and assert RESET\n");
 	reg  = 0;
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#endif
+	PCMCIA_PGCRX(slot) = reg;

 	udelay(10000);

@@ -695,7 +715,12 @@ static int hardware_disable(int slot)
 }
 #endif	/* CFG_CMD_PCMCIA */

-
+#ifdef CONFIG_NSCU
+static int voltage_set(int slot, int vcc, int vpp)
+{
+	return 0;
+}
+#else
 static int voltage_set(int slot, int vcc, int vpp)
 {
 	volatile immap_t	*immap;
@@ -714,10 +739,14 @@ static int voltage_set(int slot, int vcc, int vpp)
 	 * and assert RESET signal
 	 */
 	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = PCMCIA_PGCRX(_slot_);
+	reg  = PCMCIA_PGCRX(slot);
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#else
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);

 	/*
@@ -755,16 +784,21 @@ static int voltage_set(int slot, int vcc, int vpp)

 done:
 	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
+	reg  =  PCMCIA_PGCRX(slot);
 	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#else
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);

 	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
 		slot+'A');
 	return (0);
 }
+#endif

 #endif	/* TQM8xxL */

@@ -90,8 +90,6 @@ int trab_vfd (ulong bitmap)
 		}
 		break;
 	case VFD_REMOTE_LOGO_BMPNR:
-		transfer_pic(3, &vfd_remote_logo_bitmap[0],
-			VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
 		if ((s = getenv ("bitmap1")) != NULL) {
 			addr = (uchar *)simple_strtoul (s, NULL, 16);
 		} else {
@@ -365,10 +365,16 @@ int console_init_f (void)
 	DECLARE_GLOBAL_DATA_PTR;

 	gd->have_console = 1;
+
+#ifdef CONFIG_SILENT_CONSOLE
+	if (getenv("silent") != NULL)
+		gd->flags |= GD_FLG_SILENT;
+#endif
+
 	return (0);
 }

-#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN)
+#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN) || defined(CONFIG_SILENT_CONSOLE)
 /* search a device */
 device_t *search_device (int flags, char *name)
 {
@@ -489,11 +495,17 @@ int console_init_r (void)

 #ifdef CONFIG_SPLASH_SCREEN
 	/* suppress all output if splash screen is enabled and we have
-           a bmp to display                                            */
+	   a bmp to display                                            */
 	if (getenv("splashimage") != NULL)
 		outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
 #endif

+#ifdef CONFIG_SILENT_CONSOLE
+	/* Suppress all output if "silent" mode requested		*/
+	if (gd->flags & GD_FLG_SILENT)
+		outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+#endif
+
 	/* Scan devices looking for input and output devices */
 	for (i = 1;
 	     (i <= items) && ((inputdev == NULL) || (outputdev == NULL));
@@ -313,7 +313,7 @@ struct variables *top_vars = &shell_ver;
 #else
 static int flag_repeat = 0;
 static int do_repeat = 0;
-static struct variables *top_vars ;
+static struct variables *top_vars = NULL ;
 #endif /*__U_BOOT__ */

 #define B_CHUNK (100)
@@ -3194,13 +3194,15 @@ static void u_boot_hush_reloc(void)

 int u_boot_hush_start(void)
 {
-	top_vars = malloc(sizeof(struct variables));
-	top_vars->name = "HUSH_VERSION";
-	top_vars->value = "0.01";
-	top_vars->next = 0;
-	top_vars->flg_export = 0;
-	top_vars->flg_read_only = 1;
-	u_boot_hush_reloc();
+	if (top_vars == NULL) {
+		top_vars = malloc(sizeof(struct variables));
+		top_vars->name = "HUSH_VERSION";
+		top_vars->value = "0.01";
+		top_vars->next = 0;
+		top_vars->flg_export = 0;
+		top_vars->flg_read_only = 1;
+		u_boot_hush_reloc();
+	}
 	return 0;
 }

@@ -67,4 +67,3 @@ void lynxkdi_boot ( image_header_t *hdr )
 #endif

 #endif	/* CONFIG_LYNXKDI */
-
@@ -102,6 +102,18 @@ static __inline__ int abortboot(int bootdelay)
 	u_int presskey_max = 0;
 	u_int i;

+#ifdef CONFIG_SILENT_CONSOLE
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		if (gd->flags & GD_FLG_SILENT) {
+			/* Restore serial console */
+			console_assign (stdout, "serial");
+			console_assign (stderr, "serial");
+		}
+	}
+#endif
+
 #  ifdef CONFIG_AUTOBOOT_PROMPT
 	printf (CONFIG_AUTOBOOT_PROMPT, bootdelay);
 #  endif
@@ -180,6 +192,21 @@ static __inline__ int abortboot(int bootdelay)
 		printf("key timeout\n");
 #  endif

+#ifdef CONFIG_SILENT_CONSOLE
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		if (abort) {
+			/* permanently enable normal console output */
+			gd->flags &= ~(GD_FLG_SILENT);
+		} else if (gd->flags & GD_FLG_SILENT) {
+			/* Restore silent console */
+			console_assign (stdout, "nulldev");
+			console_assign (stderr, "nulldev");
+		}
+	}
+#endif
+
 	return abort;
 }

@@ -193,6 +220,18 @@ static __inline__ int abortboot(int bootdelay)
 {
 	int abort = 0;

+#ifdef CONFIG_SILENT_CONSOLE
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		if (gd->flags & GD_FLG_SILENT) {
+			/* Restore serial console */
+			console_assign (stdout, "serial");
+			console_assign (stderr, "serial");
+		}
+	}
+#endif
+
 #ifdef CONFIG_MENUPROMPT
 	printf(CONFIG_MENUPROMPT, bootdelay);
 #else
@@ -207,13 +246,13 @@ static __inline__ int abortboot(int bootdelay)
 	if (bootdelay >= 0) {
 		if (tstc()) {	/* we got a key press	*/
 			(void) getc();  /* consume input	*/
-			printf ("\b\b\b 0\n");
-			return 1; 	/* don't auto boot	*/
+			printf ("\b\b\b 0");
+			abort = 1; 	/* don't auto boot	*/
 		}
 	}
 #endif

-	while (bootdelay > 0) {
+	while ((bootdelay > 0) && (!abort)) {
 		int i;

 		--bootdelay;
@@ -237,6 +276,21 @@ static __inline__ int abortboot(int bootdelay)

 	putc ('\n');

+#ifdef CONFIG_SILENT_CONSOLE
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		if (abort) {
+			/* permanently enable normal console output */
+			gd->flags &= ~(GD_FLG_SILENT);
+		} else if (gd->flags & GD_FLG_SILENT) {
+			/* Restore silent console */
+			console_assign (stdout, "nulldev");
+			console_assign (stderr, "nulldev");
+		}
+	}
+#endif
+
 	return abort;
 }
 # endif	/* CONFIG_AUTOBOOT_KEYED */
@@ -21,7 +21,6 @@
 # MA 02111-1307 USA
 #

-PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi

 PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring
-##PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring
@@ -157,14 +157,14 @@ static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffe

 	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
 			str,
-		 	sohci_get_current_frame_number (dev),
-		 	usb_pipedevice (pipe),
-		 	usb_pipeendpoint (pipe),
-		 	usb_pipeout (pipe)? 'O': 'I',
-		 	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
-		 		(usb_pipecontrol (pipe)? "CTRL": "BULK"),
-		 	purb->actual_length,
-		 	transfer_len, dev->status);
+			sohci_get_current_frame_number (dev),
+			usb_pipedevice (pipe),
+			usb_pipeendpoint (pipe),
+			usb_pipeout (pipe)? 'O': 'I',
+			usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+				(usb_pipecontrol (pipe)? "CTRL": "BULK"),
+			purb->actual_length,
+			transfer_len, dev->status);
 #ifdef	OHCI_VERBOSE_DEBUG
 	if (!small) {
 		int i, len;
@@ -585,7 +585,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)

 	if (ed->state == ED_NEW) {
 		ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
-  		/* dummy td; end of td list for ed */
+		/* dummy td; end of td list for ed */
 		td = td_alloc (usb_dev);
 		ed->hwTailP = m32_swap (td);
 		ed->hwHeadP = ed->hwTailP;
@@ -669,13 +669,13 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
 	void *data;
 	int cnt = 0;
 	__u32 info = 0;
-  	unsigned int toggle = 0;
+	unsigned int toggle = 0;

 	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
-  	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-  		toggle = TD_T_TOGGLE;
+	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+		toggle = TD_T_TOGGLE;
 	} else {
-  		toggle = TD_T_DATA0;
+		toggle = TD_T_DATA0;
 		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
 	}
 	urb->td_cnt = 0;
@@ -731,11 +731,11 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
 static void dl_transfer_length(td_t * td)
 {
 	__u32 tdINFO, tdBE, tdCBP;
- 	urb_priv_t *lurb_priv = &urb_priv;
+	urb_priv_t *lurb_priv = &urb_priv;

 	tdINFO = m32_swap (td->hwINFO);
-  	tdBE   = m32_swap (td->hwBE);
-  	tdCBP  = m32_swap (td->hwCBP);
+	tdBE   = m32_swap (td->hwBE);
+	tdCBP  = m32_swap (td->hwCBP);


 	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
@@ -759,7 +759,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 	__u32 td_list_hc;
 	td_t *td_rev = NULL;
 	td_t *td_list = NULL;
-  	urb_priv_t *lurb_priv = NULL;
+	urb_priv_t *lurb_priv = NULL;

 	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
 	ohci->hcca->done_head = 0;
@@ -794,42 +794,42 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 /* td done list */
 static int dl_done_list (ohci_t *ohci, td_t *td_list)
 {
-  	td_t *td_list_next = NULL;
+	td_t *td_list_next = NULL;
 	ed_t *ed;
 	int cc = 0;
 	int stat = 0;
 	/* urb_t *urb; */
 	urb_priv_t *lurb_priv;
- 	__u32 tdINFO, edHeadP, edTailP;
+	__u32 tdINFO, edHeadP, edTailP;

-  	while (td_list) {
-   		td_list_next = td_list->next_dl_td;
+	while (td_list) {
+		td_list_next = td_list->next_dl_td;

-  		lurb_priv = &urb_priv;
-  		tdINFO = m32_swap (td_list->hwINFO);
+		lurb_priv = &urb_priv;
+		tdINFO = m32_swap (td_list->hwINFO);

-   		ed = td_list->ed;
+		ed = td_list->ed;

-   		dl_transfer_length(td_list);
+		dl_transfer_length(td_list);

-  		/* error code of transfer */
-  		cc = TD_CC_GET (tdINFO);
+		/* error code of transfer */
+		cc = TD_CC_GET (tdINFO);
 		if (cc != 0) {
 			dbg("ConditionCode %#x", cc);
 			stat = cc_to_error[cc];
 		}

-  		if (ed->state != ED_NEW) {
-  			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
-  			edTailP = m32_swap (ed->hwTailP);
+		if (ed->state != ED_NEW) {
+			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+			edTailP = m32_swap (ed->hwTailP);

 			/* unlink eds if they are not busy */
-     			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-     				ep_unlink (ohci, ed);
-     		}
+			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+				ep_unlink (ohci, ed);
+		}

-    		td_list = td_list_next;
-  	}
+		td_list = td_list_next;
+	}
 	return stat;
 }

@@ -851,9 +851,9 @@ static __u8 root_hub_dev_des[] =
 	0x00,       /*  __u16 idVendor; */
 	0x00,
 	0x00,       /*  __u16 idProduct; */
- 	0x00,
+	0x00,
 	0x00,       /*  __u16 bcdDevice; */
- 	0x00,
+	0x00,
 	0x00,       /*  __u8  iManufacturer; */
 	0x01,       /*  __u8  iProduct; */
 	0x00,       /*  __u8  iSerialNumber; */
@@ -872,7 +872,7 @@ static __u8 root_hub_config_des[] =
 	0x01,       /*  __u8  bConfigurationValue; */
 	0x00,       /*  __u8  iConfiguration; */
 	0x40,       /*  __u8  bmAttributes;
-                 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
 	0x00,       /*  __u8  MaxPower; */

 	/* interface */
@@ -890,9 +890,9 @@ static __u8 root_hub_config_des[] =
 	0x07,       /*  __u8  ep_bLength; */
 	0x05,       /*  __u8  ep_bDescriptorType; Endpoint */
 	0x81,       /*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
- 	0x03,       /*  __u8  ep_bmAttributes; Interrupt */
- 	0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 	0x00,
+	0x03,       /*  __u8  ep_bmAttributes; Interrupt */
+	0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
 	0xff        /*  __u8  ep_bInterval; 255 ms */
 };

@@ -984,7 +984,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 	int stat = 0;
 	__u32 datab[4];
 	__u8 *data_buf = (__u8 *)datab;
- 	__u16 bmRType_bReq;
+	__u16 bmRType_bReq;
 	__u16 wValue;
 	__u16 wIndex;
 	__u16 wLength;
@@ -1176,7 +1176,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 	len = min_t(int, len, leni);
 	if (data != data_buf)
 	    memcpy (data, data_buf, len);
-  	dev->act_len = len;
+	dev->act_len = len;
 	dev->status = stat;

 #ifdef DEBUG
@@ -1226,7 +1226,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

 	wait_ms(10);
 	/* ohci_dump_status(&gohci); */
-	
+
 	/* allow more time for a BULK device to react - some are slow */
 #define BULK_TO	 5000	/* timeout in milliseconds */
 	if (usb_pipetype (pipe) == PIPE_BULK)
@@ -1277,7 +1277,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	}

 	dev->status = stat;
-  	dev->act_len = transfer_len;
+	dev->act_len = transfer_len;

 #ifdef DEBUG
 	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
@@ -1362,7 +1362,7 @@ static int hc_reset (ohci_t *ohci)
 		ohci->slot_name,
 		readl (&ohci->regs->control));

-  	/* Reset USB (needed by some controllers) */
+	/* Reset USB (needed by some controllers) */
 	writel (0, &ohci->regs->control);

 	/* HC Reset requires max 10 us delay */
@@ -1385,8 +1385,8 @@ static int hc_reset (ohci_t *ohci)

 static int hc_start (ohci_t * ohci)
 {
-  	__u32 mask;
-  	unsigned int fminterval;
+	__u32 mask;
+	unsigned int fminterval;

 	ohci->disabled = 1;

@@ -1398,16 +1398,16 @@ static int hc_start (ohci_t * ohci)

 	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */

-  	fminterval = 0x2edf;
+	fminterval = 0x2edf;
 	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
 	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
 	writel (fminterval, &ohci->regs->fminterval);
 	writel (0x628, &ohci->regs->lsthresh);

- 	/* start controller operations */
- 	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+	/* start controller operations */
+	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
 	ohci->disabled = 0;
- 	writel (ohci->hc_control, &ohci->regs->control);
+	writel (ohci->hc_control, &ohci->regs->control);

 	/* disable all interrupts */
 	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
@@ -1447,7 +1447,7 @@ hc_interrupt (void)
 {
 	ohci_t *ohci = &gohci;
 	struct ohci_regs *regs = ohci->regs;
- 	int ints;
+	int ints;
 	int stat = -1;

 	if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
@@ -1534,17 +1534,17 @@ int usb_lowlevel_init(void)
 	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

-        /*
-         * Set the 48 MHz UPLL clocking. Values are taken from
-         * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-         */
-        clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
-        gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+	/*
+	 * Set the 48 MHz UPLL clocking. Values are taken from
+	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+	 */
+	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
+	gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */

-        /*
-         * Enable USB host clock.
-         */
-        clk_power->CLKCON |= (1 << 4);
+	/*
+	 * Enable USB host clock.
+	 */
+	clk_power->CLKCON |= (1 << 4);

 	memset (&gohci, 0, sizeof (ohci_t));
 	memset (&urb_priv, 0, sizeof (urb_priv_t));
@@ -1568,7 +1568,7 @@ int usb_lowlevel_init(void)
 	}
 	ptd = gtd;
 	gohci.hcca = phcca;
-        memset (phcca, 0, sizeof (struct ohci_hcca));
+	memset (phcca, 0, sizeof (struct ohci_hcca));

 	gohci.disabled = 1;
 	gohci.sleeping = 0;
@@ -1580,8 +1580,8 @@ int usb_lowlevel_init(void)

 	if (hc_reset (&gohci) < 0) {
 		hc_release_ohci (&gohci);
-                /* Initialization failed */
-                clk_power->CLKCON &= ~(1 << 4);
+		/* Initialization failed */
+		clk_power->CLKCON &= ~(1 << 4);
 		return -1;
 	}

@@ -1592,8 +1592,8 @@ int usb_lowlevel_init(void)
 	if (hc_start (&gohci) < 0) {
 		err ("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci (&gohci);
-                /* Initialization failed */
-                clk_power->CLKCON &= ~(1 << 4);
+		/* Initialization failed */
+		clk_power->CLKCON &= ~(1 << 4);
 		return -1;
 	}

@@ -224,7 +224,6 @@ struct ohci_regs {
 #define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */


-
 /* Virtual Root HUB */
 struct virt_root_hub {
 	int devnum; /* Address of Root Hub endpoint */
@@ -185,9 +185,14 @@ int interrupt_init (void)
 {
 	int32_t val;

+	/* Start the decrementer ticking down from 0xffffffff */
 	*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
 	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
 	*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
 	return (0);
 }

@@ -210,7 +215,7 @@ void set_timer (ulong t)
 	timestamp = t;
 }

-/* very rough timer... */
+/* delay x useconds AND perserve advance timstamp value */
 void udelay (unsigned long usec)
 {
 #ifdef CONFIG_INNOVATOROMAP1510
@@ -220,16 +225,24 @@ void udelay (unsigned long usec)
 	for (i = time_remaining; i > 0; i--) {
 	}
 #else
+	ulong tmo, tmp;

-	ulong tmo;
+	if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
+		tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;            /* finish normalize. */
+	}else{                          /* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CFG_HZ;
+		tmo /= (1000*1000);
+	}

-	tmo = usec / 1000;
-	tmo *= CFG_HZ;
-	tmo /= 1000;
+	tmp = get_timer (0);		/* get current timestamp */
+	if( (tmo + tmp) < tmp ) 	/* if setting this fordward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
+	else
+		tmo += tmp;		/* else, set advancing stamp wake up time */

-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
+	while (get_timer_masked () < tmo)/* loop till event */
 		/*NOP*/;
 #endif
 }
@@ -237,19 +250,23 @@ void udelay (unsigned long usec)
 void reset_timer_masked (void)
 {
 	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
+	lastdec = READ_TIMER;  /* capure current decrementer value time */
+	timestamp = 0;         /* start "advancing" time stamp from 0 */
 }

 ulong get_timer_masked (void)
 {
-	ulong now = READ_TIMER;           /* current tick value */
+	ulong now = READ_TIMER;		/* current tick value */

-	if (lastdec >= now) {             /* did I roll (rem decrementer) */
+	if (lastdec >= now) {		/* normal mode (non roll) */
 		/* normal mode */
-		timestamp += lastdec - now;   /* record amount of time since last check */
-	} else {
-		/* we have an overflow ... */
+		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+	} else {			/* we have overflow of the count down timer */
+		/* nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and cause problems.
+		 */
 		timestamp += lastdec + TIMER_LOAD_VAL - now;
 	}
 	lastdec = now;
@@ -257,6 +274,7 @@ ulong get_timer_masked (void)
 	return timestamp;
 }

+/* waits specified delay value and resets timestamp */
 void udelay_masked (unsigned long usec)
 {
 #ifdef CONFIG_INNOVATOROMAP1510
@@ -265,15 +283,20 @@ void udelay_masked (unsigned long usec)
    for (i=time_remaining; i>0; i--) { }
 #else

-	ulong tmo;
+	ulong tmo, tmp;

-	tmo = usec / 1000;
-	tmo *= CFG_HZ;
-	tmo /= 1000;
+	if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
+		tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;            /* finish normalize. */
+	}else{                          /* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CFG_HZ;
+		tmo /= (1000*1000);
+	}

-	reset_timer_masked ();
+	reset_timer_masked ();	/* set "advancing" timestamp to 0, set lastdec vaule */

-	while (get_timer_masked () < tmo)
+	while (get_timer_masked () < tmo) /* wait for time stamp to overtake tick number.*/
 		/*NOP*/;
 #endif
 }
@@ -292,7 +315,7 @@ unsigned long long get_ticks(void)
 * On ARM it returns the number of timer ticks per second.
 */
 ulong get_tbclk (void)
-{	/* poor timer, may need to improve especiall for bootp. */
+{
 	ulong tbclk;

 	tbclk = CFG_HZ;
@@ -79,7 +79,6 @@ int disable_interrupts (void)
 #endif


-
 void bad_mode (void)
 {
 	panic ("Resetting CPU ...\n");
@@ -31,7 +31,6 @@
 */


-
 #include <config.h>
 #include <version.h>

@@ -144,7 +143,7 @@ reset:
 	msr	cpsr,r0


-	/* 
+	/*
 	 * turn off the watchdog, unlock/diable sequence
 	 */
 	mov	r1, #0xF5
@@ -154,9 +153,6 @@ reset:
 	strh	r1, [r0]


-
-
-
 	/*
 	 * mask all IRQs by setting all bits in the INTMR - default
 	 */
@@ -411,7 +407,7 @@ fiq:
 .globl reset_cpu
 reset_cpu:
 	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0	
+	mov	r3, #0x0
 	strh	r3, [r1]	/* clear it */
 	mov	r3, #0x8
 	strh	r3, [r1]	/* force dsp+arm reset */
@@ -334,12 +334,12 @@ static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
 *	TRUE - if data read successfully
 */
 static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
-									  unsigned char RegisterAddress,
-									  unsigned short *pOutput)
+				      unsigned char RegisterAddress,
+				      unsigned short *pOutput)
 {
 	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
 			AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
-			(RegisterAddress << 18);
+			(RegisterAddress << 18) | *pOutput;

 	udelay (10000);

@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+OBJS	= serial.o interrupts.o cpu.o timer.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+BIG_ENDIAN = y
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+	-mshort-load-bytes -msoft-float -mbig-endian
+
+PLATFORM_CPPFLAGS += -mbig-endian -mapcs-32 -march=armv4 -mtune=strongarm1100
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/ixp425.h>
+
+int cpu_init (void)
+{
+	/*
+	 * setup up stack if necessary
+	 */
+/*
+
+  FIXME: the stack is _below_ the uboot code!!
+
+#ifdef CONFIG_USE_IRQ
+	IRQ_STACK_START = _armboot_end +
+			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+	_armboot_real_end = FIQ_STACK_START + 4;
+#else
+	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif
+*/
+   pci_init();
+	return 0;
+}
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * just disable everything that can disturb booting linux
+	 */
+
+	unsigned long i;
+
+	disable_interrupts ();
+
+	/* turn off I-cache */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	i &= ~0x1000;
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+	/* flush I-cache */
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+
+	return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	extern void reset_cpu (ulong addr);
+
+	printf ("reseting ...\n");
+
+	udelay (50000);				/* wait 50 ms */
+	disable_interrupts ();
+	reset_cpu (0);
+
+	/*NOTREACHED*/
+	return (0);
+}
+
+/* taken from blob */
+void icache_enable (void)
+{
+	register u32 i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	/* set i-cache */
+	i |= 0x1000;
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void icache_disable (void)
+{
+	register u32 i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	/* clear i-cache */
+	i &= ~0x1000;
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+	/* flush i-cache */
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+}
+
+int icache_status (void)
+{
+	register u32 i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	/* return bit */
+	return (i & 0x1000);
+}
+
+/* we will never enable dcache, because we have to setup MMU first */
+void dcache_enable (void)
+{
+	return;
+}
+
+void dcache_disable (void)
+{
+	return;
+}
+
+int dcache_status (void)
+{
+	return 0;					/* always off */
+}
+
+/* FIXME */
+void pci_init(void)
+{
+	return;
+}
@@ -0,0 +1,160 @@
+/* vi: set ts=8 sw=8 noet: */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ixp425.h>
+
+extern void reset_cpu (ulong addr);
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ/FIQ interrupts */
+void enable_interrupts (void)
+{
+#error: interrupts not implemented yet
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+#error: interrupts not implemented yet
+}
+#else
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
+	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
+	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
+	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
+	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
+	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
+	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32"
+	};
+
+	flags = condition_codes (regs);
+
+	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+		"sp : %08lx  ip : %08lx  fp : %08lx\n",
+		instruction_pointer (regs),
+		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+		flags & CC_N_BIT ? 'N' : 'n',
+		flags & CC_Z_BIT ? 'Z' : 'z',
+		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+		interrupts_enabled (regs) ? "on" : "off",
+		fast_interrupts_enabled (regs) ? "on" : "off",
+		processor_modes[processor_mode (regs)],
+		thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+
+int interrupt_init (void)
+{
+	/* nothing happens here - we don't setup any IRQs */
+	return (0);
+}
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/ixp425.h>
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned int quot = 0;
+	int uart = CFG_IXP425_CONSOLE;
+
+	if (gd->baudrate == 1200)
+		quot = 192;
+	else if (gd->baudrate == 9600)
+		quot = 96;
+	else if (gd->baudrate == 19200)
+		quot = 48;
+	else if (gd->baudrate == 38400)
+		quot = 24;
+	else if (gd->baudrate == 57600)
+		quot = 16;
+	else if (gd->baudrate == 115200)
+		quot = 8;
+	else
+		hang ();
+
+	IER(uart) = 0;					/* Disable for now */
+	FCR(uart) = 0;					/* No fifos enabled */
+
+	/* set baud rate */
+	LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
+	DLL(uart) = quot & 0xff;
+	DLH(uart) = quot >> 8;
+	LCR(uart) = LCR_WLS0 | LCR_WLS1;
+
+	IER(uart) = IER_UUE;
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+	serial_setbrg ();
+
+	return (0);
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+	/* wait for room in the tx FIFO on UART */
+	while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0);
+
+	THR(CFG_IXP425_CONSOLE) = c;
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		serial_putc ('\r');
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_tstc (void)
+{
+	return LSR(CFG_IXP425_CONSOLE) & LSR_DR;
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+	while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR));
+
+	return (char) RBR(CFG_IXP425_CONSOLE) & 0xff;
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
@@ -0,0 +1,525 @@
+/* vi: set ts=8 sw=8 noet: */
+/*
+ *  u-boot - Startup Code for XScale IXP
+ *
+ * Copyright (C) 2003	Kyle Harris <kharris@nexus-tech.net>
+ *
+ * Based on startup code example contained in the
+ * Intel IXP4xx Programmer's Guide and past u-boot Start.S
+ * samples.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/ixp425.h>
+
+#define MMU_Control_M  0x001    /* Enable MMU */
+#define MMU_Control_A  0x002    /* Enable address alignment faults */
+#define MMU_Control_C  0x004    /* Enable cache */
+#define MMU_Control_W  0x008    /* Enable write-buffer */
+#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
+#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
+#define MMU_Control_L  0x040    /* Compatability: */
+#define MMU_Control_B  0x080    /* Enable Big-Endian */
+#define MMU_Control_S  0x100    /* Enable system protection */
+#define MMU_Control_R  0x200    /* Enable ROM protection */
+#define MMU_Control_I  0x1000   /* Enable Instruction cache */
+#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
+#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
+
+
+/*
+ * Macro definitions
+ */
+	/* Delay a bit */
+	.macro DELAY_FOR cycles, reg0
+	ldr     \reg0, =\cycles
+	subs    \reg0, \reg0, #1
+	subne   pc,  pc, #0xc
+	.endm
+
+	/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
+	sub  pc,pc,#4
+	.endm
+
+.globl _start
+_start: b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * - relocate armboot to ram
+ * - setup stack
+ * - jump to second stage
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+	.word armboot_end_data
+.globl _armboot_end
+_armboot_end:
+	.word armboot_end
+
+/*
+ * This is defined in the board specific linker script
+ */
+.globl _bss_start
+_bss_start:
+	.word bss_start
+
+.globl _bss_end
+_bss_end:
+	.word bss_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+	.word 0x0badc0de
+
+/*
+ * We relocate uboot to this address (end of RAM - 128 KiB)
+ */
+.globl _uboot_reloc
+_uboot_reloc:
+	.word TEXT_BASE
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/****************************************************************************/
+/*									    */
+/* the actual reset code						    */
+/*									    */
+/****************************************************************************/
+
+reset:
+	/* disable mmu, set big-endian */
+	mov	r0, #0xf8
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT  r0
+
+	/* invalidate I & D caches & BTB */
+	mcr	p15, 0, r0, c7, c7, 0
+	CPWAIT	r0
+
+	/* invalidate I & Data TLB */
+	mcr 	p15, 0, r0, c8, c7, 0
+	CPWAIT r0
+
+	/* drain write and fill buffers */
+	mcr	p15, 0, r0, c7, c10, 4
+	CPWAIT	r0
+
+	/* disable write buffer coalescing */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #1
+	mcr	p15, 0, r0, c1, c0, 1
+	CPWAIT	r0
+
+	/* set EXP CS0 to the optimum timing */
+	ldr	r1, =CFG_EXP_CS0
+	ldr     r2, =IXP425_EXP_CS0
+	str     r1, [r2]
+
+	/* make sure flash is visible at 0 */
+	ldr 	r2, =IXP425_EXP_CFG0
+	ldr     r1, [r2]
+	orr     r1, r1, #0x80000000
+	str     r1, [r2]
+
+	mov 	r1, #CFG_SDR_CONFIG
+	ldr     r2, =IXP425_SDR_CONFIG
+	str     r1, [r2]
+
+	/* disable refresh cycles */
+	mov 	r1, #0
+	ldr     r3, =IXP425_SDR_REFRESH
+	str	r1, [r3]
+
+	/* send nop command */
+	mov 	r1, #3
+	ldr	r4, =IXP425_SDR_IR
+	str	r1, [r4]
+	DELAY_FOR 0x4000, r0
+
+	/* set SDRAM internal refresh val */
+	ldr	r1, =CFG_SDRAM_REFRESH_CNT
+	str     r1, [r3]
+	DELAY_FOR 0x4000, r0
+
+	/* send precharge-all command to close all open banks */
+	mov     r1, #2
+	str     r1, [r4]
+	DELAY_FOR 0x4000, r0
+
+	/* provide 8 auto-refresh cycles */
+	mov     r1, #4
+	mov     r5, #8
+111:    str	r1, [r4]
+	DELAY_FOR 0x100, r0
+	subs	r5, r5, #1
+	bne	111b
+
+	/* set mode register in sdram */
+	mov	r1, #1
+	str	r1, [r4]
+	DELAY_FOR 0x4000, r0
+
+	/* send normal operation command */
+	mov	r1, #6
+	str	r1, [r4]
+	DELAY_FOR 0x4000, r0
+
+	/* copy */
+	mov     r0, #0
+	mov     r4, r0
+	add     r2, r0, #0x40000
+	mov     r1, #0x10000000
+	mov     r5, r1
+
+    30:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r0, r2
+	bne     30b
+
+	/* invalidate I & D caches & BTB */
+	mcr	p15, 0, r0, c7, c7, 0
+	CPWAIT	r0
+
+	/* invalidate I & Data TLB */
+	mcr 	p15, 0, r0, c8, c7, 0
+	CPWAIT r0
+
+	/* drain write and fill buffers */
+	mcr	p15, 0, r0, c7, c10, 4
+	CPWAIT	r0
+
+	/* move flash to 0x50000000 */
+	ldr 	r2, =IXP425_EXP_CFG0
+	ldr     r1, [r2]
+	bic     r1, r1, #0x80000000
+	str     r1, [r2]
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* invalidate I & Data TLB */
+	mcr 	p15, 0, r0, c8, c7, 0
+	CPWAIT r0
+
+	/* enable I cache */
+	mrc     p15, 0, r0, c1, c0, 0
+	orr     r0, r0, #MMU_Control_I
+	mcr     p15, 0, r0, c1, c0, 0
+	CPWAIT  r0
+
+	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
+	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
+	orr	r0,r0,#0x13
+	msr	cpsr,r0
+
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+	cmp     r0, r1                  /* don't reloc during debug         */
+	beq     stack_setup
+
+	ldr	r2, _armboot_start
+	ldr	r3, _armboot_end
+	sub	r2, r3, r2		/* r2 <- size of armboot            */
+	add	r2, r0, r2		/* r2 <- source end address         */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+
+	/* Set up the stack						    */
+
+stack_setup:
+
+	ldr	r0, _uboot_reloc	/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CFG_MALLOC_LEN /* malloc area			    */
+					/* FIXME: bdinfo should be here	    */
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+
+clear_bss:
+
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
+
+	ldr	pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/****************************************************************************/
+/*									    */
+/* Interrupt handling							    */
+/*									    */
+/****************************************************************************/
+
+/* IRQ stack frame							    */
+
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+
+	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
+	add	r8, sp, #S_PC
+
+	ldr	r2, _armboot_end
+	add	r2, r2, #CONFIG_STACKSIZE
+	sub	r2, r2, #8
+	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
+	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
+	mov	r0, sp
+	.endm
+
+
+	/* use irq_save_user_regs / irq_restore_user_regs for		     */
+	/* IRQ/FIQ handling						     */
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
+	str	lr, [r8, #0]			/* Save calling PC	     */
+	mrs	r6, spsr
+	str	r6, [r8, #4]			/* Save CPSR		     */
+	str	r0, [r8, #8]			/* Save OLD_R0		     */
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_end		@ setup our mode stack
+	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
+	sub	r13, r13, #8
+
+	str	lr, [r13]			@ save caller lr / spsr
+	mrs	lr, spsr
+	str	lr, [r13, #4]
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	msr	spsr_c, r13
+	mov	lr, pc
+	movs	pc, lr
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+
+/****************************************************************************/
+/*									    */
+/* exception handlers							    */
+/*									    */
+/****************************************************************************/
+
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	irq_save_user_regs		/* someone ought to write a more    */
+	bl	do_fiq			/* effiction fiq_save_user_regs	    */
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+/****************************************************************************/
+/*                                                                          */
+/* Reset function: Use Watchdog to reset                                    */
+/*                                                                          */
+/****************************************************************************/
+
+	.align	5
+.globl reset_cpu
+
+reset_cpu:
+	ldr 	r1, =0x482e
+	ldr     r2, =IXP425_OSWK
+	str     r1, [r2]
+	ldr 	r1, =0x0fff
+	ldr     r2, =IXP425_OSWT
+	str     r1, [r2]
+	ldr 	r1, =0x5
+	ldr     r2, =IXP425_OSWE
+	str     r1, [r2]
+	b	reset_endless
+
+
+reset_endless:
+
+	b	reset_endless
@@ -0,0 +1,79 @@
+/* vi: set ts=8 sw=8 noet: */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ixp425.h>
+
+ulong get_timer (ulong base)
+{
+       return get_timer_masked () - base;
+}
+
+void ixp425_udelay(unsigned long usec)
+{
+	/*
+	 * This function has a max usec, but since it is called from udelay
+	 * we should not have to worry... be happy
+	 */
+	unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
+
+	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
+	usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
+	*IXP425_OSRT1 = usecs;
+	while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND));
+}
+
+void udelay (unsigned long usec)
+{
+	while (usec--) ixp425_udelay(1);
+}
+
+static ulong reload_constant = 0xfffffff0;
+
+void reset_timer_masked (void)
+{
+	ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
+
+	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
+	*IXP425_OSRT1 = reload;
+}
+
+ulong get_timer_masked (void)
+{
+	/*
+	 * Note that it is possible for this to wrap!
+	 * In this case we return max.
+	 */
+	ulong current = *IXP425_OST1;
+	if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)
+	{
+		return reload_constant;
+	}
+	return (reload_constant - current);
+}
@@ -28,6 +28,6 @@
 #


-PLATFORM_RELFLAGS += 	-mrelocatable -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += 	-fPIC -ffixed-r14 -meabi

-PLATFORM_CPPFLAGS +=	-DCONFIG_5xx -ffixed-r2 -ffixed-r29  -mpowerpc -msoft-float
+PLATFORM_CPPFLAGS +=	-DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float
@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #

-PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi

 PLATFORM_CPPFLAGS += -DCONFIG_MPC5XXX -ffixed-r2 -ffixed-r29 \
 		     -mstring -mcpu=603e -mmultiple
@@ -62,8 +62,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));

 	/* Charge the watchdog timer */
-	*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0xf;
+	*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
 	*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
+	while(1);

 	return 1;

@@ -847,7 +847,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)

 	/*
 	 * Try to set the mac address now. The fec mac address is
-	 * a garbage after reset. When not using fec for booting 
+	 * a garbage after reset. When not using fec for booting
 	 * the Linux fec driver will try to work with this garbage.
 	 */
 	tmp = getenv("ethaddr");
@@ -133,13 +133,13 @@ static int do_address(uchar chip, char rdwr_flag)
 	mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
 	mpc_reg_out(&regs->mdr, chip, 0);

-        if (wait_for_pin(&status)) {
-                return -2;
-        }
+	if (wait_for_pin(&status)) {
+		return -2;
+	}

-        if (status & I2C_RXAK) {
-                return -3;
-        }
+	if (status & I2C_RXAK) {
+		return -3;
+	}

 	return 0;
 }
@@ -229,9 +229,10 @@ static int mpc_get_fdr(int speed)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	static int fdr = -1;
-	static int best_speed = 0;

 	if (fdr == -1) {
+		ulong best_speed = 0;
+		ulong divider;
 		ulong ipb, scl;
 		ulong bestmatch = 0xffffffffUL;
 		int best_i = 0, best_j = 0, i, j;
@@ -250,7 +251,7 @@ static int mpc_get_fdr(int speed)
 		ipb = gd->ipb_clk;
 		for (i = 7; i >= 0; i--) {
 			for (j = 7; j >= 0; j--) {
-				scl = 2 * (scltap[j].scl2tap + 
+				scl = 2 * (scltap[j].scl2tap +
 					(SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
 				if (ipb <= speed*scl) {
 					if ((speed*scl - ipb) < bestmatch) {
@@ -262,8 +263,13 @@ static int mpc_get_fdr(int speed)
 				}
 			}
 		}
-		fdr = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
-		printf("%d kHz, ", best_speed / 1000);
+		divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
+		if (gd->flags & GD_FLG_RELOC) {
+			fdr = divider;
+		} else {
+			printf("%ld kHz, ", best_speed / 1000);
+			return divider;
+		}
 	}

 	return fdr;
@@ -344,13 +350,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 	xaddr[2] = (addr >>  8) & 0xFF;
 	xaddr[3] =  addr	& 0xFF;

-        if (wait_for_bb()) {
+	if (wait_for_bb()) {
 		printf("i2c_write: bus is busy\n");
 		goto Done;
 	}

-        mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
-        if (do_address(chip, 0)) {
+	mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+	if (do_address(chip, 0)) {
 		printf("i2c_write: failed to address chip\n");
 		goto Done;
 	}
@@ -101,22 +101,22 @@ void pci_mpc5xxx_init (struct pci_controller *hose)

 	/* GPIO Multiplexing - enable PCI */
 	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
-	
+
 	/* Set host bridge as pci master and enable memory decoding */
 	*(vu_long *)MPC5XXX_PCI_CMD |=
 		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	
+
 	/* Set maximum latency timer */
 	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);

 	/* Set cache line size */
 	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
 		(CFG_CACHELINE_SIZE / 4);
-	
+
 	/* Map MBAR to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
 	*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
-	
+
 	/* Map RAM to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
 	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
@@ -133,14 +133,14 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 	/* Enable piplining */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
 #endif
-	
+
 	/* Disable interrupts from PCI controller */
 	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
 	*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
-	
+
 	/* Disable initiator windows */
 	*(vu_long *)MPC5XXX_PCI_IWCR = 0;
-	
+
 	/* Map PCI memory to physical space */
 	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
 		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
@@ -166,7 +166,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 		pci_hose_write_config_byte_via_dword,
 		pci_hose_write_config_word_via_dword,
 		mpc5200_write_config_dword);
-	
+
 	udelay(1000);

 #ifdef CONFIG_PCI_SCAN_SHOW
@@ -103,6 +103,47 @@ boot_cold:
 boot_warm:
 	mfmsr	r5			/* save msr contents		*/

+#if defined(CFG_LOWBOOT)
+	lis	r4, CFG_DEFAULT_MBAR@h
+	lis	r3,     0x0000FF00@h
+	ori	r3, r3, 0x0000FF00@l
+	stw	r3, 0x4(r4)
+	lis	r3,     0x0000FFFF@h
+	ori	r3, r3, 0x0000FFFF@l
+	stw	r3, 0x8(r4)
+	lis	r3,     0x00047800@h
+	ori	r3, r3, 0x00047800@l
+	stw	r3, 0x300(r4)
+	lis	r3,     0x02010000@h
+	ori	r3, r3, 0x02010000@l
+	stw	r3, 0x54(r4)
+
+#if defined(CFG_LOWBOOT08)
+	lis	r3,     0xff800160@h
+	ori	r3, r3, 0xff800160@l
+#endif
+#if defined(CFG_LOWBOOT16)
+	lis	r3,     0xff000160@h
+	ori	r3, r3, 0xff000160@l
+#endif
+	mtlr	r3
+	blr
+lowboot_reentry:	/* FLASH_BASE + 0x160 */
+	
+	lis	r3,     0x0000FF00@h
+	ori	r3, r3, 0x0000FF00@l
+	stw	r3, 0x4c(r4)
+	lis	r3,     0x0000FFFF@h
+	ori	r3, r3, 0x0000FFFF@l
+	stw	r3, 0x50(r4)
+	lis	r3,     0x00047800@h
+	ori	r3, r3, 0x00047800@l
+	stw	r3, 0x300(r4)
+	lis	r3,     0x02000001@h
+	ori	r3, r3, 0x02000001@l
+	stw	r3, 0x54(r4)
+#endif	/* CFG_LOWBOOT */
+	
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
 	lis	r3, CFG_MBAR@h
 	ori	r3, r3, CFG_MBAR@l
@@ -21,7 +21,6 @@
 # MA 02111-1307 USA
 #

-PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi

 PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float
-##PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
Author	SHA1	Message	Date
wdenk	fa1399ed12	Accelerate booting on TRAB board: read and check autoupdate image headers first instead of always reading the whole images.	2003-12-06 11:20:01 +00:00
wdenk	b96619a117	Fix typo in MPC5XXX code (pointed out by Victor Wren)	2003-12-05 21:08:38 +00:00
wdenk	af6d1dfc7f	* Enabled password check on RMU board * Fix configuration problem with IceCube in LOWBOOT configuration: environment got embedded, corrupting the image layout.	2003-12-03 23:53:42 +00:00
wdenk	fd3103bb8e	Add support for BMS2003 board (featuring a NEC NL6448BC33-54. 10.4", 640x480 TFT display). Fix NEC display names (it's 6440 [for 640x480], not 6640).	2003-11-25 16:55:19 +00:00
wdenk	b4757cee52	Fix flash driver for TRAB board (must use Unlock Bypass Reset command to exit Unlock Bypass Mode); adjust timings for flash, SRAM and CPLD	2003-11-17 21:45:27 +00:00
wdenk	5bb226e821	* Use "-fPIC" instead of "-mrelocatable" to prevent problems with recent tools * Add checksum verification to 'imls' command * Add bd_info fields needed for 4xx Linux I2C driver * Patch by Martin Krause, 4 Nov. 2003: Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap) * Print used network interface when CONFIG_NET_MULTI is set	2003-11-17 21:14:37 +00:00
wdenk	5cf9da4821	* Patch by Bernhard Kuhn, 28 Oct 2003: Add low boot support for MPC5200 * Fix problem with dual PCMCIA support (NSCU) * Fix MPC5200 I2C initialization function	2003-11-07 13:42:26 +00:00
wdenk	b13fb01a62	* Fix parameter passing to standalone images with bootm command * Patch by Kyle Harris, 30 Oct 2003: Fix build errors for ixdp425 board * Patch by David M. Horn, 29 Oct 2003: Fixes to build under CYGWIN * Get IceCube MGT5100 working (again)	2003-10-30 21:49:38 +00:00
wdenk	5fa66df63a	* Prepare for release * Fix problems in memory test on some boards (which was not non-destructive as intended) * Patch by Gary Jennejohn, 28 Oct 2003: Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack to prevent stack overflow on ARM systems	2003-10-29 23:18:55 +00:00
wdenk	a0f2fe524c	* Patch by Stephan Linz, 28 Oct 2003: fix init sequence error for NIOS port * Allow lowercase spelling for IceCube_5200; support MPC5200LITE name * Add CONFIG_VERSION_VARIABLE to TRAB configuration	2003-10-28 09:14:21 +00:00
wdenk	a57a496f4d	* Patch by Xiao Xianghua, 23 Oct 2003: small patch for mpc85xx * Fix small problem in MPC5200 I2C driver * Fix FCC3 support on ATC board	2003-10-26 22:52:58 +00:00
dzu	8cb8143ef7	* Correct header printing for multi-image files in do_bootm() * Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED	2003-10-24 13:14:45 +00:00
wdenk	4654af27b8	Fix PCI problems on PPChameleon board	2003-10-22 09:00:28 +00:00
wdenk	a3ad8e26a4	* Patch by Steven Scholz, 18 Oct 2003: Fix AT91RM9200 ethernet driver * Patch by Nye Liu, 17 Oct 2003: Fix typo in include/mpc8xx.h * Patch by Richard Woodruff, 16 Oct 03: Fixes for cpu/arm925/interrupt.c - Initialize timestamp & lastdec vars. - fix timestamp overflows. - fix lastdec overflow. - smarter normalization to allow udelay() below 1ms to work. * Patch by Scott McNutt, 16 Oct add networking support for the Altera Nios Development Kit, Cyclone Edition (DK-1C20) * Patch by Jon Diekema, 14 Oct 2003: add hint about doc/README.silent to README file	2003-10-19 23:22:11 +00:00
wdenk	d7281f4109	* Fix PCI problems on PPChameleonEVB * TRAB auto-update: image type patch by Martin Krause, 17 Oct 2003	2003-10-19 22:30:08 +00:00
dzu	e7df029f1a	Add CompactFlash support for NSCU	2003-10-19 21:43:26 +00:00
wdenk	3d1e8a9d4e	TRAB auto-update: Base decision if we have to strip the image header on image type as encoded in the header	2003-10-16 12:53:35 +00:00
wdenk	42d1f0394b	* Patches by Xianghua Xiao, 15 Oct 2003: - Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup	2003-10-15 23:53:47 +00:00
wdenk	2d5b561e2b	* Make sure HUSH is initialized for running auto-update scripts * Make 5200 reset command _really_ reset the board, without running any other code after it * Fix flash mapping and display on P3G4 board * Patch by Kyle Harris, 15 Jul 2003: - add support for Intel IXP425 CPU - add support for IXDP425 eval board	2003-10-14 19:43:55 +00:00
wdenk	f72da3406b	Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent for more information	2003-10-10 10:05:42 +00:00