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* Patches by Xianghua Xiao, 15 Oct 2003:

Browse Source 
- Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup
This commit is contained in:
wdenk 2003-10-15 23:53:47 +00:00
parent 2d5b561e2b
commit 42d1f0394b
174 changed files with 14773 additions and 3497 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
CHANGELOG
View File

@ -2,6 +2,14 @@
Changes for U-Boot 1.0.0:
======================================================================
* Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
- Added Motorola MPC8540ADS board support (board/mpc8540ads)
- Added Motorola MPC8560ADS board support (board/mpc8560ads)
* Fix flash timings on TRAB board
* Make sure HUSH is initialized for running auto-update scripts
* Make 5200 reset command _really_ reset the board, without running
@ -38,7 +46,7 @@ Changes for U-Boot 1.0.0:
* Patch by Martin Krause, 09 Oct 2003:
Fixes for TRAB board
- /board/trab/rs485.c: correct baudrate
- /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
- /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
udelay(); fix some timing problems with adc controller
- /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
modify commands: touch and buzzer
@ -88,7 +96,7 @@ Changes for U-Boot 1.0.0:
link state to the fault LED.
- In NetLoop, make the Fault LED reflect the link status. The link
status gets updated on entry, and on timeouts.
* Patch by Anders Larsen, 18 Sep 2003:
allow mkimage to build and run on Cygwin-hosted systems

25
CREDITS
View File

@ -18,14 +18,14 @@ N: Dr. Bruno Achauer
E: bruno@exet-ag.de
D: Support for NetBSD (both as host and target system)
N: Swen Anderson
E: sand@peppercon.de
D: ERIC Support
N: Guillaume Alexandre
E: guillaume.alexandre@gespac.ch
D: Add PCIPPC6 configuration
N: Swen Anderson
E: sand@peppercon.de
D: ERIC Support
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA board support, ARTOS support.
@ -190,6 +190,11 @@ N: Thomas Koeller
E: tkoeller@gmx.net
D: Port to Motorola Sandpoint 3 (MPC8240)
N: Raghu Krishnaprasad
E: Raghu.Krishnaprasad@fci.com
D: Support for Adder-II MPC852T evaluation board
W: http://www.forcecomputers.com
N: Thomas Lange
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
@ -307,12 +312,6 @@ E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA board support, ARTOS support.
N: Raghu Krishnaprasad
E: Raghu.Krishnaprasad@fci.com
D: Support for Adder-II MPC852T evaluation board
W: http://www.forcecomputers.com
N: Xianghua Xiao
E: x.xiao@motorola.com
D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.

13
MAINTAINERS
View File

@ -112,10 +112,6 @@ Dave Ellis <DGE@sixnetio.com>
SXNI855T MPC8xx
Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
ADDERII MPC852T
Thomas Frieden <ThomasF@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
@ -158,6 +154,10 @@ Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
ADDERII MPC852T
Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
@ -240,6 +240,11 @@ John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
Xianghua Xiao <x.xiao@motorola.com>
MPC8540ADS MPC8540
MPC8560ADS MPC8560
-------------------------------------------------------------------------
Unknown / orphaned boards:

11
MAKEALL
View File

@ -86,6 +86,14 @@ LIST_8260=" \
TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
"
#########################################################################
## MPC85xx Systems (includes 8540, 8560 etc.)
#########################################################################
LIST_85xx=" \
MPC8540ADS MPC8560ADS \
"
#########################################################################
## 74xx/7xx Systems
#########################################################################
@ -102,6 +110,7 @@ LIST_7xx=" \
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8xx} \
${LIST_824x} ${LIST_8260} \
${LIST_85xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
@ -180,7 +189,7 @@ build_target() {
for arg in $@
do
case "$arg" in
ppc|5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx| \
ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|pxa|ixp| \
mips| \
x86|I486)

13
Makefile
View File

@ -106,6 +106,9 @@ endif
ifeq ($(CPU),ppc4xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
LIBS = board/$(BOARDDIR)/lib$(BOARD).a
LIBS += cpu/$(CPU)/lib$(CPU).a
@ -774,6 +777,16 @@ TQM8265_AA_config: unconfig
ZPC1900_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
#########################################################################
## MPC85xx Systems
#########################################################################
MPC8540ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
MPC8560ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
#########################################################################
## 74xx/7xx Systems
#########################################################################

32
README
View File

@ -146,6 +146,7 @@ Directory Hierarchy:
- cpu/mpc8xx Files specific to Motorola MPC8xx CPUs
- cpu/mpc824x Files specific to Motorola MPC824x CPUs
- cpu/mpc8260 Files specific to Motorola MPC8260 CPU
- cpu/mpc85xx Files specific to Motorola MPC85xx CPUs
- cpu/ppc4xx Files specific to IBM 4xx CPUs
@ -199,6 +200,10 @@ Directory Hierarchy:
- board/mbx8xx Files specific to MBX boards
- board/mpc8260ads
Files specific to MPC8260ADS and PQ2FADS-ZU boards
- board/mpc8540ads
Files specific to MPC8540ADS boards
- board/mpc8560ads
Files specific to MPC8560ADS boards
- board/mpl/ Files specific to boards manufactured by MPL
- board/mpl/common Common files for MPL boards
- board/mpl/pip405 Files specific to PIP405 boards
@ -210,7 +215,7 @@ Directory Hierarchy:
- board/oxc Files specific to OXC boards
- board/omap1510inn
Files specific to OMAP 1510 Innovator boards
- board/omap1610inn
- board/omap1610inn
Files specific to OMAP 1610 Innovator boards
- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
- board/pm826 Files specific to PM826 boards
@ -306,6 +311,7 @@ The following options need to be configured:
CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
or CONFIG_MPC5xx
or CONFIG_MPC824X, CONFIG_MPC8260
or CONFIG_MPC85xx
or CONFIG_IOP480
or CONFIG_405GP
or CONFIG_405EP
@ -356,7 +362,8 @@ The following options need to be configured:
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900
CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900,
CONFIG_MPC8540ADS, CONFIG_MPC8560ADS
ARM based boards:
-----------------
@ -591,7 +598,7 @@ The following options need to be configured:
CFG_CMD_DHCP DHCP support
CFG_CMD_DIAG * Diagnostics
CFG_CMD_DOC * Disk-On-Chip Support
CFG_CMD_DTT Digital Therm and Thermostat
CFG_CMD_DTT Digital Therm and Thermostat
CFG_CMD_ECHO * echo arguments
CFG_CMD_EEPROM * EEPROM read/write support
CFG_CMD_ELF bootelf, bootvx
@ -893,9 +900,9 @@ The following options need to be configured:
images is included. If not, only uncompressed and gzip
compressed images are supported.
NOTE: the bzip2 algorithm requires a lot of RAM, so
the malloc area (as defined by CFG_MALLOC_LEN) should
be at least 4MB.
NOTE: the bzip2 algorithm requires a lot of RAM, so
the malloc area (as defined by CFG_MALLOC_LEN) should
be at least 4MB.
- Ethernet address:
CONFIG_ETHADDR
@ -1757,13 +1764,13 @@ the default environment is used; a new CRC is computed as soon as you
use the "saveenv" command to store a valid environment.
- CFG_FAULT_ECHO_LINK_DOWN:
Echo the inverted Ethernet link state to the fault LED.
Echo the inverted Ethernet link state to the fault LED.
Note: If this option is active, then CFG_FAULT_MII_ADDR
also needs to be defined.
- CFG_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
MII address of the PHY to check for the Ethernet link state.
Low Level (hardware related) configuration options:
---------------------------------------------------
@ -1774,9 +1781,9 @@ Low Level (hardware related) configuration options:
- CFG_DEFAULT_IMMR:
Default address of the IMMR after system reset.
Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
and RPXsuper) to be able to adjust the position of
the IMMR register after a reset.
Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
and RPXsuper) to be able to adjust the position of
the IMMR register after a reset.
- Floppy Disk Support:
CFG_FDC_DRIVE_NUMBER
@ -1950,7 +1957,8 @@ configurations; the following names are supported:
GEN860T_config EBONY_config FPS860L_config
ELPT860_config cmi_mpc5xx_config NETVIA_config
at91rm9200dk_config omap1510inn_config MPC8260ADS_config
omap1610inn_config ZPC1900_config
omap1610inn_config ZPC1900_config MPC8540ADS_config
MPC8560ADS_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for

2
board/adderII/adderII.h
View File

@ -41,5 +41,3 @@
* | |
* | ... |
*****************************************************************************/

1
board/adderII/config.mk
View File

@ -26,4 +26,3 @@
#
TEXT_BASE = 0xFE000000

1
board/adderII/u-boot.lds
View File

@ -144,4 +144,3 @@ SECTIONS
_end = . ;
PROVIDE (end = .);
}

2
board/dave/PPChameleonEVB/PPChameleonEVB.c
View File

@ -51,7 +51,7 @@ int gunzip(void *, int, unsigned char *, int *);
int board_pre_init (void)
{
out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive

32
board/dave/PPChameleonEVB/flash.c
View File

@ -46,8 +46,8 @@ unsigned long flash_init (void)
#else
unsigned long size_b0;
int i;
uint pbcr;
unsigned long base_b0;
uint pbcr;
unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
@ -64,14 +64,14 @@ unsigned long flash_init (void)
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b0 = -size_b0;
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
size_val = 0;
@ -90,15 +90,15 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(ebccfgd, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
flash_info[0].size = size_b0;
return (size_b0);
#endif

190
board/dave/common/flash.c
View File

@ -40,11 +40,11 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
short n;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@ -58,7 +58,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
base += 64 << 10;
++i;
}
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@ -75,7 +75,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
--i;
info->start[i] = base;
}
} else {
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
@ -103,10 +103,10 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
void flash_print_info (flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
@ -164,28 +164,28 @@ void flash_print_info (flash_info_t *info)
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
#ifdef CFG_FLASH_EMPTY_INFO
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
/* print empty and read-only info */
/* print empty and read-only info */
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
@ -219,7 +219,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
short n;
CFG_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
@ -288,42 +288,42 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
info->flash_id += FLASH_STMW320DT;
info->sector_count = 67;
info->flash_id += FLASH_STMW320DT;
info->sector_count = 67;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000; break; /* => 8 MB */
@ -346,11 +346,11 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@ -364,7 +364,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
base += 64 << 10;
++i;
}
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@ -381,13 +381,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
--i;
info->start[i] = base;
}
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
/* set sector offsets for top boot block type */
base += info->size;
i = info->sector_count;
/* 1 x 16k boot sector */
/* 1 x 16k boot sector */
base -= 16 << 10;
--i;
--i;
info->start[i] = base;
/* 2 x 8k boot sectors */
for (n=0; n<2; ++n) {
@ -395,9 +395,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
--i;
info->start[i] = base;
}
/* 1 x 32k boot sector */
/* 1 x 32k boot sector */
base -= 32 << 10;
--i;
--i;
info->start[i] = base;
while (i > 0) { /* 64k regular sectors */
@ -405,7 +405,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
--i;
info->start[i] = base;
}
} else {
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
@ -432,10 +432,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
}
/*
@ -459,7 +459,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
volatile CFG_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
int i;
int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
@ -498,25 +498,25 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
if (sect == s_first) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
}
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
if (sect == s_first) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
}
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
}
}
@ -637,42 +637,42 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
int i;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
(CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
(CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
{
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
{
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
dest2[i] = data2[i];
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
(data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
(data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}

16
board/dave/common/fpga.c
View File

@ -57,16 +57,16 @@
#define SET_FPGA(data) out32(GPIO0_OR, data)
#define FPGA_WRITE_1 { \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#define FPGA_WRITE_0 { \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#if 0
static int fpga_boot (unsigned char *fpgadata, int size)

16
board/dbau1x00/memsetup.S
View File

@ -9,17 +9,17 @@
memsetup:
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
sync
nop
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
sync
nop
/* Setup AUX PLL */
/* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 8 /* 96 MHz */
sw t1, 0(t0) /* aux pll */
sync
sw t1, 0(t0) /* aux pll */
sync
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0

1
board/dk1c20/config.mk
View File

@ -27,4 +27,3 @@ TEXT_BASE = 0x018c0000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

15
board/dk1c20/u-boot.lds
View File

@ -33,17 +33,17 @@ SECTIONS
cpu/nios/start.o (.text)
*(.text)
}
__text_end = .;
__text_end = .;
. = ALIGN(4);
.rodata :
. = ALIGN(4);
.rodata :
{
*(.rodata)
}
__rodata_end = .;
. = ALIGN(4);
.data :
. = ALIGN(4);
.data :
{
*(.data)
}
@ -59,12 +59,11 @@ SECTIONS
__u_boot_cmd_end = .;
__bss_start = .;
. = ALIGN(4);
.bss :
. = ALIGN(4);
.bss :
{
*(.bss)
}
. = ALIGN(4);
__bss_end = .;
}

2
board/dk1c20/vectors.S
View File

@ -120,5 +120,3 @@ _vectors:
.long _def_xhandler@h /* Vector 61 */
.long _def_xhandler@h /* Vector 62 */
.long _def_xhandler@h /* Vector 63 */

22
board/esd/common/xilinx_jtag/lenval.c
View File

@ -64,7 +64,7 @@ long value( lenVal* plvValue )
* Returns: void.
*****************************************************************************/
void initLenVal( lenVal* plv,
long lValue )
long lValue )
{
plv->len = 1;
plv->val[0] = (unsigned char)lValue;
@ -79,8 +79,8 @@ void initLenVal( lenVal* plv,
* Returns: short - 0 = mismatch; 1 = equal.
*****************************************************************************/
short EqualLenVal( lenVal* plvTdoExpected,
lenVal* plvTdoCaptured,
lenVal* plvTdoMask )
lenVal* plvTdoCaptured,
lenVal* plvTdoMask )
{
short sEqual;
short sIndex;
@ -120,8 +120,8 @@ short EqualLenVal( lenVal* plvTdoExpected,
* Returns: short - the bit value.
*****************************************************************************/
short RetBit( lenVal* plv,
int iByte,
int iBit )
int iByte,
int iBit )
{
/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
@ -139,9 +139,9 @@ short RetBit( lenVal* plv,
* Returns: void.
*****************************************************************************/
void SetBit( lenVal* plv,
int iByte,
int iBit,
short sVal )
int iByte,
int iBit,
short sVal )
{
unsigned char ucByteVal;
unsigned char ucBitMask;
@ -166,8 +166,8 @@ void SetBit( lenVal* plv,
* Returns: void.
*****************************************************************************/
void addVal( lenVal* plvResVal,
lenVal* plvVal1,
lenVal* plvVal2 )
lenVal* plvVal1,
lenVal* plvVal2 )
{
unsigned char ucCarry;
unsigned short usSum;
@ -204,7 +204,7 @@ void addVal( lenVal* plvResVal,
* Returns: void.
*****************************************************************************/
void readVal( lenVal* plv,
short sNumBytes )
short sNumBytes )
{
unsigned char* pucVal;

170
board/esd/common/xilinx_jtag/micro.c
View File

@ -114,20 +114,20 @@ extern int filesize;
#ifdef DEBUG_MODE
#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat ); }
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat ); }
#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat, arg1 ); }
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat, arg1 ); }
#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat, arg1, arg2 ); }
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat, arg1, arg2 ); }
#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat, arg1, arg2, arg3 ); }
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
printf( pzFormat, arg1, arg2, arg3 ); }
#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
xsvfPrintLenVal(plenVal); }
{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
xsvfPrintLenVal(plenVal); }
#else /* !DEBUG_MODE */
#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
@ -327,68 +327,68 @@ TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] =
#ifdef DEBUG_MODE
char* xsvf_pzCommandName[] =
{
"XCOMPLETE",
"XTDOMASK",
"XSIR",
"XSDR",
"XRUNTEST",
"Reserved5",
"Reserved6",
"XREPEAT",
"XSDRSIZE",
"XSDRTDO",
"XSETSDRMASKS",
"XSDRINC",
"XSDRB",
"XSDRC",
"XSDRE",
"XSDRTDOB",
"XSDRTDOC",
"XSDRTDOE",
"XSTATE",
"XENDIR",
"XENDDR",
"XSIR2",
"XCOMMENT",
"XWAIT"
"XCOMPLETE",
"XTDOMASK",
"XSIR",
"XSDR",
"XRUNTEST",
"Reserved5",
"Reserved6",
"XREPEAT",
"XSDRSIZE",
"XSDRTDO",
"XSETSDRMASKS",
"XSDRINC",
"XSDRB",
"XSDRC",
"XSDRE",
"XSDRTDOB",
"XSDRTDOC",
"XSDRTDOE",
"XSTATE",
"XENDIR",
"XENDDR",
"XSIR2",
"XCOMMENT",
"XWAIT"
};
char* xsvf_pzErrorName[] =
{
"No error",
"ERROR: Unknown",
"ERROR: TDO mismatch",
"ERROR: TDO mismatch and exceeded max retries",
"ERROR: Unsupported XSVF command",
"ERROR: Illegal state specification",
"ERROR: Data overflows allocated MAX_LEN buffer size"
"No error",
"ERROR: Unknown",
"ERROR: TDO mismatch",
"ERROR: TDO mismatch and exceeded max retries",
"ERROR: Unsupported XSVF command",
"ERROR: Illegal state specification",
"ERROR: Data overflows allocated MAX_LEN buffer size"
};
char* xsvf_pzTapState[] =
{
"RESET", /* 0x00 */
"RUNTEST/IDLE", /* 0x01 */
"DRSELECT", /* 0x02 */
"DRCAPTURE", /* 0x03 */
"DRSHIFT", /* 0x04 */
"DREXIT1", /* 0x05 */
"DRPAUSE", /* 0x06 */
"DREXIT2", /* 0x07 */
"DRUPDATE", /* 0x08 */
"IRSELECT", /* 0x09 */
"IRCAPTURE", /* 0x0A */
"IRSHIFT", /* 0x0B */
"IREXIT1", /* 0x0C */
"IRPAUSE", /* 0x0D */
"IREXIT2", /* 0x0E */
"IRUPDATE" /* 0x0F */
"RESET", /* 0x00 */
"RUNTEST/IDLE", /* 0x01 */
"DRSELECT", /* 0x02 */
"DRCAPTURE", /* 0x03 */
"DRSHIFT", /* 0x04 */
"DREXIT1", /* 0x05 */
"DRPAUSE", /* 0x06 */
"DREXIT2", /* 0x07 */
"DRUPDATE", /* 0x08 */
"IRSELECT", /* 0x09 */
"IRCAPTURE", /* 0x0A */
"IRSHIFT", /* 0x0B */
"IREXIT1", /* 0x0C */
"IRPAUSE", /* 0x0D */
"IREXIT2", /* 0x0E */
"IRUPDATE" /* 0x0F */
};
#endif /* DEBUG_MODE */
//#ifdef DEBUG_MODE
// FILE* in; /* Legacy DEBUG_MODE file pointer */
/*#ifdef DEBUG_MODE */
/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */
int xsvf_iDebugLevel;
//#endif /* DEBUG_MODE */
/*#endif /XXX* DEBUG_MODE */
/*============================================================================
* Utility Functions
@ -493,7 +493,7 @@ void xsvfTmsTransition( short sTms )
* Returns: int - 0 = success; otherwise error.
*****************************************************************************/
int xsvfGotoTapState( unsigned char* pucTapState,
unsigned char ucTargetState )
unsigned char ucTargetState )
{
int i;
int iErrorCode;
@ -708,9 +708,9 @@ int xsvfGotoTapState( unsigned char* pucTapState,
* Returns: void.
*****************************************************************************/
void xsvfShiftOnly( long lNumBits,
lenVal* plvTdi,
lenVal* plvTdoCaptured,
int iExitShift )
lenVal* plvTdi,
lenVal* plvTdoCaptured,
int iExitShift )
{
unsigned char* pucTdi;
unsigned char* pucTdo;
@ -796,15 +796,15 @@ void xsvfShiftOnly( long lNumBits,
* is NOT all zeros and sMatch==1.
*****************************************************************************/
int xsvfShift( unsigned char* pucTapState,
unsigned char ucStartState,
long lNumBits,
lenVal* plvTdi,
lenVal* plvTdoCaptured,
lenVal* plvTdoExpected,
lenVal* plvTdoMask,
unsigned char ucEndState,
long lRunTestTime,
unsigned char ucMaxRepeat )
unsigned char ucStartState,
long lNumBits,
lenVal* plvTdi,
lenVal* plvTdoCaptured,
lenVal* plvTdoExpected,
lenVal* plvTdoMask,
unsigned char ucEndState,
long lRunTestTime,
unsigned char ucMaxRepeat )
{
int iErrorCode;
int iMismatch;
@ -935,15 +935,15 @@ int xsvfShift( unsigned char* pucTapState,
* Returns: int - 0 = success; otherwise TDO mismatch.
*****************************************************************************/
int xsvfBasicXSDRTDO( unsigned char* pucTapState,
long lShiftLengthBits,
short sShiftLengthBytes,
lenVal* plvTdi,
lenVal* plvTdoCaptured,
lenVal* plvTdoExpected,
lenVal* plvTdoMask,
unsigned char ucEndState,
long lRunTestTime,
unsigned char ucMaxRepeat )
long lShiftLengthBits,
short sShiftLengthBytes,
lenVal* plvTdi,
lenVal* plvTdoCaptured,
lenVal* plvTdoExpected,
lenVal* plvTdoMask,
unsigned char ucEndState,
long lRunTestTime,
unsigned char ucMaxRepeat )
{
readVal( plvTdi, sShiftLengthBytes );
if ( plvTdoExpected )
@ -968,9 +968,9 @@ int xsvfBasicXSDRTDO( unsigned char* pucTapState,
*****************************************************************************/
#ifdef XSVF_SUPPORT_COMPRESSION
void xsvfDoSDRMasking( lenVal* plvTdi,
lenVal* plvNextData,
lenVal* plvAddressMask,
lenVal* plvDataMask )
lenVal* plvNextData,
lenVal* plvAddressMask,
lenVal* plvDataMask )
{
int i;
unsigned char ucTdi;

128
board/esd/common/xilinx_jtag/micro.h
View File

@ -1,64 +1,64 @@
/*
* (C) Copyright 2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*****************************************************************************
* File: micro.h
* Description: This header file contains the function prototype to the
* primary interface function for the XSVF player.
* Usage: FIRST - PORTS.C
* Customize the ports.c function implementations to establish
* the correct protocol for communicating with your JTAG ports
* (setPort() and readTDOBit()) and tune the waitTime() delay
* function. Also, establish access to the XSVF data source
* in the readByte() function.
* FINALLY - Call xsvfExecute().
*****************************************************************************/
#ifndef XSVF_MICRO_H
#define XSVF_MICRO_H
/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
#define XSVF_LEGACY_SUCCESS 1
#define XSVF_LEGACY_ERROR 0
/* 4.04 [NEW] Error codes for xsvfExecute. */
/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
#define XSVF_ERROR_NONE 0
#define XSVF_ERROR_UNKNOWN 1
#define XSVF_ERROR_TDOMISMATCH 2
#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
#define XSVF_ERROR_ILLEGALCMD 4
#define XSVF_ERROR_ILLEGALSTATE 5
#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
/* Insert new errors here */
#define XSVF_ERROR_LAST 7
/*****************************************************************************
* Function: xsvfExecute
* Description: Process, interpret, and apply the XSVF commands.
* See port.c:readByte for source of XSVF data.
* Parameters: none.
* Returns: int - For error codes see above.
*****************************************************************************/
int xsvfExecute(void);
#endif /* XSVF_MICRO_H */
/*
* (C) Copyright 2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*****************************************************************************
* File: micro.h
* Description: This header file contains the function prototype to the
* primary interface function for the XSVF player.
* Usage: FIRST - PORTS.C
* Customize the ports.c function implementations to establish
* the correct protocol for communicating with your JTAG ports
* (setPort() and readTDOBit()) and tune the waitTime() delay
* function. Also, establish access to the XSVF data source
* in the readByte() function.
* FINALLY - Call xsvfExecute().
*****************************************************************************/
#ifndef XSVF_MICRO_H
#define XSVF_MICRO_H
/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
#define XSVF_LEGACY_SUCCESS 1
#define XSVF_LEGACY_ERROR 0
/* 4.04 [NEW] Error codes for xsvfExecute. */
/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
#define XSVF_ERROR_NONE 0
#define XSVF_ERROR_UNKNOWN 1
#define XSVF_ERROR_TDOMISMATCH 2
#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
#define XSVF_ERROR_ILLEGALCMD 4
#define XSVF_ERROR_ILLEGALSTATE 5
#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
/* Insert new errors here */
#define XSVF_ERROR_LAST 7
/*****************************************************************************
* Function: xsvfExecute
* Description: Process, interpret, and apply the XSVF commands.
* See port.c:readByte for source of XSVF data.
* Parameters: none.
* Returns: int - For error codes see above.
*****************************************************************************/
int xsvfExecute(void);
#endif /* XSVF_MICRO_H */

2
board/esd/dp405/dp405.c
View File

@ -97,7 +97,7 @@ int checkboard (void)
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
unsigned char id1, id2;
puts ("Board: ");

4
board/icecube/flash.c
View File

@ -123,7 +123,7 @@ static flash_info_t *flash_get_info(ulong base)
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->size &&
if (info->size &&
info->start[0] <= base && base <= info->start[0] + info->size - 1)
break;
}
@ -260,7 +260,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
addr2 = (FPW *)((ulong)addr | 0x800000);
if (addr2 != addr &&
((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
/* Seems 2 banks are the same space (8Mb chip is installed,
/* Seems 2 banks are the same space (8Mb chip is installed,
* J24 in default position (CS0)). Disable this (first) bank.
*/
info->flash_id = FLASH_UNKNOWN;

4
board/icecube/icecube.c
View File

@ -174,9 +174,9 @@ void flash_preinit(void)
void flash_afterinit(ulong size)
{
if (size == 0x800000) { /* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(CFG_BOOTCS_START | size);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(CFG_BOOTCS_START | size, size);
}
}

20
board/ixdp425/u-boot.lds
View File

@ -26,29 +26,29 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = 0x00000000;
. = ALIGN(4);
. = ALIGN(4);
.text :
{
cpu/ixp/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = ALIGN(4);
.got : { *(.got) }
armboot_end_data = .;
. = ALIGN(4);
. = ALIGN(4);
bss_start = .;
.bss : { *(.bss) }
.bss : { *(.bss) }
bss_end = .;
armboot_end = .;

7
board/mpc8266ads/mpc8266ads.c
View File

@ -562,13 +562,13 @@ long int initdram(int board_type)
printf(", Using Bank Based Interleave\n");
#else
printf(", Using Page Based Interleave\n");
#endif
#endif
printf("\tTotal size: ");
/* this delay only needed for original 16MB DIMM...
/* this delay only needed for original 16MB DIMM...
* Not needed for any other memory configuration */
if ((sdram_size * chipselects) == (16 *1024 *1024))
udelay (250000);
udelay (250000);
return (sdram_size * chipselects);
/*return (16 * 1024 * 1024);*/
}
@ -584,4 +584,3 @@ void pci_init_board(void)
pci_mpc8250_init(&hose);
}
#endif

48
board/mpc8540ads/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o flash.o
SOBJS := init.o
#SOBJS :=
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

32
board/mpc8540ads/config.mk Normal file
View File

@ -0,0 +1,32 @@
# Modified by Xianghua Xiao, X.Xiao@motorola.com
# (C) Copyright 2002,Motorola Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# mpc8540ads board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1

539
board/mpc8540ads/flash.c Normal file
View File

@ -0,0 +1,539 @@
/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao,(X.Xiao@motorola.com)
*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Add support the Sharp chips on the mpc8260ads.
* I started with board/ip860/flash.c and made changes I found in
* the MTD project by David Schleef.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if !defined(CFG_NO_FLASH)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
#undef DEBUG
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int clear_block_lock_bit(vu_long * addr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size;
int i;
/* Init: enable write,
* or we cannot even write flash commands
*/
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
}
/* Static FLASH Bank configuration here - FIXME XXX */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size<<20);
}
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
&flash_info[0]);
#endif
#endif
return (size);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("Intel "); break;
case FLASH_MAN_SHARP: printf ("Sharp "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
break;
case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
break;
case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
break;
case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
break;
case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
ulong sector_offset;
#ifdef DEBUG
printf("Check flash at 0x%08x\n",(uint)addr);
#endif
/* Write "Intelligent Identifier" command: read Manufacturer ID */
*addr = 0x90909090;
udelay(20);
asm("sync");
value = addr[0] & 0x00FF00FF;
#ifdef DEBUG
printf("manufacturer=0x%x\n",(uint)value);
#endif
switch (value) {
case MT_MANUFACT: /* SHARP, MT or => Intel */
case INTEL_ALT_MANU:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
printf("unknown manufacturer: %x\n", (unsigned int)value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1] & 0x00FF00FF; /* device ID */
#ifdef DEBUG
printf("deviceID=0x%x\n",(uint)value);
#endif
switch (value) {
case (INTEL_ID_28F016S):
info->flash_id += FLASH_28F016SV;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F160S3):
info->flash_id += FLASH_28F160S3;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F320S3):
info->flash_id += FLASH_28F320S3;
info->sector_count = 64;
info->size = 0x00800000;
sector_offset = 0x20000;
break; /* => 2x4 MB */
case (INTEL_ID_28F640J3A):
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
sector_offset = 0x40000;
break; /* => 2x8 MB */
case SHARP_ID_28F016SCL:
case SHARP_ID_28F016SCZ:
info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
info->sector_count = 32;
info->size = 0x00800000;
sector_offset = 0x40000;
break; /* => 4x2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += sector_offset;
/* don't know how to check sector protection */
info->protect[i] = 0;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (vu_long *)info->start[0];
*addr = 0xFFFFFF; /* reset bank to read array mode */
asm("sync");
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
#ifdef DEBUG
printf("\nFlash Erase:\n");
#endif
/* Make Sure Block Lock Bit is not set. */
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
return 1;
}
/* Start erase on unprotected sectors */
#if defined(DEBUG)
printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
#endif
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
asm("sync");
last = start = get_timer (0);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
/* Single Block Erase Command */
*addr = 0x20202020;
asm("sync");
/* Confirm */
*addr = 0xD0D0D0D0;
asm("sync");
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
/* Resume Command, as per errata update */
*addr = 0xD0D0D0D0;
asm("sync");
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((*addr & 0x00800080) != 0x00800080) {
if(*addr & 0x00200020){
printf("Error in Block Erase - Lock Bit may be set!\n");
printf("Status Register = 0x%X\n", (uint)*addr);
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
/* reset to read mode */
*addr = 0xFFFFFFFF;
asm("sync");
}
}
printf ("flash erase done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)dest;
ulong start, csr;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Write Command */
*addr = 0x10101010;
asm("sync");
/* Write Data */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
flag = 0;
while (((csr = *addr) & 0x00800080) != 0x00800080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
}
if (csr & 0x40404040) {
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
flag = 1;
}
/* Clear Status Registers Command */
*addr = 0x50505050;
asm("sync");
/* Reset to read array mode */
*addr = 0xFFFFFFFF;
asm("sync");
return (flag);
}
/*-----------------------------------------------------------------------
* Clear Block Lock Bit, returns:
* 0 - OK
* 1 - Timeout
*/
static int clear_block_lock_bit(vu_long * addr)
{
ulong start, now;
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
*addr = 0x60606060;
asm("sync");
*addr = 0xd0d0d0d0;
asm("sync");
start = get_timer (0);
while((*addr & 0x00800080) != 0x00800080){
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
}
return 0;
}
#endif /* !CFG_NO_FLASH */

178
board/mpc8540ads/init.S Normal file
View File

@ -0,0 +1,178 @@
/*
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
.long 0x0a /* the following data table uses a few of 16 TLB entries */
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if defined(CFG_FLASH_PORT_WIDTH_16)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
#if !defined(CONFIG_SPD_EEPROM)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,9,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/* LAW(Local Access Window) configuration:
* 0000_0000-0800_0000: DDR(128M) -or- larger
* f000_0000-f3ff_ffff: PCI(256M)
* f400_0000-f7ff_ffff: RapidIO(128M)
* f800_0000-ffff_ffff: localbus(128M)
* f800_0000-fbff_ffff: LBC SDRAM(64M)
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
* fdf0_0000-fdff_ffff: CCSRBAR(1M)
* fe00_0000-ffff_ffff: Flash(32M)
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
* Window.
* Note: If flash is 8M at default position(last 8M),no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
#if !defined(CONFIG_RAM_AS_FLASH)
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x03
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
entry_end

265
board/mpc8540ads/mpc8540ads.c Normal file
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/*
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
long int fixed_sdram (void);
/* MPC8540ADS Board Status & Control Registers */
#if 0
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
#endif
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
return 0;
}
int checkboard (void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: Motorola MPC8540ADS Board\n");
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur= &immap->im_gur;
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
lbc->mrtpr = CFG_LBC_MRTPR;
asm("sync");
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
return (CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */

148
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/*
* (C) Copyright 2002,2003, Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/mpc8540ads/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
board/mpc8540ads/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

48
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#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o flash.o
SOBJS := init.o
#SOBJS :=
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

32
board/mpc8560ads/config.mk Normal file
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# Modified by Xianghua Xiao, X.Xiao@motorola.com
# (C) Copyright 2002,2003 Motorola Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# mpc8560ads board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1

539
board/mpc8560ads/flash.c Normal file
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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao,(X.Xiao@motorola.com)
*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Add support the Sharp chips on the mpc8260ads.
* I started with board/ip860/flash.c and made changes I found in
* the MTD project by David Schleef.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if !defined(CFG_NO_FLASH)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
#undef DEBUG
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int clear_block_lock_bit(vu_long * addr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size;
int i;
/* Init: enable write,
* or we cannot even write flash commands
*/
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
}
/* Static FLASH Bank configuration here - FIXME XXX */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size<<20);
}
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
&flash_info[0]);
#endif
#endif
return (size);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("Intel "); break;
case FLASH_MAN_SHARP: printf ("Sharp "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
break;
case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
break;
case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
break;
case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
break;
case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
ulong sector_offset;
#ifdef DEBUG
printf("Check flash at 0x%08x\n",(uint)addr);
#endif
/* Write "Intelligent Identifier" command: read Manufacturer ID */
*addr = 0x90909090;
udelay(20);
asm("sync");
value = addr[0] & 0x00FF00FF;
#ifdef DEBUG
printf("manufacturer=0x%x\n",(uint)value);
#endif
switch (value) {
case MT_MANUFACT: /* SHARP, MT or => Intel */
case INTEL_ALT_MANU:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
printf("unknown manufacturer: %x\n", (unsigned int)value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1] & 0x00FF00FF; /* device ID */
#ifdef DEBUG
printf("deviceID=0x%x\n",(uint)value);
#endif
switch (value) {
case (INTEL_ID_28F016S):
info->flash_id += FLASH_28F016SV;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F160S3):
info->flash_id += FLASH_28F160S3;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F320S3):
info->flash_id += FLASH_28F320S3;
info->sector_count = 64;
info->size = 0x00800000;
sector_offset = 0x20000;
break; /* => 2x4 MB */
case (INTEL_ID_28F640J3A):
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
sector_offset = 0x40000;
break; /* => 8 MB */
case SHARP_ID_28F016SCL:
case SHARP_ID_28F016SCZ:
info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
info->sector_count = 32;
info->size = 0x00800000;
sector_offset = 0x40000;
break; /* => 4x2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += sector_offset;
/* don't know how to check sector protection */
info->protect[i] = 0;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (vu_long *)info->start[0];
*addr = 0xFFFFFF; /* reset bank to read array mode */
asm("sync");
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
#ifdef DEBUG
printf("\nFlash Erase:\n");
#endif
/* Make Sure Block Lock Bit is not set. */
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
return 1;
}
/* Start erase on unprotected sectors */
#if defined(DEBUG)
printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
#endif
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
asm("sync");
last = start = get_timer (0);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
/* Single Block Erase Command */
*addr = 0x20202020;
asm("sync");
/* Confirm */
*addr = 0xD0D0D0D0;
asm("sync");
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
/* Resume Command, as per errata update */
*addr = 0xD0D0D0D0;
asm("sync");
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((*addr & 0x00800080) != 0x00800080) {
if(*addr & 0x00200020){
printf("Error in Block Erase - Lock Bit may be set!\n");
printf("Status Register = 0x%X\n", (uint)*addr);
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
/* reset to read mode */
*addr = 0xFFFFFFFF;
asm("sync");
}
}
printf ("flash erase done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)dest;
ulong start, csr;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Write Command */
*addr = 0x10101010;
asm("sync");
/* Write Data */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
flag = 0;
while (((csr = *addr) & 0x00800080) != 0x00800080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
}
if (csr & 0x40404040) {
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
flag = 1;
}
/* Clear Status Registers Command */
*addr = 0x50505050;
asm("sync");
/* Reset to read array mode */
*addr = 0xFFFFFFFF;
asm("sync");
return (flag);
}
/*-----------------------------------------------------------------------
* Clear Block Lock Bit, returns:
* 0 - OK
* 1 - Timeout
*/
static int clear_block_lock_bit(vu_long * addr)
{
ulong start, now;
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
*addr = 0x60606060;
asm("sync");
*addr = 0xd0d0d0d0;
asm("sync");
start = get_timer (0);
while((*addr & 0x00800080) != 0x00800080){
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
}
return 0;
}
#endif /* !CFG_NO_FLASH */

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board/mpc8560ads/init.S Normal file
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/*
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
.long 0x0a /* the following data table uses a few of 16 TLB entries */
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if defined(CFG_FLASH_PORT_WIDTH_16)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
#if !defined(CONFIG_SPD_EEPROM)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,9,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/* LAW(Local Access Window) configuration:
* 0000_0000-0800_0000: DDR(128M) -or- larger
* f000_0000-f3ff_ffff: PCI(256M)
* f400_0000-f7ff_ffff: RapidIO(128M)
* f800_0000-ffff_ffff: localbus(128M)
* f800_0000-fbff_ffff: LBC SDRAM(64M)
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
* fdf0_0000-fdff_ffff: CCSRBAR(1M)
* fe00_0000-ffff_ffff: Flash(32M)
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
* Window.
* Note: If flash is 8M at default position(last 8M),no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
#if !defined(CONFIG_RAM_AS_FLASH)
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x03
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
entry_end

445
board/mpc8560ads/mpc8560ads.c Normal file
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/*
* (C) Copyright 2003,Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
#include <miiphy.h>
long int fixed_sdram (void);
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* MPC8560ADS Board Status & Control Registers */
typedef struct bscr_ {
volatile unsigned char bcsr0;
volatile unsigned char bcsr1;
volatile unsigned char bcsr2;
volatile unsigned char bcsr3;
volatile unsigned char bcsr4;
volatile unsigned char bcsr5;
} bcsr_t;
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
return 0;
}
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
#endif
/* reset Giga bit Ethernet port if needed here */
/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
bcsr->bcsr2 &= ~FETH2_RST;
udelay(2);
bcsr->bcsr2 |= FETH2_RST;
udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
bcsr->bcsr3 &= ~FETH3_RST;
udelay(2);
bcsr->bcsr3 |= FETH3_RST;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
miiphy_reset(0x0); /* reset PHY */
miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}
int checkboard (void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: Motorola MPC8560ADS Board\n");
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur= &immap->im_gur;
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
lbc->mrtpr = CFG_LBC_MRTPR;
asm("sync");
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
return ( CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */

152
board/mpc8560ads/u-boot.lds Normal file
View File

@ -0,0 +1,152 @@
/*
* (C) Copyright 2002,2003,Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/mpc8560ads/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
board/mpc8560ads/init.o (.text)
cpu/mpc85xx/commproc.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/serial_scc.o (.text)
cpu/mpc85xx/ether_fcc.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

9
board/mpl/common/flash.c
View File

@ -86,14 +86,14 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
* The first thing we do is to map the Flash CS to the Flash area and
* the MPS CS to the MPS area. Since the flash size is unknown at this
* point, we use the max flash size and the lowest flash address as base.
*
*
* After flash detection we adjust the size of the CS area accordingly.
* The board_init_r will fill in wrong values in the board init structure,
* but this will be fixed in the misc_init_r routine:
* bd->bi_flashstart=0-flash_info[0].size
* bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
* bd->bi_flashoffset=0
*
*
*/
int get_boot_mode(void)
{
@ -152,7 +152,6 @@ void setup_cs_reloc(void)
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1,flashcr, size_reg;
@ -207,7 +206,7 @@ unsigned long flash_init (void)
case 32: i=5; break; /* = 32MB */
case 64: i=6; break; /* = 64MB */
case 128: i=7; break; /*= 128MB */
default:
default:
printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
while(1);
}
@ -345,7 +344,7 @@ void flash_print_info (flash_info_t *info)
/*-----------------------------------------------------------------------
*/
/*

1
board/mpl/vcma9/cmd_vcma9.c
View File

@ -178,4 +178,3 @@ U_BOOT_CMD(
"vcma9 - VCMA9 specific commands\n",
"flash mem [SrcAddr]\n - updates U-Boot with image in memory\n"
);

8
board/mpl/vcma9/memsetup.S
View File

@ -153,14 +153,14 @@ memsetup:
ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
mov r4, #SDRAMDATA1_END-SDRAMDATA
/* calculate start and end point */
mla r0, r3, r4, r0
mla r0, r3, r4, r0
add r2, r0, r4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
/* everything is fine now */
mov pc, lr
@ -194,7 +194,7 @@ SDRAMDATA1_END:
.word 0x32 + BURST_EN
.word 0x30
.word 0x30
/* 2Mx8x4 (not implemented yet) */
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
@ -202,7 +202,7 @@ SDRAMDATA1_END:
.word 0x32 + BURST_EN
.word 0x30
.word 0x30
/* 4Mx8x2 (not implemented yet) */
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))

12
board/mpl/vcma9/vcma9.c
View File

@ -190,21 +190,21 @@ nand_init(void)
static u8 Get_PLD_ID(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
return(pld->ID);
}
static u8 Get_PLD_BOARD(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
return(pld->BOARD);
}
static u8 Get_PLD_SDRAM(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
return(pld->SDRAM);
}
@ -253,7 +253,7 @@ static ulong Get_SDRAM_ChipSize(void)
case 2: return 8 * (1024*1024);
case 3: return 8 * (1024*1024);
default: return 0;
}
}
}
static const char * Get_SDRAM_ChipGeom(void)
{
@ -339,10 +339,10 @@ int overwrite_console(void)
* Print VCMA9 Info
************************************************************************/
void print_vcma9_info(void)
{
{
unsigned char s[50];
int i;
if ((i = getenv_r("serial#", s, 32)) < 0) {
puts ("### No HW ID - assuming VCMA9");
printf("i %d", i*24);

7
board/omap1610inn/flash.c
View File

@ -54,7 +54,6 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define mb() __asm__ __volatile__ ("" : : : "memory")
/* Flash Organization Structure */
typedef struct OrgDef {
unsigned int sector_number;
@ -240,8 +239,6 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
}
/* unprotects a sector for write and erase
* on some intel parts, this unprotects the entire chip, but it
* wont hurt to call this additional times per sector...
@ -298,8 +295,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
}
start = get_timer (0);
last = start;
@ -326,7 +321,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
if (get_timer_masked () >
if (get_timer_masked () >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */

8
board/omap1610inn/platform.S
View File

@ -132,8 +132,6 @@ watch2Wait:
bne watch2Wait
/* Set memory timings corresponding to the new clock speed */
/* Check execution location to determine current execution location
@ -275,7 +273,7 @@ REG_ARM_CKCTL: /* 16 bits */
REG_ARM_IDLECT3: /* 16 bits */
.word 0xfffece24
REG_ARM_IDLECT2: /* 16 bits */
.word 0xfffece08
.word 0xfffece08
REG_ARM_IDLECT1: /* 16 bits */
.word 0xfffece04
@ -293,7 +291,7 @@ REG_WSPRDOG:
.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
.word 0xfffeb034
.word 0xfffeb034
WSPRDOG_VAL1:
.word 0x0000aaaa
@ -342,7 +340,7 @@ REG_WATCHDOG:
/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
.word 0x001200f4
.word 0x001200f4
DLL_LRD_CONTROL_VAL:
.word 0x00800002

4
board/omap1610inn/u-boot.lds
View File

@ -39,11 +39,11 @@ SECTIONS
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
armboot_end_data = .;
. = ALIGN(4);
.bss : { *(.bss) }

32
board/sacsng/sacsng.c
View File

@ -533,11 +533,11 @@ int misc_init_r(void)
setenv("Daq128xSampling", "1");
}
/*
* Display the ADC/DAC clocking information
/*
* Display the ADC/DAC clocking information
*/
if (!quiet) {
Daq_Display_Clocks();
Daq_Display_Clocks();
}
/*
@ -572,9 +572,9 @@ int misc_init_r(void)
* 3) Write the I2C address to register 6
* 4) Enable address matching by setting the MSB in register 7
*/
if (!quiet) {
printf("Initializing the ADC...\n");
printf("Initializing the ADC...\n");
}
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
@ -720,7 +720,7 @@ int misc_init_r(void)
I2C_TRISTATE;
if (!quiet) {
printf("\n");
printf("\n");
}
#ifdef CONFIG_ETHER_LOOPBACK_TEST
@ -795,14 +795,14 @@ void show_boot_progress (int status)
if(status > 0) {
last_boot_progress = status;
} else {
/*
/*
* If a specific failure code is given, flash this code
* else just use the last success code we've seen
*/
if(status < -1)
last_boot_progress = -status;
/*
/*
* Flash this code 5 times
*/
for(j=0; j<5; j++) {
@ -813,15 +813,15 @@ void show_boot_progress (int status)
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
flash_code(last_boot_progress, 5, 3);
/*
* Delay 5 seconds between repetitions,
* with the fault LED blinking
/*
* Delay 5 seconds between repetitions,
* with the fault LED blinking
*/
for(i=0; i<5; i++) {
status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
udelay(500000);
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
udelay(500000);
status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
udelay(500000);
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
udelay(500000);
}
}

1
board/sl8245/sl8245.c
View File

@ -92,4 +92,3 @@ void pci_init_board(void)
{
pci_mpc824x_init(&hose);
}

4
board/tqm8xx/tqm8xx.c
View File

@ -368,8 +368,8 @@ long int initdram (int board_type)
memctl->memc_or5 = CFG_OR5_ISP1362;
memctl->memc_br5 = CFG_BR5_ISP1362;
#endif /* CONFIG_ISP1362_USB */
return (size_b0 + size_b1);
}

4
board/trab/memsetup.S
View File

@ -48,8 +48,8 @@
#define BWSCON 0x14000000
/* Bank0 */
#define B0_Tacs 0x0 /* 0 clk */
#define B0_Tcos 0x0 /* 0 clk */
#define B0_Tacs 0x3 /* 4 clk */
#define B0_Tcos 0x3 /* 4 clk */
#define B0_Tacc 0x7 /* 14 clk */
#define B0_Tcoh 0x0 /* 0 clk */
#define B0_Tah 0x0 /* 0 clk */

2
board/trab/trab_fkt.c
View File

@ -885,7 +885,6 @@ int do_thermo (char **argv)
}
int do_touch (char **argv)
{
int x, y;
@ -1039,7 +1038,6 @@ static void touch_read_x_y (int *px, int *py)
}
int do_rs485 (char **argv)
{
int timeout;

66
board/trab/tsc2000.c
View File

@ -38,7 +38,7 @@ void spi_init(void)
int i;
/* Configure I/O ports. */
gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
@ -48,7 +48,7 @@ void spi_init(void)
spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
CPHA=1 */
CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
@ -73,7 +73,7 @@ void tsc2000_write(unsigned short reg, unsigned short data)
SET_CS_TOUCH();
command = reg;
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
spi->ch[0].SPTDAT = (command & 0x00FF);
spi_wait_transmit_done();
@ -94,12 +94,12 @@ unsigned short tsc2000_read (unsigned short reg)
SET_CS_TOUCH();
command = 0x8000 | reg;
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
spi->ch[0].SPTDAT = (command & 0x00FF);
spi_wait_transmit_done();
spi->ch[0].SPTDAT = 0xFF;
spi->ch[0].SPTDAT = 0xFF;
spi_wait_transmit_done();
data = spi->ch[0].SPRDAT;
spi->ch[0].SPTDAT = 0xFF;
@ -112,7 +112,7 @@ unsigned short tsc2000_read (unsigned short reg)
void tsc2000_set_mux (unsigned int channel)
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
@ -189,7 +189,7 @@ void tsc2000_set_mux (unsigned int channel)
void tsc2000_set_range (unsigned int range)
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
switch (range) {
case 1:
@ -216,8 +216,8 @@ u16 tsc2000_read_channel (unsigned int channel)
udelay(3 * TSC2000_DELAY_BASE);
tsc2000_write(TSC2000_REG_ADC, 0x2036);
adc_wait_conversion_done ();
res = tsc2000_read(TSC2000_REG_AUX1);
adc_wait_conversion_done ();
res = tsc2000_read(TSC2000_REG_AUX1);
return res;
}
@ -225,36 +225,36 @@ u16 tsc2000_read_channel (unsigned int channel)
s32 tsc2000_contact_temp (void)
{
long adc_pt1000, offset;
long u_pt1000;
long u_pt1000;
long contact_temp;
tsc2000_reg_init ();
tsc2000_reg_init ();
tsc2000_set_range (3);
adc_pt1000 = tsc2000_read_channel (14);
debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
adc_pt1000 = tsc2000_read_channel (14);
debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
offset = tsc2000_read_channel (15);
debug ("read channel 15 (offset): %ld\n", offset);
offset = tsc2000_read_channel (15);
debug ("read channel 15 (offset): %ld\n", offset);
/*
* Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
* x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
* x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
* error correction Values err_vref and err_amp3 are assumed as 0 in
* u-boot, because this could cause only a very small error (< 1%).
*/
u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
debug ("u_pt1000: %ld\n", u_pt1000);
/*
* Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
* x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
* x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
* error correction Values err_vref and err_amp3 are assumed as 0 in
* u-boot, because this could cause only a very small error (< 1%).
*/
u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
debug ("u_pt1000: %ld\n", u_pt1000);
if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
&contact_temp) == -1) {
printf ("%s: error interpolating PT1000 vlaue\n",
__FUNCTION__);
return (-1000);
}
debug ("contact_temp: %ld\n", contact_temp);
if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
&contact_temp) == -1) {
printf ("%s: error interpolating PT1000 vlaue\n",
__FUNCTION__);
return (-1000);
}
debug ("contact_temp: %ld\n", contact_temp);
return contact_temp;
}
@ -262,7 +262,7 @@ s32 tsc2000_contact_temp (void)
void tsc2000_reg_init (void)
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
tsc2000_write(TSC2000_REG_ADC, 0x2036);
tsc2000_write(TSC2000_REG_REF, 0x0011);
@ -315,5 +315,5 @@ int tsc2000_interpolate(long value, long data[][2], long *result)
void adc_wait_conversion_done(void)
{
while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
}

2
board/trab/tsc2000.h
View File

@ -112,7 +112,7 @@
#define TSC2000_NO_SENSOR -0x10000
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on
* TRAB */
* TRAB */
void tsc2000_write(unsigned short, unsigned short);
unsigned short tsc2000_read (unsigned short);

15
common/cmd_bdinfo.c
View File

@ -55,7 +55,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num ("flashoffset", bd->bi_flashoffset );
print_num ("sramstart", bd->bi_sramstart );
print_num ("sramsize", bd->bi_sramsize );
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_E500)
print_num ("immr_base", bd->bi_immr_base );
#endif
print_num ("bootflags", bd->bi_bootflags );
@ -66,13 +66,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP */
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
print_str ("brgfreq", strmhz(buf, bd->bi_brgfreq));
#endif
print_str ("intfreq", strmhz(buf, bd->bi_intfreq));
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
@ -81,12 +81,19 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB)
#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
|| (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
printf ("\neth1addr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
}
#endif /* CONFIG_PN62 */
#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
printf ("\neth2addr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
}
#endif
#ifdef CONFIG_HERMES
print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
#endif

5
common/cmd_bootm.c
View File

@ -558,7 +558,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
/* convert all clock information to MHz */
kbd->bi_intfreq /= 1000000L;
kbd->bi_busfreq /= 1000000L;
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
kbd->bi_cpmfreq /= 1000000L;
kbd->bi_brgfreq /= 1000000L;
kbd->bi_sccfreq /= 1000000L;
@ -758,7 +758,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
SHOW_BOOT_PROGRESS (15);
#ifdef CFG_INIT_RAM_LOCK
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
unlock_ram_in_cache();
#endif
/*
@ -1341,4 +1341,3 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag,
}
#endif /* CONFIG_LYNXKDI */

4
common/cmd_fat.c
View File

@ -37,8 +37,6 @@
#include <fat.h>
block_dev_desc_t *get_dev (char* ifname, int dev)
{
#if (CONFIG_COMMANDS & CFG_CMD_IDE)
@ -121,8 +119,6 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
fatload, 6, 0, do_fat_fsload,
"fatload - load binary file from a dos filesystem\n",

2
common/console.c
View File

@ -495,7 +495,7 @@ int console_init_r (void)
#ifdef CONFIG_SPLASH_SCREEN
/* suppress all output if splash screen is enabled and we have
a bmp to display */
a bmp to display */
if (getenv("splashimage") != NULL)
outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
#endif

1
common/lynxkdi.c
View File

@ -67,4 +67,3 @@ void lynxkdi_boot ( image_header_t *hdr )
#endif
#endif /* CONFIG_LYNXKDI */

136
cpu/arm920t/usb_ohci.c
View File

@ -157,14 +157,14 @@ static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffe
dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
str,
sohci_get_current_frame_number (dev),
usb_pipedevice (pipe),
usb_pipeendpoint (pipe),
usb_pipeout (pipe)? 'O': 'I',
usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
(usb_pipecontrol (pipe)? "CTRL": "BULK"),
purb->actual_length,
transfer_len, dev->status);
sohci_get_current_frame_number (dev),
usb_pipedevice (pipe),
usb_pipeendpoint (pipe),
usb_pipeout (pipe)? 'O': 'I',
usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
(usb_pipecontrol (pipe)? "CTRL": "BULK"),
purb->actual_length,
transfer_len, dev->status);
#ifdef OHCI_VERBOSE_DEBUG
if (!small) {
int i, len;
@ -585,7 +585,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
if (ed->state == ED_NEW) {
ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
/* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
ed->hwTailP = m32_swap (td);
ed->hwHeadP = ed->hwTailP;
@ -669,13 +669,13 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
void *data;
int cnt = 0;
__u32 info = 0;
unsigned int toggle = 0;
unsigned int toggle = 0;
/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
toggle = TD_T_DATA0;
toggle = TD_T_DATA0;
usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
}
urb->td_cnt = 0;
@ -731,11 +731,11 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
static void dl_transfer_length(td_t * td)
{
__u32 tdINFO, tdBE, tdCBP;
urb_priv_t *lurb_priv = &urb_priv;
urb_priv_t *lurb_priv = &urb_priv;
tdINFO = m32_swap (td->hwINFO);
tdBE = m32_swap (td->hwBE);
tdCBP = m32_swap (td->hwCBP);
tdBE = m32_swap (td->hwBE);
tdCBP = m32_swap (td->hwCBP);
if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
@ -759,7 +759,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
__u32 td_list_hc;
td_t *td_rev = NULL;
td_t *td_list = NULL;
urb_priv_t *lurb_priv = NULL;
urb_priv_t *lurb_priv = NULL;
td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
ohci->hcca->done_head = 0;
@ -794,42 +794,42 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
/* td done list */
static int dl_done_list (ohci_t *ohci, td_t *td_list)
{
td_t *td_list_next = NULL;
td_t *td_list_next = NULL;
ed_t *ed;
int cc = 0;
int stat = 0;
/* urb_t *urb; */
urb_priv_t *lurb_priv;
__u32 tdINFO, edHeadP, edTailP;
__u32 tdINFO, edHeadP, edTailP;
while (td_list) {
td_list_next = td_list->next_dl_td;
while (td_list) {
td_list_next = td_list->next_dl_td;
lurb_priv = &urb_priv;
tdINFO = m32_swap (td_list->hwINFO);
lurb_priv = &urb_priv;
tdINFO = m32_swap (td_list->hwINFO);
ed = td_list->ed;
ed = td_list->ed;
dl_transfer_length(td_list);
dl_transfer_length(td_list);
/* error code of transfer */
cc = TD_CC_GET (tdINFO);
/* error code of transfer */
cc = TD_CC_GET (tdINFO);
if (cc != 0) {
dbg("ConditionCode %#x", cc);
stat = cc_to_error[cc];
}
if (ed->state != ED_NEW) {
edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
edTailP = m32_swap (ed->hwTailP);
if (ed->state != ED_NEW) {
edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
edTailP = m32_swap (ed->hwTailP);
/* unlink eds if they are not busy */
if ((edHeadP == edTailP) && (ed->state == ED_OPER))
ep_unlink (ohci, ed);
}
if ((edHeadP == edTailP) && (ed->state == ED_OPER))
ep_unlink (ohci, ed);
}
td_list = td_list_next;
}
td_list = td_list_next;
}
return stat;
}
@ -851,9 +851,9 @@ static __u8 root_hub_dev_des[] =
0x00, /* __u16 idVendor; */
0x00,
0x00, /* __u16 idProduct; */
0x00,
0x00,
0x00, /* __u16 bcdDevice; */
0x00,
0x00,
0x00, /* __u8 iManufacturer; */
0x01, /* __u8 iProduct; */
0x00, /* __u8 iSerialNumber; */
@ -872,7 +872,7 @@ static __u8 root_hub_config_des[] =
0x01, /* __u8 bConfigurationValue; */
0x00, /* __u8 iConfiguration; */
0x40, /* __u8 bmAttributes;
Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
0x00, /* __u8 MaxPower; */
/* interface */
@ -890,9 +890,9 @@ static __u8 root_hub_config_des[] =
0x07, /* __u8 ep_bLength; */
0x05, /* __u8 ep_bDescriptorType; Endpoint */
0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
0x03, /* __u8 ep_bmAttributes; Interrupt */
0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
0x00,
0x03, /* __u8 ep_bmAttributes; Interrupt */
0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
0x00,
0xff /* __u8 ep_bInterval; 255 ms */
};
@ -984,7 +984,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
int stat = 0;
__u32 datab[4];
__u8 *data_buf = (__u8 *)datab;
__u16 bmRType_bReq;
__u16 bmRType_bReq;
__u16 wValue;
__u16 wIndex;
__u16 wLength;
@ -1176,7 +1176,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
len = min_t(int, len, leni);
if (data != data_buf)
memcpy (data, data_buf, len);
dev->act_len = len;
dev->act_len = len;
dev->status = stat;
#ifdef DEBUG
@ -1226,7 +1226,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
wait_ms(10);
/* ohci_dump_status(&gohci); */
/* allow more time for a BULK device to react - some are slow */
#define BULK_TO 5000 /* timeout in milliseconds */
if (usb_pipetype (pipe) == PIPE_BULK)
@ -1277,7 +1277,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
}
dev->status = stat;
dev->act_len = transfer_len;
dev->act_len = transfer_len;
#ifdef DEBUG
pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
@ -1362,7 +1362,7 @@ static int hc_reset (ohci_t *ohci)
ohci->slot_name,
readl (&ohci->regs->control));
/* Reset USB (needed by some controllers) */
/* Reset USB (needed by some controllers) */
writel (0, &ohci->regs->control);
/* HC Reset requires max 10 us delay */
@ -1385,8 +1385,8 @@ static int hc_reset (ohci_t *ohci)
static int hc_start (ohci_t * ohci)
{
__u32 mask;
unsigned int fminterval;
__u32 mask;
unsigned int fminterval;
ohci->disabled = 1;
@ -1398,16 +1398,16 @@ static int hc_start (ohci_t * ohci)
writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
fminterval = 0x2edf;
fminterval = 0x2edf;
writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
writel (fminterval, &ohci->regs->fminterval);
writel (0x628, &ohci->regs->lsthresh);
/* start controller operations */
ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
/* start controller operations */
ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
ohci->disabled = 0;
writel (ohci->hc_control, &ohci->regs->control);
writel (ohci->hc_control, &ohci->regs->control);
/* disable all interrupts */
mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
@ -1447,7 +1447,7 @@ hc_interrupt (void)
{
ohci_t *ohci = &gohci;
struct ohci_regs *regs = ohci->regs;
int ints;
int ints;
int stat = -1;
if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
@ -1534,17 +1534,17 @@ int usb_lowlevel_init(void)
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
memset (&gohci, 0, sizeof (ohci_t));
memset (&urb_priv, 0, sizeof (urb_priv_t));
@ -1568,7 +1568,7 @@ int usb_lowlevel_init(void)
}
ptd = gtd;
gohci.hcca = phcca;
memset (phcca, 0, sizeof (struct ohci_hcca));
memset (phcca, 0, sizeof (struct ohci_hcca));
gohci.disabled = 1;
gohci.sleeping = 0;
@ -1580,8 +1580,8 @@ int usb_lowlevel_init(void)
if (hc_reset (&gohci) < 0) {
hc_release_ohci (&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
return -1;
}
@ -1592,8 +1592,8 @@ int usb_lowlevel_init(void)
if (hc_start (&gohci) < 0) {
err ("can't start usb-%s", gohci.slot_name);
hc_release_ohci (&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
return -1;
}

1
cpu/arm920t/usb_ohci.h
View File

@ -224,7 +224,6 @@ struct ohci_regs {
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
/* Virtual Root HUB */
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */

1
cpu/arm926ejs/interrupts.c
View File

@ -79,7 +79,6 @@ int disable_interrupts (void)
#endif
void bad_mode (void)
{
panic ("Resetting CPU ...\n");

8
cpu/arm926ejs/start.S
View File

@ -31,7 +31,6 @@
*/
#include <config.h>
#include <version.h>
@ -144,7 +143,7 @@ reset:
msr cpsr,r0
/*
/*
* turn off the watchdog, unlock/diable sequence
*/
mov r1, #0xF5
@ -154,9 +153,6 @@ reset:
strh r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
@ -411,7 +407,7 @@ fiq:
.globl reset_cpu
reset_cpu:
ldr r1, rstctl1 /* get clkm1 reset ctl */
mov r3, #0x0
mov r3, #0x0
strh r3, [r1] /* clear it */
mov r3, #0x8
strh r3, [r1] /* force dsp+arm reset */

1
cpu/ixp/interrupts.c
View File

@ -60,7 +60,6 @@ int disable_interrupts (void)
#endif
void bad_mode (void)
{
panic ("Resetting CPU ...\n");

96
cpu/ixp/start.S
View File

@ -31,37 +31,37 @@
#include <version.h>
#include <asm/arch/ixp425.h>
#define MMU_Control_M 0x001 // Enable MMU
#define MMU_Control_A 0x002 // Enable address alignment faults
#define MMU_Control_C 0x004 // Enable cache
#define MMU_Control_W 0x008 // Enable write-buffer
#define MMU_Control_P 0x010 // Compatability: 32 bit code
#define MMU_Control_D 0x020 // Compatability: 32 bit data
#define MMU_Control_L 0x040 // Compatability:
#define MMU_Control_B 0x080 // Enable Big-Endian
#define MMU_Control_S 0x100 // Enable system protection
#define MMU_Control_R 0x200 // Enable ROM protection
#define MMU_Control_I 0x1000 // Enable Instruction cache
#define MMU_Control_X 0x2000 // Set interrupt vectors at 0xFFFF0000
#define MMU_Control_M 0x001 /* Enable MMU */
#define MMU_Control_A 0x002 /* Enable address alignment faults */
#define MMU_Control_C 0x004 /* Enable cache */
#define MMU_Control_W 0x008 /* Enable write-buffer */
#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
#define MMU_Control_L 0x040 /* Compatability: */
#define MMU_Control_B 0x080 /* Enable Big-Endian */
#define MMU_Control_S 0x100 /* Enable system protection */
#define MMU_Control_R 0x200 /* Enable ROM protection */
#define MMU_Control_I 0x1000 /* Enable Instruction cache */
#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
/*
* Macro definitions
*/
// Delay a bit
.macro DELAY_FOR cycles, reg0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
.endm
/* Delay a bit */
.macro DELAY_FOR cycles, reg0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
.endm
// wait for coprocessor write complete
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.globl _start
_start: b reset
@ -160,15 +160,15 @@ reset:
/* disable mmu, set big-endian */
mov r0, #0xf8
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
CPWAIT r0
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
@ -185,7 +185,7 @@ reset:
ldr r2, =IXP425_EXP_CS0
str r1, [r2]
/* make sure flash is visible at 0 */
/* make sure flash is visible at 0 */
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
orr r1, r1, #0x80000000
@ -204,7 +204,7 @@ reset:
mov r1, #3
ldr r4, =IXP425_SDR_IR
str r1, [r4]
DELAY_FOR 0x4000, r0
DELAY_FOR 0x4000, r0
/* set SDRAM internal refresh val */
ldr r1, =CFG_SDRAM_REFRESH_CNT
@ -235,31 +235,31 @@ reset:
DELAY_FOR 0x4000, r0
/* copy */
mov r0, #0
mov r4, r0
add r2, r0, #0x40000
mov r0, #0
mov r4, r0
add r2, r0, #0x40000
mov r1, #0x10000000
mov r5, r1
mov r5, r1
30:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r0, r2
bne 30b
ldr r3, [r0], #4
str r3, [r1], #4
cmp r0, r2
bne 30b
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
/* move flash to 0x50000000 */
/* move flash to 0x50000000 */
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
bic r1, r1, #0x80000000
@ -273,14 +273,14 @@ reset:
nop
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
/* enable I cache */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #MMU_Control_I
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* enable I cache */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #MMU_Control_I
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
mrs r0,cpsr /* set the cpu to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
@ -331,8 +331,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_start_armboot: .word start_armboot
/****************************************************************************/
/* */
/* Interrupt handling */

2
cpu/mpc5xxx/fec.c
View File

@ -847,7 +847,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
* a garbage after reset. When not using fec for booting
* the Linux fec driver will try to work with this garbage.
*/
tmp = getenv("ethaddr");

20
cpu/mpc5xxx/i2c.c
View File

@ -133,13 +133,13 @@ static int do_address(uchar chip, char rdwr_flag)
mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
mpc_reg_out(&regs->mdr, chip, 0);
if (wait_for_pin(&status)) {
return -2;
}
if (wait_for_pin(&status)) {
return -2;
}
if (status & I2C_RXAK) {
return -3;
}
if (status & I2C_RXAK) {
return -3;
}
return 0;
}
@ -250,7 +250,7 @@ static int mpc_get_fdr(int speed)
ipb = gd->ipb_clk;
for (i = 7; i >= 0; i--) {
for (j = 7; j >= 0; j--) {
scl = 2 * (scltap[j].scl2tap +
scl = 2 * (scltap[j].scl2tap +
(SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
if (ipb <= speed*scl) {
if ((speed*scl - ipb) < bestmatch) {
@ -344,13 +344,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
if (wait_for_bb()) {
if (wait_for_bb()) {
printf("i2c_write: bus is busy\n");
goto Done;
}
mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
if (do_address(chip, 0)) {
mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
if (do_address(chip, 0)) {
printf("i2c_write: failed to address chip\n");
goto Done;
}

16
cpu/mpc5xxx/pci_mpc5200.c
View File

@ -101,22 +101,22 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
/* GPIO Multiplexing - enable PCI */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
/* Set host bridge as pci master and enable memory decoding */
*(vu_long *)MPC5XXX_PCI_CMD |=
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
/* Set maximum latency timer */
*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
/* Set cache line size */
*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
(CFG_CACHELINE_SIZE / 4);
/* Map MBAR to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
/* Map RAM to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
@ -133,14 +133,14 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
/* Enable piplining */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
#endif
/* Disable interrupts from PCI controller */
*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
/* Disable initiator windows */
*(vu_long *)MPC5XXX_PCI_IWCR = 0;
/* Map PCI memory to physical space */
*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
@ -166,7 +166,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
mpc5200_write_config_dword);
udelay(1000);
#ifdef CONFIG_PCI_SCAN_SHOW

16
cpu/mpc8260/ether_fcc.c
View File

@ -233,7 +233,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (3): connect FCC's tx and rx clocks */
immr->im_cpmux.cmx_uar = 0;
immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
info->cmxfcr_value;
info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
immr->im_fcc[info->ether_index].fcc_gfmr =
@ -378,7 +378,7 @@ int fec_initialize(bd_t *bis)
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FCC%d ETHERNET",
ether_fcc_info[i].ether_index + 1);
ether_fcc_info[i].ether_index + 1);
dev->priv = &ether_fcc_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
@ -652,10 +652,10 @@ eth_loopback_test (void)
#if defined(CONFIG_HYMOD)
/*
* Attention: this is board-specific
* 0, FCC1
* 1, FCC2
* 2, FCC3
*/
* 0, FCC1
* 1, FCC2
* 2, FCC3
*/
# define FCC_START_LOOP 0
# define FCC_END_LOOP 2
@ -677,8 +677,8 @@ eth_loopback_test (void)
#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
/*
* Attention: this is board-specific
* 1, FCC2
*/
* 1, FCC2
*/
# define FCC_START_LOOP 1
# define FCC_END_LOOP 1

45
cpu/mpc85xx/Makefile Normal file
View File

@ -0,0 +1,45 @@
#
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao,X.Xiao@motorola.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o resetvec.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tsec.o \
pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
OBJS = $(COBJS)
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
sinclude .depend
#########################################################################

214
cpu/mpc85xx/commproc.c Normal file
View File

@ -0,0 +1,214 @@
/*
* Adapted for Motorola MPC8560 chips
* Xianghua Xiao <x.xiao@motorola.com>
*
* This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
* 8220 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
* 2.3.99 Updates
* Copyright (c) 2003 Motorola,Inc.
*
* In addition to the individual control of the communication
* channels, there are a few functions that globally affect the
* communication processor.
*
* Buffer descriptors must be allocated from the dual ported memory
* space. The allocator for that is here. When the communication
* process is reset, we reclaim the memory available. There is
* currently no deallocator for this memory.
*/
#include <common.h>
#include <asm/cpm_85xx.h>
#if defined(CONFIG_MPC8560)
/*
* because we have stack and init data in dual port ram
* we must reduce the size
*/
#undef CPM_DATAONLY_SIZE
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
void
m8560_cpm_reset(void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ulong count;
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Reclaim the DP memory for our use.
*/
gd->dp_alloc_base = CPM_DATAONLY_BASE;
gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
/*
* Reset CPM
*/
immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
count = 0;
do { /* Spin until command processed */
__asm__ __volatile__ ("eieio");
} while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
}
/* Allocate some memory from the dual ported ram.
* To help protocols with object alignment restrictions, we do that
* if they ask.
*/
uint
m8560_cpm_dpalloc(uint size, uint align)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
uint retloc;
uint align_mask, off;
uint savebase;
align_mask = align - 1;
savebase = gd->dp_alloc_base;
if ((off = (gd->dp_alloc_base & align_mask)) != 0)
gd->dp_alloc_base += (align - off);
if ((off = size & align_mask) != 0)
size += align - off;
if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
gd->dp_alloc_base = savebase;
panic("m8560_cpm_dpalloc: ran out of dual port ram!");
}
retloc = gd->dp_alloc_base;
gd->dp_alloc_base += size;
memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
return(retloc);
}
/* We also own one page of host buffer space for the allocation of
* UART "fifos" and the like.
*/
uint
m8560_cpm_hostalloc(uint size, uint align)
{
/* the host might not even have RAM yet - just use dual port RAM */
return (m8560_cpm_dpalloc(size, align));
}
/* Set a baud rate generator. This needs lots of work. There are
* eight BRGs, which can be connected to the CPM channels or output
* as clocks. The BRGs are in two different block of internal
* memory mapped space.
* The baud rate clock is the system clock divided by something.
* It was set up long ago during the initial boot phase and is
* is given to us.
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->brg_clk
#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
/* This function is used by UARTS, or anything else that uses a 16x
* oversampled clock.
*/
void
m8560_cpm_setbrg(uint brg, uint rate)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
}
else {
bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
}
/* This function is used to set high speed synchronous baud rate
* clocks.
*/
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
}
else {
bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
if (div16)
*bp |= CPM_BRG_DIV16;
}
/* This function is used to set baud rate generators using an external
* clock source and 16x oversampling.
*/
void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
if (brg < 4) {
bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
}
else {
bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
if (pinsel == 0)
*bp |= CPM_BRG_EXTC_CLK3_9;
else
*bp |= CPM_BRG_EXTC_CLK5_15;
}
#ifdef CONFIG_POST
void post_word_store (ulong a)
{
volatile ulong *save_addr =
(volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
*save_addr = a;
}
ulong post_word_load (void)
{
volatile ulong *save_addr =
(volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
return *save_addr;
}
#endif /* CONFIG_POST */
#endif /* CONFIG_MPC8560 */

26
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#
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao, X.Xiao@motorola.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float

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/*
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
/* ------------------------------------------------------------------------- */
int checkcpu (void)
{
uint pir = get_pir();
uint pvr = get_pvr();
printf("Motorola PowerPC ProcessorID=%08x Rev. ",pir);
switch(pvr) {
default:
printf("PVR=%08x", pvr);
break;
}
printf("\n");
return 0;
}
/* ------------------------------------------------------------------------- */
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
/*
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
__asm__ __volatile__("lis 3, 0x7000" ::: "r3");
mtspr(DBCR0,3);
return 1;
}
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk (void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
return ((sys_info.freqSystemBus + 3L) / 4L);
}
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_85xx_watchdog();
if (re_enable) enable_interrupts();
}
void
reset_85xx_watchdog(void)
{
/*
* Clear TSR(WIS) bit by writing 1
*/
unsigned long val;
val = mfspr(tsr);
val |= 0x40000000;
mtspr(tsr, val);
}
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_DDR_ECC)
__inline__ void dcbz(const void* addr)
{
__asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr));
}
__inline__ void dcbf(const void* addr)
{
__asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr));
}
void dma_init(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
asm("sync; isync; msync");
return;
}
uint dma_check(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
volatile uint status = dma->sr0;
/* While the channel is busy, spin */
while((status & 4) == 4) {
status = dma->sr0;
}
if (status != 0) {
printf ("DMA Error: status = %x\n", status);
}
return status;
}
int dma_xfer(void *dest, uint count, void *src) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->dar0 = (uint) dest;
dma->sar0 = (uint) src;
dma->bcr0 = count;
dma->mr0 = 0xf000004;
asm("sync;isync;msync");
dma->mr0 = 0xf000005;
asm("sync;isync;msync");
return dma_check();
}
#endif

205
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/*
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <asm/io.h>
#ifdef CONFIG_MPC8560
static void config_8560_ioports (volatile immap_t * immr)
{
int portnum;
for (portnum = 0; portnum < 4; portnum++) {
uint pmsk = 0,
ppar = 0,
psor = 0,
pdir = 0,
podr = 0,
pdat = 0;
iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
iop_conf_t *eiopc = iopc + 32;
uint msk = 1;
/*
* NOTE:
* index 0 refers to pin 31,
* index 31 refers to pin 0
*/
while (iopc < eiopc) {
if (iopc->conf) {
pmsk |= msk;
if (iopc->ppar)
ppar |= msk;
if (iopc->psor)
psor |= msk;
if (iopc->pdir)
pdir |= msk;
if (iopc->podr)
podr |= msk;
if (iopc->pdat)
pdat |= msk;
}
msk <<= 1;
iopc++;
}
if (pmsk != 0) {
volatile ioport_t *iop = ioport_addr (immr, portnum);
uint tpmsk = ~pmsk;
/*
* the (somewhat confused) paragraph at the
* bottom of page 35-5 warns that there might
* be "unknown behaviour" when programming
* PSORx and PDIRx, if PPARx = 1, so I
* decided this meant I had to disable the
* dedicated function first, and enable it
* last.
*/
iop->ppar &= tpmsk;
iop->psor = (iop->psor & tpmsk) | psor;
iop->podr = (iop->podr & tpmsk) | podr;
iop->pdat = (iop->pdat & tpmsk) | pdat;
iop->pdir = (iop->pdir & tpmsk) | pdir;
iop->ppar |= ppar;
}
}
}
#endif
/*
* Breathe some life into the CPU...
*
* Set up the memory map
* initialize a bunch of registers
*/
void cpu_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#ifdef CONFIG_MPC8560
config_8560_ioports(immap);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CFG_OR0_REMAP)
memctl->or0 = CFG_OR0_REMAP;
#endif
#if defined(CFG_OR1_REMAP)
memctl->or1 = CFG_OR1_REMAP;
#endif
/* now restrict to preliminary range */
#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
memctl->br0 = CFG_BR0_PRELIM;
memctl->or0 = CFG_OR0_PRELIM;
#endif
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
memctl->or1 = CFG_OR1_PRELIM;
memctl->br1 = CFG_BR1_PRELIM;
#endif
#if !defined(CONFIG_MPC85xx)
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
memctl->or2 = CFG_OR2_PRELIM;
memctl->br2 = CFG_BR2_PRELIM;
#endif
#endif
#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
memctl->or3 = CFG_OR3_PRELIM;
memctl->br3 = CFG_BR3_PRELIM;
#endif
#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
memctl->or4 = CFG_OR4_PRELIM;
memctl->br4 = CFG_BR4_PRELIM;
#endif
#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
memctl->or5 = CFG_OR5_PRELIM;
memctl->br5 = CFG_BR5_PRELIM;
#endif
#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
memctl->or6 = CFG_OR6_PRELIM;
memctl->br6 = CFG_BR6_PRELIM;
#endif
#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
memctl->or7 = CFG_OR7_PRELIM;
memctl->br7 = CFG_BR7_PRELIM;
#endif
#if defined(CONFIG_MPC8560)
m8560_cpm_reset();
#endif
}
/*
* We initialize L2 as cache here.
*/
int cpu_init_r (void)
{
#if defined(CONFIG_L2_CACHE)
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
volatile uint temp;
asm("msync;isync");
l2cache->l2ctl = 0x68000000; /* invalidate */
temp = l2cache->l2ctl;
asm("msync;isync");
l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
temp = l2cache->l2ctl;
asm("msync;isync");
printf("L2 cache enabled: 256KB\n");
#else
printf("L2 cache disabled.\n");
#endif
return 0;
}

461
cpu/mpc85xx/ether_fcc.c Normal file
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/*
* MPC8560 FCC Fast Ethernet
* Copyright (c) 2003 Motorola,Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
*
* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* MPC8560 FCC Fast Ethernet
* Basic ET HW initialization and packet RX/TX routines
*
* This code will not perform the IO port configuration. This should be
* done in the iop_conf_t structure specific for the board.
*
* TODO:
* add a PHY driver to do the negotiation
* reflect negotiation results in FPSMR
* look for ways to configure the board specific stuff elsewhere, eg.
* config_xxx.h or the board directory
*/
#include <common.h>
#include <malloc.h>
#include <asm/cpm_85xx.h>
#include <command.h>
#include <config.h>
#include <net.h>
#if defined(CONFIG_MPC8560)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
static struct ether_fcc_info_s
{
int ether_index;
int proff_enet;
ulong cpm_cr_enet_sblock;
ulong cpm_cr_enet_page;
ulong cmxfcr_mask;
ulong cmxfcr_value;
}
ether_fcc_info[] =
{
#ifdef CONFIG_ETHER_ON_FCC1
{
0,
PROFF_FCC1,
CPM_CR_FCC1_SBLOCK,
CPM_CR_FCC1_PAGE,
CFG_CMXFCR_MASK1,
CFG_CMXFCR_VALUE1
},
#endif
#ifdef CONFIG_ETHER_ON_FCC2
{
1,
PROFF_FCC2,
CPM_CR_FCC2_SBLOCK,
CPM_CR_FCC2_PAGE,
CFG_CMXFCR_MASK2,
CFG_CMXFCR_VALUE2
},
#endif
#ifdef CONFIG_ETHER_ON_FCC3
{
2,
PROFF_FCC3,
CPM_CR_FCC3_SBLOCK,
CPM_CR_FCC3_PAGE,
CFG_CMXFCR_MASK3,
CFG_CMXFCR_VALUE3
},
#endif
};
/*---------------------------------------------------------------------*/
/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
#define PKT_MAXDMA_SIZE 1520
/* The FCC stores dest/src/type, data, and checksum for receive packets. */
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
/* Maximum input buffer size. Must be a multiple of 32. */
#define PKT_MAXBLR_SIZE 1536
#define TOUT_LOOP 1000000
#define TX_BUF_CNT 2
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
/*
* FCC Ethernet Tx and Rx buffer descriptors.
* Provide for Double Buffering
* Note: PKTBUFSRX is defined in net.h
*/
typedef volatile struct rtxbd {
cbd_t rxbd[PKTBUFSRX];
cbd_t txbd[TX_BUF_CNT];
} RTXBD;
/* Good news: the FCC supports external BDs! */
#ifdef __GNUC__
static RTXBD rtx __attribute__ ((aligned(8)));
#else
#error "rtx must be 64-bit aligned"
#endif
#define ET_DEBUG
static int fec_send(struct eth_device* dev, volatile void *packet, int length)
{
int i = 0;
int result = 0;
if (length <= 0) {
printf("fec: bad packet size: %d\n", length);
goto out;
}
for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= TOUT_LOOP) {
printf("fec: tx buffer not ready\n");
goto out;
}
}
rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
rtx.txbd[txIdx].cbd_datlen = length;
rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
BD_ENET_TX_TC );
for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= TOUT_LOOP) {
printf("fec: tx error\n");
goto out;
}
}
#ifdef ET_DEBUG
printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
for(i=0;i<(length/16 + 1);i++) {
printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
}
#endif
/* return only status bits */
result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
txIdx = (txIdx + 1) % TX_BUF_CNT;
out:
return result;
}
static int fec_recv(struct eth_device* dev)
{
int length;
for (;;)
{
if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
length = rtx.rxbd[rxIdx].cbd_datlen;
if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
}
else {
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[rxIdx], length - 4);
}
/* Give the buffer back to the FCC. */
rtx.rxbd[rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
}
else {
rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
}
return length;
}
static int fec_init(struct eth_device* dev, bd_t *bis)
{
struct ether_fcc_info_s * info = dev->priv;
int i;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
#if 0
mii_discover_phy();
#endif
/* 28.9 - (1-2): ioports have been set up already */
/* 28.9 - (3): connect FCC's tx and rx clocks */
immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
}
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 1){
immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 2){
immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
}
/* 28.9 - (6): FDSR: Ethernet Syn */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
}
/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
rxIdx = 0;
txIdx = 0;
/* Setup Receiver Buffer Descriptors */
for (i = 0; i < PKTBUFSRX; i++)
{
rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx.rxbd[i].cbd_datlen = 0;
rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
}
rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/* Setup Ethernet Transmitter Buffer Descriptors */
for (i = 0; i < TX_BUF_CNT; i++)
{
rtx.txbd[i].cbd_sc = 0;
rtx.txbd[i].cbd_datlen = 0;
rtx.txbd[i].cbd_bufaddr = 0;
}
rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* 28.9 - (7): initialize parameter ram */
pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
/* clear whole structure to make sure all reserved fields are zero */
memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
/*
* common Parameter RAM area
*
* Allocate space in the reserved FCC area of DPRAM for the
* internal buffers. No one uses this space (yet), so we
* can do this. Later, we will add resource management for
* this area. CPM_FCC_SPECIAL_BASE: 0xb000.
*/
mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
/*
* Set maximum bytes per receive buffer.
* It must be a multiple of 32.
*/
pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
/* localbus SDRAM should be preferred */
pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
CFG_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
pram_ptr->fen_genfcc.fcc_rbdstat = 0;
pram_ptr->fen_genfcc.fcc_rbdlen = 0;
pram_ptr->fen_genfcc.fcc_rdptr = 0;
/* localbus SDRAM should be preferred */
pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
CFG_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
pram_ptr->fen_genfcc.fcc_tbdstat = 0;
pram_ptr->fen_genfcc.fcc_tbdlen = 0;
pram_ptr->fen_genfcc.fcc_tdptr = 0;
/* protocol-specific area */
pram_ptr->fen_statbuf = 0x0;
pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
pram_ptr->fen_crcec = 0;
pram_ptr->fen_alec = 0;
pram_ptr->fen_disfc = 0;
pram_ptr->fen_retlim = 15; /* Retry limit threshold */
pram_ptr->fen_retcnt = 0;
pram_ptr->fen_pper = 0;
pram_ptr->fen_boffcnt = 0;
pram_ptr->fen_gaddrh = 0;
pram_ptr->fen_gaddrl = 0;
pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
/*
* Set Ethernet station address.
*
* This is supplied in the board information structure, so we
* copy that into the controller.
* So far we have only been given one Ethernet address. We make
* it unique by setting a few bits in the upper byte of the
* non-static part of the address.
*/
#define ea eth_get_dev()->enetaddr
pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
#undef ea
pram_ptr->fen_ibdcount = 0;
pram_ptr->fen_ibdstart = 0;
pram_ptr->fen_ibdend = 0;
pram_ptr->fen_txlen = 0;
pram_ptr->fen_iaddrh = 0; /* disable hash */
pram_ptr->fen_iaddrl = 0;
pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
/* pad pointer. use tiptr since we don't need a specific padding char */
pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
#if defined(ET_DEBUG)
printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
pram_ptr->fen_genfcc.fcc_rbase);
printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
pram_ptr->fen_genfcc.fcc_tbase);
#endif
/* 28.9 - (8)(9): clear out events in FCCE */
/* 28.9 - (9): FCCM: mask all events */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
immr->im_cpm.im_cpm_fcc1.fccm = 0;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
immr->im_cpm.im_cpm_fcc2.fccm = 0;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
immr->im_cpm.im_cpm_fcc3.fccm = 0;
}
/* 28.9 - (10-12): we don't use ethernet interrupts */
/* 28.9 - (13)
*
* Let's re-initialize the channel now. We have to do it later
* than the manual describes because we have just now finished
* the BD initialization.
*/
cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
info->cpm_cr_enet_sblock,
0x0c,
CPM_CR_INIT_TRX) | CPM_CR_FLG;
do {
__asm__ __volatile__ ("eieio");
} while (cp->cpcr & CPM_CR_FLG);
/* 28.9 - (14): enable tx/rx in gfmr */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
}
return 0;
}
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
/* write GFMR: disable tx/rx */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
}
}
int fec_initialize(bd_t *bis)
{
struct eth_device* dev;
int i;
for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FCC%d ETHERNET",
ether_fcc_info[i].ether_index + 1);
dev->priv = &ether_fcc_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
dev->send = fec_send;
dev->recv = fec_recv;
eth_register(dev);
}
return 1;
}
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
#endif /* CONFIG_MPC8560 */

288
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/*
* (C) Copyright 2003,Motorola Inc.
* Xianghua Xiao <x.xiao@motorola.com>
* Adapted for Motorola 85xx chip.
*
* (C) Copyright 2003
* Gleb Natapov <gnatapov@mrv.com>
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk
*
* Hardware I2C driver for MPC107 PCI bridge.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#define DEBUG
#if defined(DEBUG)
#define DEB(x) x
#else
#define DEB(x)
#endif
#ifdef CONFIG_HARD_I2C
#include <i2c.h>
#define TIMEOUT (CFG_HZ/4)
#define I2C_Addr ((unsigned *)(CFG_CCSRBAR + 0x3000))
#define I2CADR &I2C_Addr[0]
#define I2CFDR &I2C_Addr[1]
#define I2CCCR &I2C_Addr[2]
#define I2CCSR &I2C_Addr[3]
#define I2CCDR &I2C_Addr[4]
#define I2CDFSRR &I2C_Addr[5]
#define I2C_READ 1
#define I2C_WRITE 0
/* taken from linux include/asm-ppc/io.h */
inline unsigned in_le32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
inline void out_le32(volatile unsigned *addr, int val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
#define writel(val, addr) out_le32(addr, val)
#define readl(addr) in_le32(addr)
void
i2c_init(int speed, int slaveadd)
{
/* stop I2C controller */
writel (0x0, I2CCCR);
/* set clock */
writel (0x3f, I2CFDR);
/* set default filter */
writel (0x10,I2CDFSRR);
/* write slave address */
writel (slaveadd, I2CADR);
/* clear status register */
writel (0x0, I2CCSR);
/* start I2C controller */
writel (MPC85xx_I2CCR_MEN, I2CCCR);
}
static __inline__ int
i2c_wait4bus (void)
{
ulong timeval = get_timer (0);
while (readl (I2CCSR) & MPC85xx_I2CSR_MBB)
if (get_timer (timeval) > TIMEOUT)
return -1;
return 0;
}
static __inline__ int
i2c_wait (int write)
{
u32 csr;
ulong timeval = get_timer (0);
do
{
csr = readl (I2CCSR);
if (!(csr & MPC85xx_I2CSR_MIF))
continue;
writel (0x0, I2CCSR);
if (csr & MPC85xx_I2CSR_MAL)
{
DEB(printf ("i2c_wait: MAL\n"));
return -1;
}
if (!(csr & MPC85xx_I2CSR_MCF))
{
DEB(printf ("i2c_wait: unfinished\n"));
return -1;
}
if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK))
{
DEB(printf ("i2c_wait: No RXACK\n"));
return -1;
}
return 0;
} while (get_timer (timeval) < TIMEOUT);
DEB(printf ("i2c_wait: timed out\n"));
return -1;
}
static __inline__ int
i2c_write_addr (u8 dev, u8 dir, int rsta)
{
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX |
(rsta?MPC85xx_I2CCR_RSTA:0), I2CCCR);
writel ((dev << 1) | dir, I2CCDR);
if (i2c_wait (I2C_WRITE) < 0)
return 0;
return 1;
}
static __inline__ int
__i2c_write (u8 *data, int length)
{
int i;
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, I2CCCR);
for (i=0; i < length; i++)
{
writel (data[i], I2CCDR);
if (i2c_wait (I2C_WRITE) < 0)
break;
}
return i;
}
static __inline__ int
__i2c_read (u8 *data, int length)
{
int i;
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
((length == 1) ? MPC85xx_I2CCR_TXAK : 0), I2CCCR);
/* dummy read */
readl (I2CCDR);
for (i=0; i < length; i++)
{
if (i2c_wait (I2C_READ) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
MPC85xx_I2CCR_TXAK, I2CCCR);
/* Generate stop on last byte */
if (i == length - 1)
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR);
data[i] = readl (I2CCDR);
}
return i;
}
int
i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
{
int i = 0;
u8 *a = (u8*)&addr;
if (i2c_wait4bus () < 0)
goto exit;
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
goto exit;
if (__i2c_write (&a[4 - alen], alen) != alen)
goto exit;
if (i2c_write_addr (dev, I2C_READ, 1) == 0)
goto exit;
i = __i2c_read (data, length);
exit:
writel (MPC85xx_I2CCR_MEN, I2CCCR);
return !(i == length);
}
int
i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
{
int i = 0;
u8 *a = (u8*)&addr;
if (i2c_wait4bus () < 0)
goto exit;
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
goto exit;
if (__i2c_write (&a[4 - alen], alen) != alen)
goto exit;
i = __i2c_write (data, length);
exit:
writel (MPC85xx_I2CCR_MEN, I2CCCR);
return !(i == length);
}
int i2c_probe (uchar chip)
{
int tmp;
/*
* Try to read the first location of the chip. The underlying
* driver doesn't appear to support sending just the chip address
* and looking for an <ACK> back.
*/
udelay(10000);
return i2c_read (chip, 0, 1, (char *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
char buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
return (buf[0]);
}
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
{
i2c_write (i2c_addr, reg, 1, &val, 1);
}
#endif /* CONFIG_HARD_I2C */

138
cpu/mpc85xx/interrupts.c Normal file
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/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 (440 port)
* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
*
* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
* Xianghua Xiao (X.Xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <ppc_asm.tmpl>
unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
static __inline__ unsigned long get_msr(void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
{
asm volatile("mtmsr %0" : : "r" (msr));
asm volatile("isync");
}
void enable_interrupts (void)
{
set_msr (get_msr() | MSR_EE);
}
/* returns flag if MSR_EE was set before */
int disable_interrupts (void)
{
ulong msr = get_msr();
set_msr (msr & ~MSR_EE);
return ((msr & MSR_EE) != 0);
}
/* interrupt is not supported yet */
int interrupt_init (void)
{
return (0);
}
/*
* Install and free a interrupt handler. Not implemented yet.
*/
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
return;
}
void
irq_free_handler(int vec)
{
return;
}
/****************************************************************************/
volatile ulong timestamp = 0;
/*
* timer_interrupt - gets called when the decrementer overflows,
* with interrupts disabled.
* Trivial implementation - no need to be really accurate.
*/
void timer_interrupt(struct pt_regs *regs)
{
printf ("*** Timer Interrupt *** ");
timestamp++;
#if defined(CONFIG_WATCHDOG)
if ((timestamp % 1000) == 0)
reset_85xx_watchdog();
#endif /* CONFIG_WATCHDOG */
}
void reset_timer (void)
{
timestamp = 0;
}
ulong get_timer (ulong base)
{
return (timestamp - base);
}
void set_timer (ulong t)
{
timestamp = t;
}
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
/*******************************************************************************
*
* irqinfo - print information about PCI devices,not implemented.
*
*/
int
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf ("\nInterrupt-unsupported:\n");
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */

107
cpu/mpc85xx/pci.c Normal file
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/*
* Copyright (C) 2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI Configuration space access support for MPC85xx PCI Bridge
*/
#include <common.h>
#include <asm/cpm_85xx.h>
#include <pci.h>
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ }
};
#endif
struct pci_controller local_hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxads_config_table,
#endif
};
void pci_init_board(void)
{
struct pci_controller* hose = (struct pci_controller *)&local_hose;
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_pcix_t *pcix = &immap->im_pcix;
u16 reg16;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
CFG_PCI_MEM_BASE,
CFG_PCI_MEM_PHYS,
(CFG_PCI_MEM_SIZE/2),
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
(CFG_PCI_MEM_BASE+0x08000000),
(CFG_PCI_MEM_PHYS+0x08000000),
0x1000000, /* 16M */
PCI_REGION_IO);
hose->region_count = 2;
pci_setup_indirect(hose,
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/* Clear non-reserved bits in status register */
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
pcix->potar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
pcix->powbar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = 0x8004401a; /* 128M MEM space */
pcix->potar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
pcix->powbar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) && 0x000fffff;
pcix->powbear2 = 0x00000000;
pcix->powar2 = 0x80088017; /* 16M IO space */
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
pcix->piwar1 = 0xa0F5501f;
}
#endif /* CONFIG_PCI */

2
cpu/mpc85xx/resetvec.S Normal file
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.section .resetvec,"ax"
b _start_e500

274
cpu/mpc85xx/serial_scc.c Normal file
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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
* Modified based on 8260 for 8560.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
*/
/*
* Minimal serial functions needed to use one of the SCC ports
* as serial console interface.
*/
#include <common.h>
#include <asm/cpm_85xx.h>
#if defined(CONFIG_MPC8560)
#if defined(CONFIG_CONS_ON_SCC)
#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
#define SCC_INDEX 0
#define PROFF_SCC PROFF_SCC1
#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
#define SCC_INDEX 1
#define PROFF_SCC PROFF_SCC2
#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
#define SCC_INDEX 2
#define PROFF_SCC PROFF_SCC3
#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
#define SCC_INDEX 3
#define PROFF_SCC PROFF_SCC4
#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
#else
#error "console not correctly defined"
#endif
int serial_init (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile ccsr_cpm_scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
uint dpaddr;
/* initialize pointers to SCC */
sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
/* Disable transmitter/receiver.
*/
sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/* put the SCC channel into NMSI (non multiplexd serial interface)
* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
*/
im->im_cpm.im_cpm_mux.cmxscr = \
(im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
/* Set up the baud rate generator.
*/
serial_setbrg ();
/* Allocate space for two buffer descriptors in the DP ram.
* damm: allocating space after the two buffers for rx/tx data
*/
dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
tbdf = rbdf + 1;
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = BD_SC_WRAP;
/* Set up the uart parameters in the parameter ram.
*/
up->scc_genscc.scc_rbase = dpaddr;
up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
up->scc_genscc.scc_rfcr = CPMFCR_EB;
up->scc_genscc.scc_tfcr = CPMFCR_EB;
up->scc_genscc.scc_mrblr = 1;
up->scc_maxidl = 0;
up->scc_brkcr = 1;
up->scc_parec = 0;
up->scc_frmec = 0;
up->scc_nosec = 0;
up->scc_brkec = 0;
up->scc_uaddr1 = 0;
up->scc_uaddr2 = 0;
up->scc_toseq = 0;
up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
up->scc_rccm = 0xc0ff;
/* Mask all interrupts and remove anything pending.
*/
sp->sccm = 0;
sp->scce = 0xffff;
/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
*/
sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
sp->gsmrl = \
SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
/* Set CTS no flow control, 1 stop bit, 8 bit character length,
* normal async UART mode, no parity
*/
sp->psmr = SCU_PSMR_CL;
/* execute the "Init Rx and Tx params" CP command.
*/
while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
/* Enable transmitter/receiver.
*/
sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
return (0);
}
void
serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CONS_USE_EXTC)
m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
#else
m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
#endif
}
void
serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
volatile immap_t *im;
if (c == '\n')
serial_putc ('\r');
im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
/* Wait for last character to go.
*/
while (tbdf->cbd_sc & BD_SC_READY)
;
/* Load the character into the transmit buffer.
*/
*(volatile char *)tbdf->cbd_bufaddr = c;
tbdf->cbd_datlen = 1;
tbdf->cbd_sc |= BD_SC_READY;
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int
serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
volatile immap_t *im;
unsigned char c;
im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
/* Wait for character to show up.
*/
while (rbdf->cbd_sc & BD_SC_EMPTY)
;
/* Grab the char and clear the buffer again.
*/
c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
rbdf->cbd_sc |= BD_SC_EMPTY;
return (c);
}
int
serial_tstc()
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
volatile immap_t *im;
im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
#endif /* CONFIG_CONS_ON_SCC */
#endif /* CONFIG_MPC8560 */

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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
#ifdef CONFIG_SPD_EEPROM
#undef DEBUG
#if defined(DEBUG)
#define DEB(x) x
#else
#define DEB(x)
#endif
#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
long int spd_sdram(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
spd_eeprom_t spd;
unsigned int memsize,tmp,tmp1,tmp2;
unsigned char caslat;
i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
if ( spd.nrows > 2 ) {
printf("DDR:Only two chip selects are supported on ADS.\n");
return 0;
}
if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
printf("DDR:Row or Col number unsupported.\n");
return 0;
}
ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
DEB(printf("\n"));
DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
if ( spd.nrows == 2 ) {
ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
}
memsize = spd.nrows * (4 * spd.row_dens);
if( spd.mem_type == 0x07 ) {
printf("DDR module detected, total size:%dMB.\n",memsize);
} else {
printf("No DDR module found!\n");
return 0;
}
switch(memsize) {
case 16:
tmp = 7; /* TLB size */
tmp1 = 1; /* TLB entry number */
tmp2 = 23; /* Local Access Window size */
break;
case 32:
tmp = 7;
tmp1 = 2;
tmp2 = 24;
break;
case 64:
tmp = 8;
tmp1 = 1;
tmp2 = 25;
break;
case 128:
tmp = 8;
tmp1 = 2;
tmp2 = 26;
break;
case 256:
tmp = 9;
tmp1 = 1;
tmp2 = 27;
break;
case 512:
tmp = 9;
tmp1 = 2;
tmp2 = 28;
break;
case 1024:
tmp = 10;
tmp1 = 1;
tmp2 = 29;
break;
default:
printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
return 0;
break;
}
/* configure DDR TLB to TLB1 Entry 4,5 */
mtspr(MAS0, TLB1_MAS0(1,4,0));
mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
& 0xfffff),0,0,0,0,0,0,0,0)));
DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1)));
if(tmp1 == 2) {
mtspr(MAS0, TLB1_MAS0(1,5,0));
mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
}
#if defined(CONFIG_RAM_AS_FLASH)
ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
#else
ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
#endif
tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
/* find the largest CAS */
if(spd.cas_lat & 0x40) {
caslat = 7;
} else if (spd.cas_lat & 0x20) {
caslat = 6;
} else if (spd.cas_lat & 0x10) {
caslat = 5;
} else if (spd.cas_lat & 0x08) {
caslat = 4;
} else if (spd.cas_lat & 0x04) {
caslat = 3;
} else if (spd.cas_lat & 0x02) {
caslat = 2;
} else if (spd.cas_lat & 0x01) {
caslat = 1;
} else {
printf("DDR:no valid CAS Latency information.\n");
return 0;
}
tmp1 = get_bus_freq(0)/1000000;
if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
if(spd.clk_cycle3 == 0xa0) caslat -= 2;
else if(spd.clk_cycle2 == 0xa0) caslat--;
} else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
if(spd.clk_cycle3 == 0x75) caslat -= 2;
else if(spd.clk_cycle2 == 0x75) caslat--;
} else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
if(spd.clk_cycle3 == 0x60) caslat -= 2;
else if(spd.clk_cycle2 == 0x60) caslat--;
} else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
printf("DDR:platform frequency is not fit for DDR rate\n");
return 0;
}
/* note: caslat must also be programmed into ddr->sdram_mode register */
/* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
#if 1
ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
((caslat & 0x07)<< 16 ) | \
(((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
( 0x300 ) | \
((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
#else
ddr->timing_cfg_1 = 0x37344321;
caslat = 4;
#endif
DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
/* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
#if defined(CONFIG_MPC85xx_REV1)
ddr->timing_cfg_2 = 0x00000800;
#endif
DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
/* only DDR I is supported, DDR I and II have different mode-register-set definition */
/* burst length is always 4 */
switch(caslat) {
case 2:
ddr->sdram_mode = 0x52; /* 1.5 */
break;
case 3:
ddr->sdram_mode = 0x22; /* 2.0 */
break;
case 4:
ddr->sdram_mode = 0x62; /* 2.5 */
break;
case 5:
ddr->sdram_mode = 0x32; /* 3.0 */
break;
default:
printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
return 0;
}
DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
switch(spd.refresh) {
case 0x00:
case 0x80:
tmp = ns2clk(15625);
break;
case 0x01:
case 0x81:
tmp = ns2clk(3900);
break;
case 0x02:
case 0x82:
tmp = ns2clk(7800);
break;
case 0x03:
case 0x83:
tmp = ns2clk(31300);
break;
case 0x04:
case 0x84:
tmp = ns2clk(62500);
break;
case 0x05:
case 0x85:
tmp = ns2clk(125000);
break;
default:
tmp = 0x512;
break;
}
/* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
/* is this an ECC DDR chip? */
#if defined(CONFIG_DDR_ECC)
if(spd.config == 0x02) {
ddr->err_disable = 0x0000000d;
ddr->err_sbe = 0x00ff0000;
}
DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
#endif
asm("sync;isync;msync");
udelay(500);
/* registered or unbuffered? */
#if defined(CONFIG_DDR_ECC)
ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
#endif
ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
((spd.mod_attr == 0x26) ? 0x10000000:0x0));
asm("sync;isync;msync");
udelay(500);
DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
return (memsize*1024*1024);
}
#endif /* CONFIG_SPD_EEPROM */

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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc_asm.tmpl>
#include <asm/processor.h>
/* --------------------------------------------------------------- */
#define ONE_BILLION 1000000000
void get_sys_info (sys_info_t * sysInfo)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio,e500_ratio;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
switch(plat_ratio) {
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x08:
case 0x09:
case 0x0a:
case 0x0c:
case 0x10:
sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
break;
default:
sysInfo->freqSystemBus = 0;
break;
}
e500_ratio = (gur->porpllsr) & 0x003f0000;
e500_ratio >>= 16;
switch(e500_ratio) {
case 0x04:
sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
break;
case 0x05:
sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
break;
case 0x06:
sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
break;
case 0x07:
sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
break;
default:
sysInfo->freqProcessor = 0;
break;
}
}
int get_clocks (void)
{
DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
#if defined(CONFIG_MPC8560)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
sccr = immap->im_cpm.im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
#if defined(CONFIG_MPC8560)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);
else return (1);
}
/********************************************
* get_bus_freq
* return system bus freq in Hz
*********************************************/
ulong get_bus_freq (ulong dummy)
{
ulong val;
sys_info_t sys_info;
get_sys_info (&sys_info);
val = sys_info.freqSystemBus;
return val;
}

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/*
* linux/arch/ppc/kernel/traps.c
*
* Copyright (C) 2003 Motorola
* Modified by Xianghua Xiao(x.xiao@motorola.com)
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Modified by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras (paulus@cs.anu.edu.au)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file handles the architecture-dependent parts of hardware exceptions
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
*/
#define END_OF_MEM (CFG_SDRAM_SIZE * 1024 * 1024)
static __inline__ void set_tsr(unsigned long val)
{
asm volatile("mtspr 0x150, %0" : : "r" (val));
}
static __inline__ unsigned long get_esr(void)
{
unsigned long val;
asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
return val;
}
#define ESR_MCI 0x80000000
#define ESR_PIL 0x08000000
#define ESR_PPR 0x04000000
#define ESR_PTR 0x02000000
#define ESR_DST 0x00800000
#define ESR_DIZ 0x00400000
#define ESR_U0F 0x00008000
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
/*
* Trap & Exception support
*/
void
print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("Call backtrace: ");
while (sp) {
if ((uint)sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
printf("\n");
printf("%08lX ", i);
if (cnt > 32) break;
sp = (unsigned long *)*sp;
}
printf("\n");
}
void show_regs(struct pt_regs * regs)
{
int i;
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
regs->msr&MSR_IR ? 1 : 0,
regs->msr&MSR_DR ? 1 : 0);
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
{
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
{
printf("\n");
}
}
}
void
_exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
void
CritcalInputException(struct pt_regs *regs)
{
panic("Critical Input Exception");
}
void
MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
printf("regs %p ",regs);
switch( regs->msr & 0x0000F000)
{
case (1<<12) :
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
case (1<<13) :
printf("Transfer error ack signal\n");
break;
case (1<<14) :
printf("Data parity signal\n");
break;
case (1<<15) :
printf("Address parity signal\n");
break;
default:
printf("Unknown values in msr\n");
}
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("machine check");
}
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Alignment Exception");
}
void
ProgramCheckException(struct pt_regs *regs)
{
long esr_val;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
esr_val = get_esr();
if( esr_val & ESR_PIL )
printf( "** Illegal Instruction **\n" );
else if( esr_val & ESR_PPR )
printf( "** Privileged Instruction **\n" );
else if( esr_val & ESR_PTR )
printf( "** Trap Instruction **\n" );
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Program Check Exception");
}
void
PITException(struct pt_regs *regs)
{
/*
* Reset PIT interrupt
*/
set_tsr(0x0c000000);
/*
* Call timer_interrupt routine in interrupts.c
*/
timer_interrupt(NULL);
}
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
void
DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
int
addr_probe(uint *addr)
{
return 0;
}

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/*
* tsec.c
* Motorola Three Speed Ethernet Controller driver
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
*
*/
#include <config.h>
#include <mpc85xx.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#if defined(CONFIG_TSEC_ENET)
#include "tsec.h"
#define TX_BUF_CNT 2
#undef TSEC_DEBUG
#ifdef TSEC_DEBUG
#define DBGPRINT(x) printf(x)
#else
#define DBGPRINT(x)
#endif
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
typedef volatile struct rtxbd {
txbd8_t txbd[TX_BUF_CNT];
rxbd8_t rxbd[PKTBUFSRX];
} RTXBD;
#ifdef __GNUC__
static RTXBD rtx __attribute__ ((aligned(8)));
#else
#error "rtx must be 64-bit aligned"
#endif
static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
static int tsec_recv(struct eth_device* dev);
static int tsec_init(struct eth_device* dev, bd_t * bd);
static void tsec_halt(struct eth_device* dev);
static void init_registers(tsec_t *regs);
static void startup_tsec(tsec_t *regs);
static void init_phy(tsec_t *regs);
/* Initialize device structure. returns 0 on failure, 1 on
* success */
int tsec_initialize(bd_t *bis)
{
struct eth_device* dev;
int i;
dev = (struct eth_device*) malloc(sizeof *dev);
if(dev == NULL)
return 0;
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "MOTOROLA ETHERNET");
dev->iobase = 0;
dev->priv = 0;
dev->init = tsec_init;
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
/* Tell u-boot to get the addr from the env */
for(i=0;i<6;i++)
dev->enetaddr[i] = 0;
eth_register(dev);
return 1;
}
/* Initializes data structures and registers for the controller,
* and brings the interface up */
int tsec_init(struct eth_device* dev, bd_t * bd)
{
tsec_t *regs;
uint tempval;
char tmpbuf[MAC_ADDR_LEN];
int i;
regs = (tsec_t *)(TSEC_BASE_ADDR);
/* Make sure the controller is stopped */
tsec_halt(dev);
/* Reset the MAC */
regs->maccfg1 |= MACCFG1_SOFT_RESET;
/* Clear MACCFG1[Soft_Reset] */
regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
/* Init MACCFG2. Defaults to GMII/MII */
regs->maccfg2 = MACCFG2_INIT_SETTINGS;
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
for(i=0;i<MAC_ADDR_LEN;i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = bd->bi_enetaddr[i];
}
(uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
tempval = *((uint *)(tmpbuf +4));
(uint)(regs->macstnaddr2) = tempval;
/* Initialize the PHY */
init_phy(regs);
/* reset the indices to zero */
rxIdx = 0;
txIdx = 0;
/* Clear out (for the most part) the other registers */
init_registers(regs);
/* Ready the device for tx/rx */
startup_tsec(regs);
return 1;
}
/* Reads from the register at offset in the PHY at phyid, */
/* using the register set defined in regbase. It waits until the */
/* bits in the miimstat are valid (miimind notvalid bit cleared), */
/* and then passes those bits on to the variable specified in */
/* value */
/* Before it does the read, it needs to clear the command field */
uint read_phy_reg(tsec_t *regbase, uint phyid, uint offset)
{
uint value;
/* Put the address of the phy, and the register number into
* MIIMADD
*/
regbase->miimadd = (phyid << 8) | offset;
/* Clear the command register, and wait */
regbase->miimcom = 0;
asm("msync");
/* Initiate a read command, and wait */
regbase->miimcom = MIIM_READ_COMMAND;
asm("msync");
/* Wait for the the indication that the read is done */
while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
/* Grab the value read from the PHY */
value = regbase->miimstat;
return value;
}
/* Setup the PHY */
static void init_phy(tsec_t *regs)
{
uint testval;
unsigned int timeout = TSEC_TIMEOUT;
/* Assign a Physical address to the TBI */
regs->tbipa=TBIPA_VALUE;
/* reset the management interface */
regs->miimcfg=MIIMCFG_RESET;
regs->miimcfg=MIIMCFG_INIT_VALUE;
/* Wait until the bus is free */
while(regs->miimind & MIIMIND_BUSY);
#ifdef CONFIG_PHY_CIS8201
/* override PHY config settings */
write_phy_reg(regs, 0, MIIM_AUX_CONSTAT, MIIM_AUXCONSTAT_INIT);
/* Set up interface mode */
write_phy_reg(regs, 0, MIIM_EXT_CON1, MIIM_EXTCON1_INIT);
#endif
/* Set the PHY to gigabit, full duplex, Auto-negotiate */
write_phy_reg(regs, 0, MIIM_CONTROL, MIIM_CONTROL_INIT);
/* Wait until TBI_STATUS indicates AN is done */
DBGPRINT("Waiting for Auto-negotiation to complete\n");
testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
while((!(testval & MIIM_TBI_STATUS_AN_DONE))&& timeout--) {
testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
}
if(testval & MIIM_TBI_STATUS_AN_DONE)
DBGPRINT("Auto-negotiation done\n");
else
DBGPRINT("Auto-negotiation timed-out.\n");
#ifdef CONFIG_PHY_CIS8201
/* Find out what duplexity (duplicity?) we have */
/* Read it twice to make sure */
testval=read_phy_reg(regs, 0, MIIM_AUX_CONSTAT);
if(testval & MIIM_AUXCONSTAT_DUPLEX) {
DBGPRINT("Enet starting in full duplex\n");
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
} else {
DBGPRINT("Enet starting in half duplex\n");
regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
}
/* Also, we look to see what speed we are at
* if Gigabit, MACCFG2 goes in GMII, otherwise,
* MII mode.
*/
if((testval & MIIM_AUXCONSTAT_SPEED) != MIIM_AUXCONSTAT_GBIT) {
if((testval & MIIM_AUXCONSTAT_SPEED) == MIIM_AUXCONSTAT_100)
DBGPRINT("Enet starting in 100BT\n");
else
DBGPRINT("Enet starting in 10BT\n");
/* mark the mode in MACCFG2 */
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
} else {
DBGPRINT("Enet starting in 1000BT\n");
}
#endif
#ifdef CONFIG_PHY_M88E1011
/* Read the PHY to see what speed and duplex we are */
testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
timeout = TSEC_TIMEOUT;
while((!(testval & MIIM_PHYSTAT_SPDDONE)) && timeout--) {
testval = read_phy_reg(regs,0,MIIM_PHY_STATUS);
}
if(!(testval & MIIM_PHYSTAT_SPDDONE))
DBGPRINT("Enet: Speed not resolved\n");
testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
if(testval & MIIM_PHYSTAT_DUPLEX) {
DBGPRINT("Enet starting in Full Duplex\n");
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
} else {
DBGPRINT("Enet starting in Half Duplex\n");
regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
}
if(!((testval&MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_GBIT)) {
if((testval & MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_100)
DBGPRINT("Enet starting in 100BT\n");
else
DBGPRINT("Enet starting in 10BT\n");
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
} else {
DBGPRINT("Enet starting in 1000BT\n");
}
#endif
}
static void init_registers(tsec_t *regs)
{
/* Clear IEVENT */
regs->ievent = IEVENT_INIT_CLEAR;
regs->imask = IMASK_INIT_CLEAR;
regs->hash.iaddr0 = 0;
regs->hash.iaddr1 = 0;
regs->hash.iaddr2 = 0;
regs->hash.iaddr3 = 0;
regs->hash.iaddr4 = 0;
regs->hash.iaddr5 = 0;
regs->hash.iaddr6 = 0;
regs->hash.iaddr7 = 0;
regs->hash.gaddr0 = 0;
regs->hash.gaddr1 = 0;
regs->hash.gaddr2 = 0;
regs->hash.gaddr3 = 0;
regs->hash.gaddr4 = 0;
regs->hash.gaddr5 = 0;
regs->hash.gaddr6 = 0;
regs->hash.gaddr7 = 0;
regs->rctrl = 0x00000000;
/* Init RMON mib registers */
memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
regs->rmon.cam1 = 0xffffffff;
regs->rmon.cam2 = 0xffffffff;
regs->mrblr = MRBLR_INIT_SETTINGS;
regs->minflr = MINFLR_INIT_SETTINGS;
regs->attr = ATTR_INIT_SETTINGS;
regs->attreli = ATTRELI_INIT_SETTINGS;
}
static void startup_tsec(tsec_t *regs)
{
int i;
/* Point to the buffer descriptors */
regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
/* Initialize the Rx Buffer descriptors */
for (i = 0; i < PKTBUFSRX; i++) {
rtx.rxbd[i].status = RXBD_EMPTY;
rtx.rxbd[i].length = 0;
rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
}
rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
/* Initialize the TX Buffer Descriptors */
for(i=0; i<TX_BUF_CNT; i++) {
rtx.txbd[i].status = 0;
rtx.txbd[i].length = 0;
rtx.txbd[i].bufPtr = 0;
}
rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
/* Enable Transmit and Receive */
regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
/* Tell the DMA it is clear to go */
regs->dmactrl |= DMACTRL_INIT_SETTINGS;
regs->tstat = TSTAT_CLEAR_THALT;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
}
/* This returns the status bits of the device. The return value
* is never checked, and this is what the 8260 driver did, so we
* do the same. Presumably, this would be zero if there were no
* errors */
static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
{
int i;
int result = 0;
tsec_t * regs = (tsec_t *)(TSEC_BASE_ADDR);
/* Find an empty buffer descriptor */
for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
DBGPRINT("tsec: tx buffers full\n");
return result;
}
}
rtx.txbd[txIdx].bufPtr = (uint)packet;
rtx.txbd[txIdx].length = length;
rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
/* Tell the DMA to go */
regs->tstat = TSTAT_CLEAR_THALT;
/* Wait for buffer to be transmitted */
for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
DBGPRINT("tsec: tx error\n");
return result;
}
}
txIdx = (txIdx + 1) % TX_BUF_CNT;
result = rtx.txbd[txIdx].status & TXBD_STATS;
return result;
}
static int tsec_recv(struct eth_device* dev)
{
int length;
tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
length = rtx.rxbd[rxIdx].length;
/* Send the packet up if there were no errors */
if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
NetReceive(NetRxPackets[rxIdx], length - 4);
}
rtx.rxbd[rxIdx].length = 0;
/* Set the wrap bit if this is the last element in the list */
rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
rxIdx = (rxIdx + 1) % PKTBUFSRX;
}
if(regs->ievent&IEVENT_BSY) {
regs->ievent = IEVENT_BSY;
regs->rstat = RSTAT_CLEAR_RHALT;
}
return -1;
}
static void tsec_halt(struct eth_device* dev)
{
tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
}
#endif /* CONFIG_TSEC_ENET */

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/*
* tsec.h
*
* Driver for the Motorola Triple Speed Ethernet Controller
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
*
*/
#ifndef __TSEC_H
#define __TSEC_H
#include <net.h>
#include <mpc85xx.h>
#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
#define TSEC_MEM_SIZE 0x01000
#define MAC_ADDR_LEN 6
#define TSEC_TIMEOUT 1000000
#define TOUT_LOOP 1000000
/* MAC register bits */
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_RESET_RX_MC 0x00080000
#define MACCFG1_RESET_TX_MC 0x00040000
#define MACCFG1_RESET_RX_FUN 0x00020000
#define MACCFG1_RESET_TX_FUN 0x00010000
#define MACCFG1_LOOPBACK 0x00000100
#define MACCFG1_RX_FLOW 0x00000020
#define MACCFG1_TX_FLOW 0x00000010
#define MACCFG1_SYNCD_RX_EN 0x00000008
#define MACCFG1_RX_EN 0x00000004
#define MACCFG1_SYNCD_TX_EN 0x00000002
#define MACCFG1_TX_EN 0x00000001
#define MACCFG2_INIT_SETTINGS 0x00007205
#define MACCFG2_FULL_DUPLEX 0x00000001
#define MACCFG2_IF 0x00000300
#define MACCFG2_MII 0x00000100
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
#define TBIPA_VALUE 0x1f
#define MIIMCFG_INIT_VALUE 0x00000003
#define MIIMCFG_RESET 0x80000000
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define MIIM_TBICON 0x11
#define MIIM_TBICON_GMII 0x00000010
#define MIIM_TBICON_AN 0x00000100
#define MIIM_CONTROL 0x00
#define MIIM_CONTROL_INIT 0x00001140
#define MIIM_ANEN 0x00001000
#define MIIM_TBI_STATUS 0x1
#define MIIM_TBI_STATUS_AN_DONE 0x00000020
#define MIIM_TBI_ANEX 0x6
#define MIIM_TBI_ANEX_NP 0x00000004
#define MIIM_TBI_ANEX_PRX 0x00000002
#define MIIM_TBI_ANLPBPA 0x5
#define MIIM_TBI_ANLPBPA_HALF 0x00000040
#define MIIM_TBI_ANLPBPA_FULL 0x00000020
#ifdef CONFIG_PHY_CIS8201
#define MIIM_AUX_CONSTAT 0x1c
#define MIIM_AUXCONSTAT_INIT 0x0004
#define MIIM_AUXCONSTAT_DUPLEX 0x0020
#define MIIM_AUXCONSTAT_SPEED 0x0018
#define MIIM_AUXCONSTAT_GBIT 0x0010
#define MIIM_AUXCONSTAT_100 0x0008
#define MIIM_EXT_CON1 0x17
#define MIIM_EXTCON1_INIT 0x0000
#endif
#ifdef CONFIG_PHY_M88E1011
#define MIIM_ANAR 0x04
#define MIIM_ANAR_ADVERTISEMENT 0x01e1
#define MIIM_GBIT_CON 0x09
#define MIIM_GBIT_CON_ADVERT 0x1e00
#define MIIM_PHY_STATUS 0x11
#define MIIM_PHYSTAT_SPEED 0xc000
#define MIIM_PHYSTAT_GBIT 0x8000
#define MIIM_PHYSTAT_100 0x4000
#define MIIM_PHYSTAT_DUPLEX 0x2000
#define MIIM_PHYSTAT_SPDDONE 0x0800
#define MIIM_PHYSTAT_LINK 0x0400
#endif
#define MIIM_READ_COMMAND 0x00000001
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
#define MINFLR_INIT_SETTINGS 0x00000040
#define DMACTRL_INIT_SETTINGS 0x000000c3
#define DMACTRL_GRS 0x00000010
#define DMACTRL_GTS 0x00000008
#define TSTAT_CLEAR_THALT 0x80000000
#define RSTAT_CLEAR_RHALT 0x00800000
/* Write value to the PHY at phyid to the register at offset, */
/* using the register space defined in regbase. Note that */
/* miimcfg needs to have the clock speed setup correctly. This */
/* macro will wait until the write is done before it finishes */
#define write_phy_reg(regbase, phyid, offset, value) do { \
int timeout=1000000; \
regbase->miimadd = (phyid << 8) | offset; \
regbase->miimcon = value; \
asm("msync"); \
while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
} while(0)
#define IEVENT_INIT_CLEAR 0xffffffff
#define IEVENT_BABR 0x80000000
#define IEVENT_RXC 0x40000000
#define IEVENT_BSY 0x20000000
#define IEVENT_EBERR 0x10000000
#define IEVENT_MSRO 0x04000000
#define IEVENT_GTSC 0x02000000
#define IEVENT_BABT 0x01000000
#define IEVENT_TXC 0x00800000
#define IEVENT_TXE 0x00400000
#define IEVENT_TXB 0x00200000
#define IEVENT_TXF 0x00100000
#define IEVENT_IE 0x00080000
#define IEVENT_LC 0x00040000
#define IEVENT_CRL 0x00020000
#define IEVENT_XFUN 0x00010000
#define IEVENT_RXB0 0x00008000
#define IEVENT_GRSC 0x00000100
#define IEVENT_RXF0 0x00000080
#define IMASK_INIT_CLEAR 0x00000000
#define IMASK_TXEEN 0x00400000
#define IMASK_TXBEN 0x00200000
#define IMASK_TXFEN 0x00100000
#define IMASK_RXFEN0 0x00000080
/* Default Attribute fields */
#define ATTR_INIT_SETTINGS 0x000000c0
#define ATTRELI_INIT_SETTINGS 0x00000000
/* TxBD status field bits */
#define TXBD_READY 0x8000
#define TXBD_PADCRC 0x4000
#define TXBD_WRAP 0x2000
#define TXBD_INTERRUPT 0x1000
#define TXBD_LAST 0x0800
#define TXBD_CRC 0x0400
#define TXBD_DEF 0x0200
#define TXBD_HUGEFRAME 0x0080
#define TXBD_LATECOLLISION 0x0080
#define TXBD_RETRYLIMIT 0x0040
#define TXBD_RETRYCOUNTMASK 0x003c
#define TXBD_UNDERRUN 0x0002
#define TXBD_STATS 0x03ff
/* RxBD status field bits */
#define RXBD_EMPTY 0x8000
#define RXBD_RO1 0x4000
#define RXBD_WRAP 0x2000
#define RXBD_INTERRUPT 0x1000
#define RXBD_LAST 0x0800
#define RXBD_FIRST 0x0400
#define RXBD_MISS 0x0100
#define RXBD_BROADCAST 0x0080
#define RXBD_MULTICAST 0x0040
#define RXBD_LARGE 0x0020
#define RXBD_NONOCTET 0x0010
#define RXBD_SHORT 0x0008
#define RXBD_CRCERR 0x0004
#define RXBD_OVERRUN 0x0002
#define RXBD_TRUNCATED 0x0001
#define RXBD_STATS 0x003f
typedef struct txbd8
{
ushort status; /* Status Fields */
ushort length; /* Buffer length */
uint bufPtr; /* Buffer Pointer */
} txbd8_t;
typedef struct rxbd8
{
ushort status; /* Status Fields */
ushort length; /* Buffer Length */
uint bufPtr; /* Buffer Pointer */
} rxbd8_t;
typedef struct rmon_mib
{
/* Transmit and Receive Counters */
uint tr64; /* Transmit and Receive 64-byte Frame Counter */
uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
/* Receive Counters */
uint rbyt; /* Receive Byte Counter */
uint rpkt; /* Receive Packet Counter */
uint rfcs; /* Receive FCS Error Counter */
uint rmca; /* Receive Multicast Packet (Counter) */
uint rbca; /* Receive Broadcast Packet */
uint rxcf; /* Receive Control Frame Packet */
uint rxpf; /* Receive Pause Frame Packet */
uint rxuo; /* Receive Unknown OP Code */
uint raln; /* Receive Alignment Error */
uint rflr; /* Receive Frame Length Error */
uint rcde; /* Receive Code Error */
uint rcse; /* Receive Carrier Sense Error */
uint rund; /* Receive Undersize Packet */
uint rovr; /* Receive Oversize Packet */
uint rfrg; /* Receive Fragments */
uint rjbr; /* Receive Jabber */
uint rdrp; /* Receive Drop */
/* Transmit Counters */
uint tbyt; /* Transmit Byte Counter */
uint tpkt; /* Transmit Packet */
uint tmca; /* Transmit Multicast Packet */
uint tbca; /* Transmit Broadcast Packet */
uint txpf; /* Transmit Pause Control Frame */
uint tdfr; /* Transmit Deferral Packet */
uint tedf; /* Transmit Excessive Deferral Packet */
uint tscl; /* Transmit Single Collision Packet */
/* (0x2_n700) */
uint tmcl; /* Transmit Multiple Collision Packet */
uint tlcl; /* Transmit Late Collision Packet */
uint txcl; /* Transmit Excessive Collision Packet */
uint tncl; /* Transmit Total Collision */
uint res2;
uint tdrp; /* Transmit Drop Frame */
uint tjbr; /* Transmit Jabber Frame */
uint tfcs; /* Transmit FCS Error */
uint txcf; /* Transmit Control Frame */
uint tovr; /* Transmit Oversize Frame */
uint tund; /* Transmit Undersize Frame */
uint tfrg; /* Transmit Fragments Frame */
/* General Registers */
uint car1; /* Carry Register One */
uint car2; /* Carry Register Two */
uint cam1; /* Carry Register One Mask */
uint cam2; /* Carry Register Two Mask */
} rmon_mib_t;
typedef struct tsec_hash_regs
{
uint iaddr0; /* Individual Address Register 0 */
uint iaddr1; /* Individual Address Register 1 */
uint iaddr2; /* Individual Address Register 2 */
uint iaddr3; /* Individual Address Register 3 */
uint iaddr4; /* Individual Address Register 4 */
uint iaddr5; /* Individual Address Register 5 */
uint iaddr6; /* Individual Address Register 6 */
uint iaddr7; /* Individual Address Register 7 */
uint res1[24];
uint gaddr0; /* Group Address Register 0 */
uint gaddr1; /* Group Address Register 1 */
uint gaddr2; /* Group Address Register 2 */
uint gaddr3; /* Group Address Register 3 */
uint gaddr4; /* Group Address Register 4 */
uint gaddr5; /* Group Address Register 5 */
uint gaddr6; /* Group Address Register 6 */
uint gaddr7; /* Group Address Register 7 */
uint res2[24];
} tsec_hash_t;
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
uint res000[4];
uint ievent; /* Interrupt Event */
uint imask; /* Interrupt Mask */
uint edis; /* Error Disabled */
uint res01c;
uint ecntrl; /* Ethernet Control */
uint minflr; /* Minimum Frame Length */
uint ptv; /* Pause Time Value */
uint dmactrl; /* DMA Control */
uint tbipa; /* TBI PHY Address */
uint res034[3];
uint res040[48];
/* Transmit Control and Status Registers (0x2_n100) */
uint tctrl; /* Transmit Control */
uint tstat; /* Transmit Status */
uint res108;
uint tbdlen; /* Tx BD Data Length */
uint res110[5];
uint ctbptr; /* Current TxBD Pointer */
uint res128[23];
uint tbptr; /* TxBD Pointer */
uint res188[30];
/* (0x2_n200) */
uint res200;
uint tbase; /* TxBD Base Address */
uint res208[42];
uint ostbd; /* Out of Sequence TxBD */
uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
uint res2b8[18];
/* Receive Control and Status Registers (0x2_n300) */
uint rctrl; /* Receive Control */
uint rstat; /* Receive Status */
uint res308;
uint rbdlen; /* RxBD Data Length */
uint res310[4];
uint res320;
uint crbptr; /* Current Receive Buffer Pointer */
uint res328[6];
uint mrblr; /* Maximum Receive Buffer Length */
uint res344[16];
uint rbptr; /* RxBD Pointer */
uint res388[30];
/* (0x2_n400) */
uint res400;
uint rbase; /* RxBD Base Address */
uint res408[62];
/* MAC Registers (0x2_n500) */
uint maccfg1; /* MAC Configuration #1 */
uint maccfg2; /* MAC Configuration #2 */
uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
uint hafdup; /* Half-duplex */
uint maxfrm; /* Maximum Frame */
uint res514;
uint res518;
uint res51c;
uint miimcfg; /* MII Management: Configuration */
uint miimcom; /* MII Management: Command */
uint miimadd; /* MII Management: Address */
uint miimcon; /* MII Management: Control */
uint miimstat; /* MII Management: Status */
uint miimind; /* MII Management: Indicators */
uint res538;
uint ifstat; /* Interface Status */
uint macstnaddr1; /* Station Address, part 1 */
uint macstnaddr2; /* Station Address, part 2 */
uint res548[46];
/* (0x2_n600) */
uint res600[32];
/* RMON MIB Registers (0x2_n680-0x2_n73c) */
rmon_mib_t rmon;
uint res740[48];
/* Hash Function Registers (0x2_n800) */
tsec_hash_t hash;
uint res900[128];
/* Pattern Registers (0x2_nb00) */
uint resb00[62];
uint attr; /* Default Attribute Register */
uint attreli; /* Default Attribute Extract Length and Index */
/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
uint resc00[256];
} tsec_t;
#endif /* __TSEC_H */

22
cpu/mpc8xx/cpu.c
View File

@ -80,7 +80,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
switch (k) {
#ifdef CONFIG_MPC866_et_al
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
case 0x08000003: pre = 'M'; suf = ""; m = 1; break;
#else
case 0x00020001: pre = 'p'; suf = ""; break;
@ -130,9 +130,9 @@ static int check_CPU (long clock, uint pvr, uint immr)
putc ('\n');
#ifdef DEBUG
if(clock != measure_gclk()) {
printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
}
if(clock != measure_gclk()) {
printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
}
#endif
return 0;
@ -485,15 +485,15 @@ unsigned long get_tbclk (void)
}
#define PLPRCR_val(a) (((CFG_PLPRCR) & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
#ifdef CONFIG_MPC866_et_al
/* MFN
MFI + -------
MFD + 1
factor = -----------------
(PDF + 1) * 2^S
*/
/* MFN
MFI + -------
MFD + 1
factor = -----------------
(PDF + 1) * 2^S
*/
factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
#else
factor = PLPRCR_val(MF)+1;
#endif

8
cpu/mpc8xx/speed.c
View File

@ -89,10 +89,10 @@ unsigned long measure_gclk(void)
ulong msr_val;
#ifdef CONFIG_MPC866_et_al
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
#endif
/* Reset + Stop Timer 2, no cascading
@ -161,7 +161,7 @@ unsigned long measure_gclk(void)
immr->im_sit.sit_piscr &= ~PISCR_PTE;
#ifdef CONFIG_MPC866_et_al
/* not using OSCM, using XIN, so scale appropriately */
/* not using OSCM, using XIN, so scale appropriately */
return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
#else
return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */

1
cpu/nios/config.mk
View File

@ -22,4 +22,3 @@
#
PLATFORM_RELFLAGS +=

2
cpu/pxa/mmc.c
View File

@ -481,7 +481,7 @@ mmc_init(int verbose)
MMC_CLKRT = 0; /* 20 MHz */
resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
return rc;
}

1
doc/README.INCA-IP
View File

@ -41,7 +41,6 @@ to install a U-Boot image into flash.
go 0xb0000000
Ethernet autonegotiation needs some time to complete. Instead of
delaying the boot process in all cases, we just start the
autonegotiation process when U-Boot comes up and that is all. Most

535
doc/README.mpc85xxads Normal file
View File

@ -0,0 +1,535 @@
Motorola MPC8540ADS and MPC8560ADS board
Xianghua Xiao(X.Xiao@motorola.com)
Created 10/15/03
-----------------------------------------
1. SWITCH SETTINGS & JUMPERS
1.1 First, make sure the board default setting is consistent with the document
shipped with your board. Then apply the following changes:
SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
SW11[2]='OFF for dracom, ON for draco' (single switch to toggle draco.dracom mode)
SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
SW22[1-4]="OFF OFF ON OFF"
SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
J1 = "Enable Prog" (Make sure your flash is programmable for development)
Ethernet PHY connectors(J47,J56) should be removed if you want to use the ethernet.
1.2 If you want to test PCI functionality with a 33Mhz PCI card, you will have to change
the system clock from the default 66Mhz to 33Mhz by setting SW15[1]="OFF" and
SW17[8]="OFF". After that you may also need double your platform clock(SW6) because
the system clock is now only half of its original value.
1.3 SW6 is a very important switch, it decides your platform clock and CPU clock based on
the on-board system clock(default 66MHz). Check the document along with your board
for details.
2. MEMORY MAP TO WORK WITH LINUX KERNEL
2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
linux kernel, you can customize it based on your system requirements:
DDR: 0x00000000-0x1fffffff (max 512MB)
PCI: 0xe0000000-0xefffffff (256MB)
RIO: 0xf0000000-0xf7ffffff (128MB)
Local SDRAM: 0xf8000000-0xfbffffff (64MB)
Local CSx: 0xfc000000-0xfdefffff (31MB) BCSR,RTC,ATM config,etc.
CCSRBAR: 0xfdf00000-0xfdffffff (1MB)
Flash: 0xfe000000-0xffffffff (max 32MB)
2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. Hope you will be
able to download them from linuxppc-2.4 public source by the time you are reading
this. Please make sure the kernel's ppcboot.h is consistent with U-Boot's u-boot.h,
then you can use two default configuration files in the kernel source as a test:
arch/ppc/configs/mpc8540ads_defconfig
arch/ppc/configs/mpc8560ads_defconfig
3. DEFINITIONS AND COMPILATION
3.1 Explanation on NEW definitions in include/configs/MPC8540ADS.h and include/
configs/MPC8560ADS.h
CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
CONFIG_E500 BOOKE e500 family(Motorola)
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
CONFIG_MPC85xx_REV1 MPC85xx Rev 1 Chip, in general you will use a Rev2
chip from Nov.2003. If you still see this definition
while you have a Rev2(and newer) chip,undef this.
CONFIG_MPC8540 MPC8540 specific
CONFIG_MPC8560 MPC8560 specific
CONFIG_MPC8540ADS MPC8540ADS board specific
CONFIG_MPC8560ADS MPC8560ADS board specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can also
manual config the DDR after undef this definition.
CONFIG_DDR_ECC only for ECC DDR module
CONFIG_DDR_DLL possible DLL fix needed for Rev1 chip for more stability.
you can disable this if you're having a newer chip.
CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into localbus
SDRAM and treat localbus SDRAM as a flash. We use this
memory based U-Boot before flash is working while Metrowerks
and Windriver are still working on their flash/JTAG tools.
if you can program the flash directly, undef this.
Other than the above definitions, the rest in the config files are straightforward.
3.2 Compilation
export CROSS_COMPILE=your-cross-compile-prefix(assuming you're using BASH shell)
cd u-boot
make distclean
make MPC8560ADS_config (or make MPC8540ADS_config)
make
4. Note on the 10/100/1000 Ethernet controller:
4.1 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC ethernet. If that
happens, you can try the following steps to make network work:
MPC8560ADS>tftp 1000000 pImage
(if it hangs, use Ctrl-C to quit)
MPC8560ADS>nm fdf24524
>0
>1
>. (to quit this memory operation)
MPC8560ADS>tftp 1000000 pImage
5. Screen dump:
5.1 MPC8540ADS board
U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33)
Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
Board: Motorola MPC8540ADS Board
CPU: 792 MHz
CCB: 264 MHz
DDR: 132 MHz
LBC: 66 MHz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
I2C: ready
DRAM: DDR module detected, total size:128MB.
128 MB
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: MOTOROLA ETHERNE
Hit any key to stop autoboot: 0
MPC8540ADS=> fli
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
Size: 16 MB in 64 Sectors
Sector Start Addresses:
FF000000 FF040000 FF080000 FF0C0000 FF100000
FF140000 FF180000 FF1C0000 FF200000 FF240000
FF280000 FF2C0000 FF300000 FF340000 FF380000
FF3C0000 FF400000 FF440000 FF480000 FF4C0000
FF500000 FF540000 FF580000 FF5C0000 FF600000
FF640000 FF680000 FF6C0000 FF700000 FF740000
FF780000 FF7C0000 FF800000 FF840000 FF880000
FF8C0000 FF900000 FF940000 FF980000 FF9C0000
FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
MPC8540ADS=> imi ff000000
## Checking Image at ff000000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 800594 Bytes = 781.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
MPC8540ADS=> bdinfo
memstart = 0x00000000
memsize = 0x08000000
flashstart = 0xFF000000
flashsize = 0x01000000
flashoffset = 0x00000000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFDF00000
bootflags = 0x40003F80
intfreq = 792 MHz
busfreq = 264 MHz
ethaddr = 00:01:AF:07:9B:8A
eth1addr = 00:01:AF:07:9B:8B
eth2addr = 00:01:AF:07:9B:8C
IP addr = 10.82.0.105
baudrate = 115200 bps
MPC8540ADS=> printenv
bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
bootcmd=bootm 0xff300000 0xff700000
bootdelay=3
baudrate=115200
loads_echo=1
ethaddr=00:01:af:07:9b:8a
eth1addr=00:01:af:07:9b:8b
eth2addr=00:01:af:07:9b:8c
ipaddr=10.82.0.105
serverip=163.12.64.52
rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
gatewayip=10.82.1.254
netmask=255.255.254.0
hostname=MPC8560ADS_PILOT_003
bootfile=pImage
stdin=serial
stdout=serial
stderr=serial
Environment size: 560/8188 bytes
MPC8540ADS=> bootm ff000000
## Booting image at ff000000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 800594 Bytes = 781.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
mpc85xx_init(): exit
id mach(): done
MMU:enter
Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
MMU:hw init
MMU:mapin
MMU:mapin_ram done
MMU:setio
MMU:exit
Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #1 Wed Oct 15 09:05:42 CDT 2003
setup_arch: enter
setup_arch: bootmem
mpc85xx_setup_arch
Host Bridge Vendor ID = 1057
Host Bridge Device ID = 3
Host Bridge header = 0
arch: exit
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
openpic: enter
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
openpic: timer
openpic: external
openpic: spurious
openpic: exit
time_init: decrementer frequency = 33.000000 MHz
Calibrating delay loop... 226.09 BogoMIPS
Memory: 127488k available (1344k kernel code, 448k data, 248k init, 0k highmem)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
pty: 256 Unix98 ptys configured
Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
ttyS00 at 0xfdf04500 (irq = 90) is a 16550A
ttyS01 at 0xfdf04600 (irq = 0) is a 16550A
eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
Copyright (c) 1999-2003 Intel Corporation.
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 8192)
IP-Config: Complete:
device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
host=mpc8540ads-003, domain=, nis-domain=(none),
bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 163.12.64.52
Looking up port of RPC 100005/1 on 163.12.64.52
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 248k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: rp_filter.
Disable TCP/IP Explicit Congestion Notification: done.
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Cleaning: /tmp /var/lock /var/run.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
mpc8540ads-003 login: root
Last login: Thu Jan 1 00:00:07 1970 on console
Linux mpc8540ads-003 2.4.21-rc5 #1 Wed Oct 15 09:05:42 CDT 2003 ppc unknown
root@mpc8540ads-003:~# ls
21142.o aa e100.o hello.o mii.o timer.o
root@mpc8540ads-003:~# /sbin/ifconfig
eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4576 errors:0 dropped:0 overruns:0 frame:0
TX packets:2587 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:100
RX bytes:4457023 (4.2 Mb) TX bytes:437770 (427.5 Kb)
Base address:0x4000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
root@mpc8540ads-003:~# ping 163.12.64.52
PING 163.12.64.52 (163.12.64.52): 56 data bytes
64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.2 ms
64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
--- 163.12.64.52 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.1/0.1/0.2 ms
root@mpc8540ads-003:~#
5.2 MPC8560ADS board
U-Boot 1.0.0-pre (Oct 15 2003 - 13:42:04)
Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
Board: Motorola MPC8560ADS Board
CPU: 792 MHz
CCB: 264 MHz
DDR: 132 MHz
LBC: 66 MHz
CPM: 264 Mhz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
I2C: ready
DRAM: DDR module detected, total size:128MB.
128 MB
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: MOTOROLA ETHERNE
Hit any key to stop autoboot: 3
MPC8560ADS=> bdinfo
memstart = 0x00000000
memsize = 0x08000000
flashstart = 0xFF000000
flashsize = 0x01000000
flashoffset = 0x00000000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFDF00000
bootflags = 0x00000000
vco = 528 MHz
sccfreq = 132 MHz
brgfreq = 132 MHz
intfreq = 792 MHz
cpmfreq = 264 MHz
busfreq = 264 MHz
ethaddr = 00:01:AF:07:9B:8A
eth1addr = 00:01:AF:07:9B:8B
eth2addr = 00:01:AF:07:9B:8C
IP addr = 10.82.0.105
baudrate = 115200 bps
MPC8560ADS=> printenv
bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
bootcmd=bootm 0xff400000 0xff700000
bootdelay=3
baudrate=115200
loads_echo=1
ethaddr=00:01:af:07:9b:8a
eth1addr=00:01:af:07:9b:8b
eth2addr=00:01:af:07:9b:8c
ipaddr=10.82.0.105
serverip=163.12.64.52
rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
gatewayip=10.82.1.254
netmask=255.255.254.0
hostname=MPC8560ADS_PILOT_003
bootfile=pImage
stdin=serial
stdout=serial
stderr=serial
Environment size: 560/8188 bytes
MPC8560ADS=> fli
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
Size: 16 MB in 64 Sectors
Sector Start Addresses:
FF000000 FF040000 FF080000 FF0C0000 FF100000
FF140000 FF180000 FF1C0000 FF200000 FF240000
FF280000 FF2C0000 FF300000 FF340000 FF380000
FF3C0000 FF400000 FF440000 FF480000 FF4C0000
FF500000 FF540000 FF580000 FF5C0000 FF600000
FF640000 FF680000 FF6C0000 FF700000 FF740000
FF780000 FF7C0000 FF800000 FF840000 FF880000
FF8C0000 FF900000 FF940000 FF980000 FF9C0000
FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
MPC8560ADS=> imi ff100000
## Checking Image at ff100000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 755361 Bytes = 737.7 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
MPC8560ADS=> tftp 1000000 pImage.dracom.public
TFTP from server 163.12.64.52; our IP address is 10.82.0.105; sending through gateway 10.82.1.254
Filename 'pImage.dracom.public'.
Load address: 0x1000000
Loading: *#################################################################
#################################################################
##################
done
Bytes transferred = 755425 (b86e1 hex)
MPC8560ADS=> bootm ff100000
## Booting image at ff100000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 755361 Bytes = 737.7 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
mpc85xx_init(): exit
id mach(): done
MMU:enter
Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
MMU:hw init
MMU:mapin
MMU:mapin_ram done
MMU:setio
MMU:exit
Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #2 Wed Oct 15 09:13:46 CDT 2003
setup_arch: enter
setup_arch: bootmem
mpc85xx_setup_arch
Host Bridge Vendor ID = 1057
Host Bridge Device ID = 3
Host Bridge header = 0
arch: exit
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
openpic: enter
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
openpic: timer
openpic: external
openpic: spurious
openpic: exit
time_init: decrementer frequency = 33.000000 MHz
Calibrating delay loop... 226.09 BogoMIPS
Memory: 127624k available (1276k kernel code, 384k data, 236k init, 0k highmem)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
CPM UART driver version 0.01
ttyS0 on SCC1 at 0x8000, BRG1
UART interrupt installed(40)
pty: 256 Unix98 ptys configured
eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
Copyright (c) 1999-2003 Intel Corporation.
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 8192)
IP-Config: Complete:
device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
host=mpc8560ads-003, domain=, nis-domain=(none),
bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 163.12.64.52
Looking up port of RPC 100005/1 on 163.12.64.52
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 236k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: FAILED
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Cleaning: /tmp /var/lock /var/run.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
mpc8560ads-003 login: root
Last login: Thu Jan 1 00:00:05 1970 on console
Linux mpc8560ads-003 2.4.21-rc5 #2 Wed Oct 15 09:13:46 CDT 2003 ppc unknown
root@mpc8560ads-003:~# ls
21142.o aa e100.o hello.o mii.o timer.o
root@mpc8560ads-003:~# cd /
root@mpc8560ads-003:/# ls
bin boot dev etc home lib mnt opt proc root sbin tmp usr var
root@mpc8560ads-003:/# /sbin/ifconfig
eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4608 errors:0 dropped:0 overruns:0 frame:0
TX packets:2610 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:100
RX bytes:4465943 (4.2 Mb) TX bytes:440944 (430.6 Kb)
Base address:0x4000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
root@mpc8560ads-003:/# ping 163.12.64.52
PING 163.12.64.52 (163.12.64.52): 56 data bytes
64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
--- 163.12.64.52 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.1/0.1/0.1 ms
root@mpc8560ads-003:/#

2
doc/README.nios
View File

@ -44,7 +44,6 @@ The Nios port also does not use the long-winded peripheral
structure definitions from the Nios SDK.
2. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
@ -189,7 +188,6 @@ for those interested in contributing:
MSTEP and MUL instructions (e.g. CFG_NIOS_MULT_HW and CFG_NIOS_MULT_MSTEP).
Regards,
--Scott

4
drivers/dc2114x.c
View File

@ -169,7 +169,11 @@ static void dc21x4x_halt(struct eth_device* dev);
extern void dc21x4x_select_media(struct eth_device* dev);
#endif
#if defined(CONFIG_E500)
#define phys_to_bus(a) (a)
#else
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif
static int INL(struct eth_device* dev, u_long addr)
{

5
drivers/eepro100.c
View File

@ -248,8 +248,13 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet,
static int eepro100_recv (struct eth_device *dev);
static void eepro100_halt (struct eth_device *dev);
#if defined(CONFIG_E500)
#define bus_to_phys(a) (a)
#define phys_to_bus(a) (a)
#else
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif
static inline int INW (struct eth_device *dev, u_long addr)
{

11
drivers/pci_indirect.c
View File

@ -32,6 +32,17 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_E500)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
*(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \

6
drivers/sk98lin/Makefile
View File

@ -29,8 +29,8 @@ include $(TOPDIR)/config.mk
LIB := libsk98lin.a
OBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
skxmac2.o skcsum.o #skproc.o
ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
skxmac2.o skcsum.o #skproc.o
OBJS += uboot_skb.o uboot_drv.o
@ -99,5 +99,3 @@ $(LIB): $(OBJS)
sinclude .depend
#########################################################################

10
drivers/sk98lin/h/lm80.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Name: lm80.h
* Name: lm80.h
* Project: GEnesis, PCI Gigabit Ethernet Adapter
* Version: $Revision: 1.4 $
* Date: $Date: 2002/04/25 11:04:10 $
@ -28,16 +28,16 @@
* $Log: lm80.h,v $
* Revision 1.4 2002/04/25 11:04:10 rschmidt
* Editorial changes
*
*
* Revision 1.3 1999/11/22 13:41:19 cgoos
* Changed license header to GPL.
*
*
* Revision 1.2 1999/03/12 13:26:51 malthoff
* remove __STDC__.
*
*
* Revision 1.1 1998/06/19 09:28:31 malthoff
* created.
*
*
*
******************************************************************************/

52
drivers/sk98lin/h/skaddr.h
View File

@ -28,90 +28,90 @@
* $Log: skaddr.h,v $
* Revision 1.26 2002/11/15 07:24:42 tschilli
* SK_ADDR_EQUAL macro fixed.
*
*
* Revision 1.25 2002/06/10 13:55:18 tschilli
* Changes for handling YUKON.
* All changes are internally and not visible to the programmer
* using this module.
*
*
* Revision 1.24 2001/01/22 13:41:34 rassmann
* Supporting two nets on dual-port adapters.
*
*
* Revision 1.23 2000/08/10 11:27:50 rassmann
* Editorial changes.
* Preserving 32-bit alignment in structs for the adapter context.
*
*
* Revision 1.22 2000/08/07 11:10:40 rassmann
* Editorial changes.
*
*
* Revision 1.21 2000/05/04 09:39:59 rassmann
* Editorial changes.
* Corrected multicast address hashing.
*
*
* Revision 1.20 1999/11/22 13:46:14 cgoos
* Changed license header to GPL.
* Allowing overwrite for SK_ADDR_EQUAL.
*
*
* Revision 1.19 1999/05/28 10:56:07 rassmann
* Editorial changes.
*
*
* Revision 1.18 1999/04/06 17:22:04 rassmann
* Added private "ActivePort".
*
*
* Revision 1.17 1999/01/14 16:18:19 rassmann
* Corrected multicast initialization.
*
*
* Revision 1.16 1999/01/04 10:30:36 rassmann
* SkAddrOverride only possible after SK_INIT_IO phase.
*
*
* Revision 1.15 1998/12/29 13:13:11 rassmann
* An address override is now preserved in the SK_INIT_IO phase.
* All functions return an int now.
* Extended parameter checking.
*
*
* Revision 1.14 1998/11/24 12:39:45 rassmann
* Reserved multicast entry for BPDU address.
* 13 multicast entries left for protocol.
*
*
* Revision 1.13 1998/11/13 17:24:32 rassmann
* Changed return value of SkAddrOverride to int.
*
*
* Revision 1.12 1998/11/13 16:56:19 rassmann
* Added macro SK_ADDR_COMPARE.
* Changed return type of SkAddrOverride to SK_BOOL.
*
*
* Revision 1.11 1998/10/28 18:16:35 rassmann
* Avoiding I/Os before SK_INIT_RUN level.
* Aligning InexactFilter.
*
*
* Revision 1.10 1998/10/22 11:39:10 rassmann
* Corrected signed/unsigned mismatches.
*
*
* Revision 1.9 1998/10/15 15:15:49 rassmann
* Changed Flags Parameters from SK_U8 to int.
* Checked with lint.
*
*
* Revision 1.8 1998/09/24 19:15:12 rassmann
* Code cleanup.
*
*
* Revision 1.7 1998/09/18 20:22:13 rassmann
* Added HW access.
*
*
* Revision 1.6 1998/09/04 19:40:20 rassmann
* Interface enhancements.
*
*
* Revision 1.5 1998/09/04 12:40:57 rassmann
* Interface cleanup.
*
*
* Revision 1.4 1998/09/04 12:14:13 rassmann
* Interface cleanup.
*
*
* Revision 1.3 1998/09/02 16:56:40 rassmann
* Updated interface.
*
*
* Revision 1.2 1998/08/27 14:26:09 rassmann
* Updated interface.
*
*
* Revision 1.1 1998/08/21 08:31:08 rassmann
* First public version.
*
@ -401,7 +401,7 @@ extern int SkAddrGmacPromiscuousChange(
SK_AC *pAC,
SK_IOC IoC,
SK_U32 PortNumber,
int NewPromMode);
int NewPromMode);
extern int SkAddrSwap(
SK_AC *pAC,

18
drivers/sk98lin/h/skcsum.h
View File

@ -28,34 +28,34 @@
* $Log: skcsum.h,v $
* Revision 1.9 2001/02/06 11:21:39 rassmann
* Editorial changes.
*
*
* Revision 1.8 2001/02/06 11:15:36 rassmann
* Supporting two nets on dual-port adapters.
*
*
* Revision 1.7 2000/06/29 13:17:05 rassmann
* Corrected reception of a packet with UDP checksum == 0 (which means there
* is no UDP checksum).
*
*
* Revision 1.6 2000/02/28 12:33:44 cgoos
* Changed C++ style comments to C style.
*
*
* Revision 1.5 2000/02/21 12:10:05 cgoos
* Fixed license comment.
*
*
* Revision 1.4 2000/02/21 11:08:37 cgoos
* Merged changes back into common source.
*
*
* Revision 1.1 1999/07/26 14:47:49 mkarl
* changed from common source to windows specific source
* added return SKCS_STATUS_IP_CSUM_ERROR_UDP and
* SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester
* changes for Tx csum offload
*
*
* Revision 1.2 1998/09/04 12:16:34 mhaveman
* Checked in for Stephan to allow compilation.
* -Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic
* -Added prototype for SkCsEvent()
*
*
* Revision 1.1 1998/09/01 15:36:53 swolf
* initial revision
*
@ -130,7 +130,7 @@
* SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
* SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
* SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
* SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
* SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
*/
#ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */
#define SKCS_STATUS int /* Define status type. */

24
drivers/sk98lin/h/skdebug.h
View File

@ -28,42 +28,42 @@
* Revision 1.12 2002/07/15 15:37:13 rschmidt
* Power Management support
* Editorial changes
*
*
* Revision 1.11 2002/04/25 11:04:39 rschmidt
* Editorial changes
*
*
* Revision 1.10 1999/11/22 13:47:40 cgoos
* Changed license header to GPL.
*
*
* Revision 1.9 1999/09/14 14:02:43 rwahl
* Added SK_DBGMOD_PECP.
*
*
* Revision 1.8 1998/11/25 08:31:54 gklug
* fix: no C++ comments allowed in common sources
*
*
* Revision 1.7 1998/11/24 16:47:24 swolf
* Driver may now define its own SK_DBG_MSG() (eg. in "h/skdrv1st.h").
*
*
* Revision 1.6 1998/10/28 10:23:55 rassmann
* ADDED SK_DBGMOD_ADDR.
*
*
* Revision 1.5 1998/10/22 09:43:55 gklug
* add: CSUM module
*
*
* Revision 1.4 1998/10/01 07:54:44 gklug
* add: PNMI debug module
*
*
* Revision 1.3 1998/09/18 08:32:34 afischer
* Macros changed according ssr-spec.:
* SK_DBG_MODCHK -> SK_DBG_CHKMOD
* SK_DBG_CATCHK -> SK_DBG_CHKCAT
*
*
* Revision 1.2 1998/07/03 14:38:25 malthoff
* Add category SK_DBGCAT_FATAL.
*
*
* Revision 1.1 1998/06/19 13:39:01 malthoff
* created.
*
*
*
******************************************************************************/

37
drivers/sk98lin/h/skdrv1st.h
View File

@ -28,50 +28,50 @@
* $Log: skdrv1st.h,v $
* Revision 1.11 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
*
*
* Revision 1.10 2002/10/02 12:46:02 mlindner
* Add: Support for Yukon
*
*
* Revision 1.9.2.2 2001/12/07 12:06:42 mlindner
* Fix: malloc -> slab changes
*
*
* Revision 1.9.2.1 2001/03/12 16:50:59 mlindner
* chg: kernel 2.4 adaption
*
*
* Revision 1.9 2001/01/22 14:16:04 mlindner
* added ProcFs functionality
* Dual Net functionality integrated
* Rlmt networks added
*
*
* Revision 1.8 2000/02/21 12:19:18 cgoos
* Added default for SK_DEBUG_CHKMOD/_CHKCAT
*
*
* Revision 1.7 1999/11/22 13:50:00 cgoos
* Changed license header to GPL.
* Added overwrite for several functions.
* Removed linux 2.0.x definitions.
* Removed PCI vendor ID definition (now in kernel).
*
*
* Revision 1.6 1999/07/27 08:03:33 cgoos
* Changed SK_IN/OUT macros to readX/writeX instead of memory
* accesses (necessary for ALPHA).
*
*
* Revision 1.5 1999/07/23 12:10:21 cgoos
* Removed SK_RLMT_SLOW_LOOKAHEAD define.
*
*
* Revision 1.4 1999/07/14 12:31:13 cgoos
* Added SK_RLMT_SLOW_LOOKAHEAD define.
*
*
* Revision 1.3 1999/04/07 10:12:54 cgoos
* Added check for KERNEL and OPTIMIZATION defines.
*
*
* Revision 1.2 1999/03/01 08:51:47 cgoos
* Fixed pcibios_read/write definitions.
*
*
* Revision 1.1 1999/02/16 07:40:49 cgoos
* First version.
*
*
*
*
*
******************************************************************************/
@ -179,7 +179,7 @@ typedef struct s_AC SK_AC;
#define SK_MEM_MAPPED_IO
// #define SK_RLMT_SLOW_LOOKAHEAD
/* #define SK_RLMT_SLOW_LOOKAHEAD */
#define SK_MAX_MACS 2
#define SK_MAX_NETS 2
@ -199,9 +199,9 @@ typedef struct s_DrvRlmtMbuf SK_MBUF;
#define SK_STRCMP(pStr1,pStr2) strcmp((char*)(pStr1),(char*)(pStr2))
/* macros to access the adapter */
#define SK_OUT8(b,a,v) writeb((v), ((b)+(a)))
#define SK_OUT16(b,a,v) writew((v), ((b)+(a)))
#define SK_OUT32(b,a,v) writel((v), ((b)+(a)))
#define SK_OUT8(b,a,v) writeb((v), ((b)+(a)))
#define SK_OUT16(b,a,v) writew((v), ((b)+(a)))
#define SK_OUT32(b,a,v) writel((v), ((b)+(a)))
#define SK_IN8(b,a,pv) (*(pv) = readb((b)+(a)))
#define SK_IN16(b,a,pv) (*(pv) = readw((b)+(a)))
#define SK_IN32(b,a,pv) (*(pv) = readl((b)+(a)))
@ -262,4 +262,3 @@ extern void SkDbgPrintf(const char *format,...);
extern void SkErrorLog(SK_AC*, int, int, char*);
#endif

86
drivers/sk98lin/h/skdrv2nd.h
View File

@ -28,19 +28,19 @@
* $Log: skdrv2nd.h,v $
* Revision 1.15 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
*
*
* Revision 1.14 2003/02/25 13:26:26 mlindner
* Add: Support for various vendors
*
*
* Revision 1.13 2002/10/02 12:46:02 mlindner
* Add: Support for Yukon
*
*
* Revision 1.12.2.2 2001/09/05 12:14:50 mlindner
* add: New hardware revision int
*
*
* Revision 1.12.2.1 2001/03/12 16:50:59 mlindner
* chg: kernel 2.4 adaption
*
*
* Revision 1.12 2001/03/01 12:52:15 mlindner
* Fixed ring size
*
@ -66,28 +66,28 @@
*
* Revision 1.7 1999/09/28 12:38:21 cgoos
* Added CheckQueue to SK_AC.
*
*
* Revision 1.6 1999/07/27 08:04:05 cgoos
* Added checksumming variables to SK_AC.
*
*
* Revision 1.5 1999/03/29 12:33:26 cgoos
* Rreversed to fine lock granularity.
*
*
* Revision 1.4 1999/03/15 12:14:02 cgoos
* Added DriverLock to SK_AC.
* Removed other locks.
*
*
* Revision 1.3 1999/03/01 08:52:27 cgoos
* Changed pAC->PciDev declaration.
*
*
* Revision 1.2 1999/02/18 10:57:14 cgoos
* Removed SkDrvTimeStamp prototype.
* Fixed SkGeOsGetTime prototype.
*
*
* Revision 1.1 1999/02/16 07:41:01 cgoos
* First version.
*
*
*
*
*
******************************************************************************/
@ -126,40 +126,40 @@
result = SK_FALSE; /* default */ \
/* 3Com (0x10b7) */ \
if (pdev->vendor == 0x10b7) { \
/* Gigabit Ethernet Adapter (0x1700) */ \
if ((pdev->device == 0x1700)) { \
result = SK_TRUE; \
} \
/* Gigabit Ethernet Adapter (0x1700) */ \
if ((pdev->device == 0x1700)) { \
result = SK_TRUE; \
} \
/* SysKonnect (0x1148) */ \
} else if (pdev->vendor == 0x1148) { \
/* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \
/* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \
if ((pdev->device == 0x4300) || \
(pdev->device == 0x4320)) { \
result = SK_TRUE; \
} \
/* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \
/* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \
if ((pdev->device == 0x4300) || \
(pdev->device == 0x4320)) { \
result = SK_TRUE; \
} \
/* D-Link (0x1186) */ \
} else if (pdev->vendor == 0x1186) { \
/* Gigabit Ethernet Adapter (0x4c00) */ \
if ((pdev->device == 0x4c00)) { \
result = SK_TRUE; \
} \
/* Gigabit Ethernet Adapter (0x4c00) */ \
if ((pdev->device == 0x4c00)) { \
result = SK_TRUE; \
} \
/* CNet (0x1371) */ \
} else if (pdev->vendor == 0x1371) { \
/* GigaCard Network Adapter (0x434e) */ \
if ((pdev->device == 0x434e)) { \
result = SK_TRUE; \
} \
/* GigaCard Network Adapter (0x434e) */ \
if ((pdev->device == 0x434e)) { \
result = SK_TRUE; \
} \
/* Linksys (0x1737) */ \
} else if (pdev->vendor == 0x1737) { \
/* Gigabit Network Adapter (0x1032) */ \
/* Gigabit Network Adapter (0x1064) */ \
if ((pdev->device == 0x1032) || \
(pdev->device == 0x1064)) { \
result = SK_TRUE; \
} \
/* Gigabit Network Adapter (0x1032) */ \
/* Gigabit Network Adapter (0x1064) */ \
if ((pdev->device == 0x1032) || \
(pdev->device == 0x1064)) { \
result = SK_TRUE; \
} \
} else { \
result = SK_FALSE; \
result = SK_FALSE; \
} \
}
@ -188,7 +188,6 @@ struct s_DrvRlmtMbuf {
};
/*
* ioctl definitions
*/
@ -309,7 +308,6 @@ struct s_TxD {
#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
/* The offsets of registers in the TX and RX queue control io area ***********/
#define RX_Q_BUF_CTRL_CNT 0x00
@ -441,7 +439,7 @@ struct s_DevNet {
int Mtu;
int Up;
SK_AC *pAC;
};
};
typedef struct s_TxPort TX_PORT;
@ -504,7 +502,7 @@ struct s_AC {
SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
int RlmtMode; /* link check mode to set */
int RlmtNets; /* Number of nets */
SK_IOC IoBase; /* register set of adapter */
int BoardLevel; /* level of active hw init (0-2) */
char DeviceStr[80]; /* adapter string from vpd */
@ -520,7 +518,7 @@ struct s_AC {
struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */
int RxBufSize; /* length of receive buffers */
#if 0
struct net_device_stats stats; /* linux 'netstat -i' statistics */
struct net_device_stats stats; /* linux 'netstat -i' statistics */
#endif
int Index; /* internal board index number */
@ -560,6 +558,4 @@ struct s_AC {
};
#endif /* __INC_SKDRV2ND_H */

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