H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.
Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This syncs the sun8i-h3-nanopi-neo.dts from the Linux tree, from tag
v5.18-rc1.
The alias is required to enable automatic MAC address generation.
Signed-off-by: Baltazár Radics <baltazar.radics@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Create a do-nothing driver for each sunxi pin controller variant.
Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
colibri-imx6ull ethernet device is fec2, while the optional secondary
ethernet is fec1, update the ethernet aliases in the .dts file so that
ethaddr is set to fec2 and eth1addr to fec1.
Without this change the ethernet interfaces have a different
mac address between Linux and U-Boot.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
When migrating SYS_IMMR, I didn't allow for boards to provide
non-default values here. This lead to an incorrect migration on the
platforms where CONFIG_SYS_IMMR is set to CONFIG_SYS_CCSRBAR and
CONFIG_SYS_CSSRBAR is NOT the same as CONFIG_SYS_CCSRBAR_DEFAULT. Add
text to the prompt so that non-default values can be used and re-migrate
the platforms that have CONFIG_SYS_IMMR=CONFIG_SYS_CSSRBAR where
CONFIG_SYS_CSSRBAR != CONFIG_SYS_CCSRBAR_DEFAULT.
Fixes: be7dbb60c5 ("Convert CONFIG_SYS_IMMR to Kconfig")
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Pali Rohár <pali@kernel.org>
The current approach for setting the environment variables that
describe the memory layout runs the risk of overlapping with
reserved memory regions. Use the lmb code to derive the addresses
for these variables instead.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The firmware on larger NVMe drives needs more than 100ms to come up.
Change the timeout to 1s.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit f11513d997 ("net: phy: realtek: Add tx/rx delay config for
8211e") made the Realtek PHY driver honour the phy-mode DT property,
to set up the proper delay scheme for the RX and TX lines. A similar
change in the kernel revealed that those properties were mostly wrong.
The kernel DTs got updated over the last few months, but we were missing
out on the U-Boot version.
Just sync in the phy-mode properties from the mainline kernel,
v5.17-rc7, to avoid the breaking DT sync that late in the cycle.
This fixes Ethernet operation on the affected boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Commit 5bc4cd05d7 ("sunxi: move non-essential code out of s_init()")
moved the call to eth_init_board() from s_init() into board_init_f().
This means it's now only called from the SPL, which makes sense for
most of the other moved low-level functions. However the GMAC pinmux and
clock setup in eth_init_board() was not happy about that, so it broke
the sun7i GMAC.
Since Ethernet is of no use in the SPL anyway, just move the call into
board_init(), which is only run in U-Boot proper.
This fixes Ethernet operation for the A20 SoCs, which broke in
v2022.04-rc1, with the above mentioned commit.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Petr Štetiar <ynezz@true.cz> [a20-olinuxino-lime2]
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke SPI support on some Espressobin boards and results in
following U-Boot error:
Loading Environment from SPIFlash... jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f7, 30, 0b
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
Before that commit DT node for SPI was called 'spi-flash@0' and after
that commit it is called 'flash@0'. Before that commit 'spi-max-frequency'
was set to 50000000 and after it is 104000000.
Rename DT node 'spi-flash@0 in armada-3720-espressobin-u-boot.dtsi to
'flash@0' and set custom U-Boot 'spi-max-frequency' back to 50000000.
With this change SPI is working on Espressobin again and it is detected
with JEDEC ids ef, 60, 16 on our tested unit.
Loading Environment from SPIFlash... SF: Detected w25q32dw with page size 256 Bytes, erase size 4 KiB, total 4 MiB
OK
Note that it is unknown why spi-max-frequency with value 104000000 does not
work in U-Boot as it works fine with Linux kernel. Also note that in
defconfig file configs/mvebu_espressobin-88f3720_defconfig is set option
CONFIG_SF_DEFAULT_SPEED=40000000 which is different value than in DT.
Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke USB port on Turris MOX, because in Linux' DTS the bus
voltage supply is described as a `phy-supply` property of connector
node, a mechanism that is not supported in U-Boot yet.
For now, fix this by adding `vbus-supply` to usb3 node.
Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
U-Boot can be chainloaded from vendor firmware on ARM64 chromebooks from
a GPT partition (roughly the same as in doc/chromium/chainload.rst), but
an appropriate image header must be built-in to the U-Boot binary by
enabling LINUX_KERNEL_IMAGE_HEADER.
This header has a field for an image load offset from 2MiB alignment
which must also be customized through LNX_KRNL_IMG_TEXT_OFFSET_BASE.
Set it equal to SYS_TEXT_BASE by default for Rockchip boards, which
happens to make this offset zero and works fine on chromebook_kevin
both for chainloading and bare-metal use.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for Kevin, an RK3399-based convertible chromebook that is
very similar to Bob. This patch is mostly based on existing support for
Bob, with only minor changes for Kevin-specific things.
Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
has an unknown event code reference which has to be defined, set it
to the Linux counterpart. The new defconfig is copied from Bob with the
diffconfig:
DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
+TARGET_CHROMEBOOK_KEVIN y
With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
display with the keyboard working, but cannot boot into Linux for
unknown reasons.
eMMC starts in a working state but fails to re-init, microSD card works
but at a lower-than-expected speed, USB works but causes a hang on
de-init. There are known workarounds to solve eMMC and USB issues.
Cc: Marty E. Plummer <hanetzer@startmail.com>
Cc: Simon Glass <sjg@chromium.org>
[Alper: commit message, resync config with Bob, update MAINTAINERS,
add to Rockchip doc, add Kconfig help message, set regulator]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This adds some devicetree settings for the Gru-based boards, based on
what works on a Kevin board.
Gru-based boards usually have an 8MiB SPI flash chip and boot from it.
Make the u-boot.rom file intended to be flashed on it match its size.
Add properties for booting from SPI, and only try to boot from SPI as
MMC and SD card don't seem to work in SPL yet.
The Chromium OS EC needs a delay between transactions so it can get
itself ready. Also it currently uses a non-standard way of specifying
the interrupt. Add these so that the EC works reliably.
The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel
property to find the panel it should work on. Add the property for the
Gru-based boards.
The U-Boot GPIO controlled regulator driver only considers the
"enable-gpios" devicetree property, not the singular "enable-gpio" one.
Some devicetree source files have the singular form as they were added
to Linux kernel when it used that form, and imported to U-Boot as is.
Fix one instance of this in the Gru boards' devicetree to the form that
works in U-Boot.
The PWM controlled regulator driver complains that there is no init
voltage set for a regulator it drives, though it's not clear which one.
Set them all to the voltage levels coreboot sets them: 900 mV.
The RK3399 SoC needs to know the voltage level that some supplies
provides, including one fixed 1.8V audio-related regulator. Although
this synchronization is currently statically done in the board init
functions, a not-so-hypothetical driver that does this dynamically would
query the regulator only to get -ENODATA and be confused. Make sure
U-Boot knows this supply is at 1.8V by setting its limits to that.
Most of this is a reapplication of commit 08c85b57a5 ("rockchip: gru:
Add extra device-tree settings") whose changes were removed during a
sync with Linux at commit 167efc2c7a ("arm64: dts: rk3399: Sync
v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so
they don't get lost again.
Signed-off-by: Simon Glass <sjg@chromium.org>
[Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke network on Turris MOX, because the SOC's MDIO bus in
U-Boot currently isn't probed via DM as it's own device, but is
registered as part of mvneta's driver, which means that pinctrl
definitions are not parsed for the MDIO bus node. Also mvneta driver
does not consider "phy-handle" property, only "phy".
For now, fix this by adding armada-3720-turris-mox-u-boot.dtsi file
returning the MDIO to how it was defined previously.
A better solution (using proper mvmdio DM driver) is being work on, but
will need testing on various boards, and we need the bug fixed now for
the upcoming release.
Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
The Linux PLIC interrupt-controller driver actually initializes the hart
context registers in the PLIC driver exactly in the same order as
specified in the interrupts-extended device tree property. See the device
tree binding [1].
The ordering of the interrupts is therefore essential in order to
configure the PLIC correctly.
Fix the order so that we will have sane IRQ behavior when booting Linux
with the u-boot device tree.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the
power bit offset of the fpioa device to be specified as a single
property "canaan,k210-sysctl-power".
Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset"
properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel
requirements. This new property is parsed using the existing function
dev_read_phandle_with_args().
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Linux drivers for many of the K210 peripherals depend on the power bus
clock to be specified. Add the missing clocks and their names to avoid
problems when booting Linux using u-boot DT.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This patch configures U-Boot SPL for DHCOM SoM to permit DFU upload of
SPL and subsequent u-boot.itb for recovery or commissioning purposes.
The DFU usage procedure is identical to STM32MP1 DHCOR SoM, see commit
3919aa1722 ("ARM: dts: stm32: Add DFU support for DHCOR recovery") ,
except for switching the SoM into DFU mode. By default, the DHCOM SoM
has no dedicated mechanism for setting BOOTn straps into UART/USB mode,
therefore to enter DFU mode, the SoC must fail to boot from boot media
which can be selected by the BOOTn strap override mechanism first and
then fall back to DFU mode.
In case of a SoM with pre-populated BOOTn strap override button, power
the system off, remove microSD card (if applicable), hold down the BOOTn
strap override button located between eMMC and SoM edge connector, power
on the SoM. The SoC will fail to boot from SD card and fall back into
DFU mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Implement PSCI system suspend and placement of DRAM into SSR while the
CPUs are in suspend. This saves non-trivial amount of power in suspend,
on 2x W632GU6NB-15 ~710mW.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
The vdd_io regulator is present only on DHCOR SoM configured for 1V8 IO,
as populated on Avenger96, but not present on 3V3 DHCOR SoM. Move these
extras to Avenger96 u-boot DT extras.
Fixes: 3919aa1722 ("ARM: dts: stm32: Add DFU support for DHCOR recovery")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Fix the following warning in SPL and make sure that even DTs which
enforce Vbus detection using u-boot,force-vbus-detection;, the DFU
in SPL will work.
dwc2-udc-otg usb-otg@49000000: prop pinctrl-0 index 0 invalid phandle
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Device tree alignment with Linux kernel v5.17-rc1
- ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins
on STM32MP15 DKx boards
- ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
- ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add the missing @dev reference in some function description.
Fixes: b66bfdf238 ("arm: stm32mp: bsec: migrate trace to log macro")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add support of the permanent lock support in U-Boot proper
when BSEC is not managed by secure monitor (TF-A SP_MIN or OP-TEE).
This patch avoid issue with stm32key command and fuse command
on basic boot for this missing feature of U-Boot BSEC driver.
Reported-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Remap PCI I/O space to the bus address 0x0 in the Armada 37xx device-tree
in order to support legacy I/O port based cards which have hardcoded I/O
ports in low address space.
Some legacy PCI I/O based cards do not support 32-bit I/O addressing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This enum is currently anonymous. Add a name so it can be used in the
code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Commit 7945caf22c ("arm: sunxi: Enable SPI/SPI-FLASH support for A64")
selected CONFIG_SPI by default on all Allwinner A64 boards, even though
only 4 out of the 14 A64 boards have a SPI flash chip. All other SoCs
had to manually select DM_SPI and friends, even though they are a
platform property (the sunxi SPI driver is DM_SPI only).
Clean this up to allow easy selection of SPI flash support in U-Boot
proper, by selecting DM_SPI and DM_SPI_FLASH *if* CONFIG_SPI is
selected, for *all* Allwinner SoCs. This simplifies the defconfig for
two Libretech boards already.
Also remove the forced CONFIG_SPI from the A64 Kconfig, instead let the
four boards which allow SPI booting select this explicitly.
Any board wishing to support SPI flash in U-Boot proper now just defines
CONFIG_SPI and CONFIG_SPI_FLASH_<vendor> in its defconfig, Kconfig takes
care of the rest.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Recent unrelated fixes (9876ae7db6) revealed that we were missing bits
from 2af181b53e in the IOT2050 dt. Add them, but only for main U-Boot.
SPL loads from QSPI only, thus cannot use DMA.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
We only want to call do_board_detect() if CONFIG_TI_I2C_BOARD_DETECT
is set. Same as done for am64.
This makes it possible to add a custom am65 based board design to
U-Boot that does not use this board detection mechanism.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
The a3700_fdt_fix_pcie_regions() function still computes nonsense.
It computes the fixup offset from the PCI address taken from the first
row of the "ranges" array, which means that:
- PCI address must equal CPU address (otherwise the computed fix offset
will be wrong),
- the first row must contain the lowest address.
This is the case for the default device-tree, which is why we didn't
notice it.
It also adds the fixup offset to all PCI and CPU addresses, which is
wrong.
Instead:
1) The fixup offset must be computed from the CPU address, not PCI
address.
2) The fixup offset must be computed from the row containing the lowest
CPU address, which is not necessarily contained in the first row.
3) The PCI address - the address to which the PCIe controller remaps the
address space as seen from the point of view of the PCIe device -
must be fixed by the fix offset in the same way as the CPU address
only in the special case when the CPU adn PCI addresses are the same.
Same addresses means that remapping is disabled, and thus if we
change the CPU address, we need also to change the PCI address so
that the remapping is still disabled afterwards.
Consider an example:
The ranges entries contain:
PCI address CPU address
70000000 EA000000
E9000000 E9000000
EB000000 EB000000
By default CPU PCIe window is at: E8000000 - F0000000
Consider the case when TF-A moves it to: F2000000 - FA000000
Until now the function would take the PCI address of the first entry:
70000000, and the new base, F2000000, to compute the fix offset:
F2000000 - 70000000 = 82000000, and then add 8200000 to all addresses,
resulting in
PCI address CPU address
F2000000 6C000000
6B000000 6B000000
6D000000 6D000000
which is complete nonsense - none of the CPU addresses is in the
requested window.
Now it will take the lowest CPU address, which is in second row,
E9000000, and compute the fix offset F2000000 - E9000000 = 09000000,
and then add it to all CPU addresses and those PCI addresses which
equal to their corresponding CPU addresses, resulting in
PCI address CPU address
70000000 F3000000
F2000000 F2000000
F4000000 F4000000
where all of the CPU addresses are in the needed window.
Fixes: 4a82fca8e3 ("arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
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Merge tag 'u-boot-at91-fixes-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-atmel fixes for the 2022.04 cycle:
This fixes set includes only a single fix for the Ethernet on sama7g5ek
board which is broken at the moment.
Commit 88998f7775 ("arm: arm926ej-s: Add sunxi code") introduced
the ARM926 version of the code to save and restore some FEL state, to
be able to return to the BROM FEL code after the SPL has run.
However during review a change was made, that happened to mess up the
register restore part, so SCTLR and CPSR ended up with the wrong values,
breaking return to FEL.
Use the same offset that we actually save those registers to, to make
FEL booting actually work on the Lichee Pi Nano.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Enable SPI boot in SPL on SUNIV architecture and use
it in the licheepi nano that uses the F1C100s.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: adaptation to Upstream U-Boot]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
