stm32mp: psci: Implement PSCI system suspend and DRAM SSR
Implement PSCI system suspend and placement of DRAM into SSR while the CPUs are in suspend. This saves non-trivial amount of power in suspend, on 2x W632GU6NB-15 ~710mW. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Marek Vasut
Patrice Chotard
parent
0d44ad8bb4
commit
b49105320a
@ -16,8 +16,11 @@
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*/
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#define STM32_RCC_BASE 0x50000000
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#define STM32_PWR_BASE 0x50001000
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#define STM32_SYSCFG_BASE 0x50020000
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#define STM32_DBGMCU_BASE 0x50081000
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#define STM32_FMC2_BASE 0x58002000
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#define STM32_DDRCTRL_BASE 0x5A003000
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#define STM32_DDRPHYC_BASE 0x5A004000
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#define STM32_TZC_BASE 0x5C006000
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#define STM32_ETZPC_BASE 0x5C007000
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#define STM32_STGEN_BASE 0x5C008000
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@ -11,19 +11,152 @@
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <hang.h>
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#include <linux/bitops.h>
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#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
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#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
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/* PWR */
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#define PWR_CR3 0x0c
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#define PWR_MPUCR 0x10
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#define MPIDR_AFF0 GENMASK(7, 0)
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#define PWR_CR3_DDRSREN BIT(10)
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#define PWR_CR3_DDRRETEN BIT(12)
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#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
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#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
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#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
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#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
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#define PWR_MPUCR_PDDS BIT(0)
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#define PWR_MPUCR_CSTDBYDIS BIT(3)
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#define PWR_MPUCR_CSSF BIT(9)
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#define STM32MP1_PSCI_NR_CPUS 2
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/* RCC */
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#define RCC_DDRITFCR 0xd8
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#define RCC_DDRITFCR_DDRC1EN BIT(0)
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#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
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#define RCC_DDRITFCR_DDRC2EN BIT(2)
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#define RCC_DDRITFCR_DDRC2LPEN BIT(3)
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#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
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#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
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#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
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#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
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#define RCC_DDRITFCR_AXIDCGEN BIT(8)
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#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
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#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
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#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
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#define RCC_DDRITFCR_GSKPCTRL BIT(24)
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#define RCC_MP_SREQSETR 0x104
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#define RCC_MP_SREQCLRR 0x108
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#define RCC_MP_CIER 0x414
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#define RCC_MP_CIFR 0x418
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#define RCC_MP_CIFR_WKUPF BIT(20)
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/* SYSCFG */
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#define SYSCFG_CMPCR 0x20
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#define SYSCFG_CMPCR_SW_CTRL BIT(2)
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#define SYSCFG_CMPENSETR 0x24
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#define SYSCFG_CMPENCLRR 0x28
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#define SYSCFG_CMPENR_MPUEN BIT(0)
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/* DDR Controller registers offsets */
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#define DDRCTRL_STAT 0x004
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#define DDRCTRL_PWRCTL 0x030
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#define DDRCTRL_PWRTMG 0x034
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#define DDRCTRL_HWLPCTL 0x038
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#define DDRCTRL_DFIMISC 0x1b0
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#define DDRCTRL_SWCTL 0x320
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#define DDRCTRL_SWSTAT 0x324
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#define DDRCTRL_PSTAT 0x3fc
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#define DDRCTRL_PCTRL_0 0x490
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#define DDRCTRL_PCTRL_1 0x540
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/* DDR Controller Register fields */
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#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
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#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 0x1
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#define DDRCTRL_STAT_OPERATING_MODE_SR 0x3
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#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
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#define DDRCTRL_STAT_SELFREF_TYPE_ASR (0x3 << 4)
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#define DDRCTRL_STAT_SELFREF_TYPE_SR (0x2 << 4)
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#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
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#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
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#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
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#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
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#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
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#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
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#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
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#define DDRCTRL_SWCTL_SW_DONE BIT(0)
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#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
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#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 BIT(0)
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#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 BIT(1)
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#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 BIT(16)
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#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 BIT(17)
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#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
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/* DDR PHY registers offsets */
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#define DDRPHYC_PIR 0x004
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#define DDRPHYC_PGSR 0x00c
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#define DDRPHYC_ACDLLCR 0x014
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#define DDRPHYC_ACIOCR 0x024
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#define DDRPHYC_DXCCR 0x028
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#define DDRPHYC_DSGCR 0x02c
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#define DDRPHYC_ZQ0CR0 0x180
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#define DDRPHYC_DX0DLLCR 0x1cc
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#define DDRPHYC_DX1DLLCR 0x20c
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#define DDRPHYC_DX2DLLCR 0x24c
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#define DDRPHYC_DX3DLLCR 0x28c
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/* DDR PHY Register fields */
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#define DDRPHYC_PIR_INIT BIT(0)
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#define DDRPHYC_PIR_DLLSRST BIT(1)
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#define DDRPHYC_PIR_DLLLOCK BIT(2)
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#define DDRPHYC_PIR_ITMSRST BIT(4)
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#define DDRPHYC_PGSR_IDONE BIT(0)
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#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
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#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
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#define DDRPHYC_ACIOCR_ACOE BIT(1)
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#define DDRPHYC_ACIOCR_ACPDD BIT(3)
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#define DDRPHYC_ACIOCR_ACPDR BIT(4)
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#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
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#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
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#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
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#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
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#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(20, 18)
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#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
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#define DDRPHYC_DXCCR_DXPDD BIT(2)
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#define DDRPHYC_DXCCR_DXPDR BIT(3)
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#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
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#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
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#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
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#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
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#define DDRPHYC_DSGCR_NL2PD BIT(24)
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#define DDRPHYC_DSGCR_CKOE BIT(28)
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#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
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#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
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#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xca7face0
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#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xca7face1
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#define MPIDR_AFF0 GENMASK(7, 0)
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#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
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#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
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#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
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#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
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#define STM32MP1_PSCI_NR_CPUS 2
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#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
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#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
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#endif
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@ -98,6 +231,7 @@ s32 __secure psci_features(u32 function_id, u32 psci_fid)
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case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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case ARM_PSCI_0_2_FN_SYSTEM_OFF:
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case ARM_PSCI_0_2_FN_SYSTEM_RESET:
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case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
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return 0x0;
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}
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return ARM_PSCI_RET_NI;
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@ -222,3 +356,374 @@ void __secure psci_system_off(void)
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while (1)
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wfi();
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}
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static void __secure secure_udelay(unsigned int delay)
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{
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u32 freq = cp15_read_cntfrq() / 1000000;
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u64 start, end;
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delay *= freq;
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
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for (;;) {
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
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if ((end - start) > delay)
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break;
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}
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}
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static int __secure secure_waitbits(u32 reg, u32 mask, u32 val)
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{
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u32 freq = cp15_read_cntfrq() / 1000000;
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u32 delay = 500 * freq; /* 500 us */
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u64 start, end;
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u32 tmp;
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
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for (;;) {
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tmp = readl(reg);
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tmp &= mask;
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if ((tmp & val) == val)
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return 0;
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
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if ((end - start) > delay)
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return -ETIMEDOUT;
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}
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}
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static void __secure ddr_sr_mode_ssr(u32 *saved_pwrctl)
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{
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setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
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RCC_DDRITFCR_DDRC1LPEN | RCC_DDRITFCR_DDRC1EN |
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RCC_DDRITFCR_DDRC2LPEN | RCC_DDRITFCR_DDRC2EN |
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RCC_DDRITFCR_DDRCAPBLPEN | RCC_DDRITFCR_DDRPHYCAPBLPEN |
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RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN |
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RCC_DDRITFCR_DDRPHYCEN);
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clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
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RCC_DDRITFCR_AXIDCGEN | RCC_DDRITFCR_DDRCKMOD_MASK);
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/* Disable HW LP interface of uMCTL2 */
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL,
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DDRCTRL_HWLPCTL_HW_LP_EN);
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/* Configure Automatic LP modes of uMCTL2 */
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clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG,
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DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK,
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DDRCTRL_PWRTMG_SELFREF_TO_X32_0);
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/* Save PWRCTL register to restart ASR after suspend (if applicable) */
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*saved_pwrctl = readl(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL);
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/*
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* Disable Clock disable with LP modes
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* (used in RUN mode for LPDDR2 with specific timing).
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*/
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
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DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
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/* Disable automatic Self-Refresh mode */
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
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DDRCTRL_PWRCTL_SELFREF_EN);
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}
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static void __secure ddr_sr_mode_restore(u32 saved_pwrctl)
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{
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saved_pwrctl &= DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
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DDRCTRL_PWRCTL_SELFREF_EN;
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/* Restore ASR mode in case it was enabled before suspend. */
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setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, saved_pwrctl);
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}
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static int __secure ddr_sw_self_refresh_in(void)
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{
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int ret;
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clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
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/* Blocks AXI ports from taking anymore transactions */
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0,
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DDRCTRL_PCTRL_N_PORT_EN);
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1,
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DDRCTRL_PCTRL_N_PORT_EN);
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/*
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* Waits unit all AXI ports are idle
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* Poll PSTAT.rd_port_busy_n = 0
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* Poll PSTAT.wr_port_busy_n = 0
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*/
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ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_PSTAT,
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DDRCTRL_PSTAT_RD_PORT_BUSY_0 |
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DDRCTRL_PSTAT_RD_PORT_BUSY_1 |
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DDRCTRL_PSTAT_WR_PORT_BUSY_0 |
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DDRCTRL_PSTAT_WR_PORT_BUSY_1, 0);
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if (ret)
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goto pstat_failed;
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/* SW Self-Refresh entry */
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setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
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/*
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* Wait operating mode change in self-refresh mode
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* with STAT.operating_mode[1:0]==11.
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* Ensure transition to self-refresh was due to software
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* by checking also that STAT.selfref_type[1:0]=2.
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*/
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ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT,
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DDRCTRL_STAT_OPERATING_MODE_MASK |
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DDRCTRL_STAT_SELFREF_TYPE_MASK,
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DDRCTRL_STAT_OPERATING_MODE_SR |
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DDRCTRL_STAT_SELFREF_TYPE_SR);
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if (ret)
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goto selfref_sw_failed;
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/* IOs powering down (PUBL registers) */
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR);
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clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
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DDRPHYC_ACIOCR_CKPDD_MASK,
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DDRPHYC_ACIOCR_CKPDD_0);
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clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
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DDRPHYC_ACIOCR_CKPDR_MASK,
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DDRPHYC_ACIOCR_CKPDR_0);
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clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
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DDRPHYC_ACIOCR_CSPDD_MASK,
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DDRPHYC_ACIOCR_CSPDD_0);
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/* Disable command/address output driver */
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clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR);
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clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR,
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DDRPHYC_DSGCR_ODTPDD_MASK,
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DDRPHYC_DSGCR_ODTPDD_0);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD);
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clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR,
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DDRPHYC_DSGCR_CKEPDD_MASK,
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DDRPHYC_DSGCR_CKEPDD_0);
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/* Disable PZQ cell (PUBL register) */
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD);
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/* Set latch */
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clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE);
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/* Additional delay to avoid early latch */
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secure_udelay(10);
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/* Activate sw retention in PWRCTRL */
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setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN);
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/* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
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setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
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/* Disable all DLLs: GLITCH window */
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLDIS);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
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setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
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/* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */
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clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
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/* Deactivate all DDR clocks */
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clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
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RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN |
|
||||
RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN);
|
||||
|
||||
return 0;
|
||||
|
||||
selfref_sw_failed:
|
||||
/* This bit should be cleared to restore DDR in its previous state */
|
||||
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
|
||||
DDRCTRL_PWRCTL_SELFREF_SW);
|
||||
|
||||
pstat_failed:
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0,
|
||||
DDRCTRL_PCTRL_N_PORT_EN);
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1,
|
||||
DDRCTRL_PCTRL_N_PORT_EN);
|
||||
|
||||
return -EINVAL;
|
||||
};
|
||||
|
||||
static void __secure ddr_sw_self_refresh_exit(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Enable all clocks */
|
||||
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
|
||||
RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN |
|
||||
RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN |
|
||||
RCC_DDRITFCR_DDRCAPBEN);
|
||||
|
||||
/* Handshake */
|
||||
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
||||
|
||||
/* Mask dfi_init_complete_en */
|
||||
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC,
|
||||
DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
|
||||
/* Ack */
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
||||
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT,
|
||||
DDRCTRL_SWSTAT_SW_DONE_ACK,
|
||||
DDRCTRL_SWSTAT_SW_DONE_ACK);
|
||||
if (ret)
|
||||
hang();
|
||||
|
||||
/* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
|
||||
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
|
||||
|
||||
/* Enable all DLLs: GLITCH window */
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR,
|
||||
DDRPHYC_ACDLLCR_DLLDIS);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
|
||||
/* Additional delay to avoid early DLL clock switch */
|
||||
secure_udelay(50);
|
||||
|
||||
/* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
|
||||
clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST);
|
||||
|
||||
secure_udelay(10);
|
||||
|
||||
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST);
|
||||
|
||||
/* PHY partial init: (DLL lock and ITM reset) */
|
||||
writel(DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK |
|
||||
DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT,
|
||||
STM32_DDRPHYC_BASE + DDRPHYC_PIR);
|
||||
|
||||
/* Need to wait at least 10 clock cycles before accessing PGSR */
|
||||
secure_udelay(1);
|
||||
|
||||
/* Pool end of init */
|
||||
ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR,
|
||||
DDRPHYC_PGSR_IDONE, DDRPHYC_PGSR_IDONE);
|
||||
if (ret)
|
||||
hang();
|
||||
|
||||
/* Handshake */
|
||||
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
||||
|
||||
/* Unmask dfi_init_complete_en to uMCTL2 */
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
|
||||
/* Ack */
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
||||
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT,
|
||||
DDRCTRL_SWSTAT_SW_DONE_ACK,
|
||||
DDRCTRL_SWSTAT_SW_DONE_ACK);
|
||||
if (ret)
|
||||
hang();
|
||||
|
||||
/* Deactivate sw retention in PWR */
|
||||
clrbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN);
|
||||
|
||||
/* Enable PZQ cell (PUBL register) */
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD);
|
||||
|
||||
/* Enable pad drivers */
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
|
||||
|
||||
/* Enable command/address output driver */
|
||||
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CKPDD_MASK);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CSPDD_MASK);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR);
|
||||
|
||||
/* Release latch */
|
||||
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_ODTPDD_MASK);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD);
|
||||
|
||||
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKEPDD_MASK);
|
||||
|
||||
/* Remove selfrefresh */
|
||||
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
|
||||
|
||||
/* Wait operating_mode == normal */
|
||||
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT,
|
||||
DDRCTRL_STAT_OPERATING_MODE_MASK,
|
||||
DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
||||
if (ret)
|
||||
hang();
|
||||
|
||||
/* AXI ports are no longer blocked from taking transactions */
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, DDRCTRL_PCTRL_N_PORT_EN);
|
||||
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, DDRCTRL_PCTRL_N_PORT_EN);
|
||||
|
||||
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
|
||||
}
|
||||
|
||||
void __secure psci_system_suspend(u32 __always_unused function_id,
|
||||
u32 ep, u32 context_id)
|
||||
{
|
||||
u32 saved_pwrctl, reg;
|
||||
|
||||
/* Disable IO compensation */
|
||||
|
||||
/* Place current APSRC/ANSRC into RAPSRC/RANSRC */
|
||||
reg = readl(STM32_SYSCFG_BASE + SYSCFG_CMPCR);
|
||||
reg >>= 8;
|
||||
reg &= 0xff << 16;
|
||||
reg |= SYSCFG_CMPCR_SW_CTRL;
|
||||
writel(reg, STM32_SYSCFG_BASE + SYSCFG_CMPCR);
|
||||
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENCLRR);
|
||||
|
||||
writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR);
|
||||
setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
|
||||
|
||||
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
|
||||
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
|
||||
|
||||
psci_v7_flush_dcache_all();
|
||||
ddr_sr_mode_ssr(&saved_pwrctl);
|
||||
ddr_sw_self_refresh_in();
|
||||
setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN);
|
||||
writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR);
|
||||
|
||||
/* Zzz, enter stop mode */
|
||||
asm volatile(
|
||||
"isb\n"
|
||||
"dsb\n"
|
||||
"wfi\n");
|
||||
|
||||
writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR);
|
||||
ddr_sw_self_refresh_exit();
|
||||
ddr_sr_mode_restore(saved_pwrctl);
|
||||
|
||||
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
|
||||
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user