Commit Graph

772 Commits

Author SHA1 Message Date
Olof Johansson
7f95b51d54 ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8
- name the GPIO lines
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Merge tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi into next/dt64

ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8

- name the GPIO lines

* tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hikey: name the GPIO lines

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-05 21:47:46 -07:00
Olof Johansson
1fa04d923c The Freescale arm64 device tree updates for 4.8:
- Update address-cells and reg properties of cpu nodes, considering
    MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
    and ls2080a
  - Adds the cache nodes and next-level-cache property for ls1043a and
    ls2080a to get cacheinfo work on these platforms
  - Add dma-coherent for ls1043a PCI nodes to utilize the hardware
    capability on data coherency
  - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
    detection in P3 PHY mode
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Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

The Freescale arm64 device tree updates for 4.8:
 - Update address-cells and reg properties of cpu nodes, considering
   MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
   and ls2080a
 - Adds the cache nodes and next-level-cache property for ls1043a and
   ls2080a to get cacheinfo work on these platforms
 - Add dma-coherent for ls1043a PCI nodes to utilize the hardware
   capability on data coherency
 - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
   detection in P3 PHY mode

* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls2080a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
  bindings: PCI: layerscape: Add 'dma-coherent' property
  arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: fsl: Update address-cells and reg properties of cpu nodes

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-05 21:10:09 -07:00
Florian Fainelli
b2aa1bb2be This pull request brings in the Raspberry Pi 3 DT for its arm64
support.  Note that it also merges in the ethernet DT changes so that
 the Pi3's ethernet can also get the MAC address.
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Merge tag 'bcm2835-dt-64-next-2016-07-03' into devicetree-arm64/next

This pull request brings in the Raspberry Pi 3 DT for its arm64
support.  Note that it also merges in the ethernet DT changes so that
the Pi3's ethernet can also get the MAC address.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-07-05 20:47:49 -07:00
Olof Johansson
87040f7c96 Qualcomm ARM64 Updates for v4.8
* Enable assorted peripherals on APQ8016 SBC
 * Update reserved memory on MSM8916
 * Add MSM8996 peripheral support
 * Add SCM firmware node on MSM8916
 * Add PMU node on MSM8916
 * Add PSCI cpuidle support on MSM8916
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Merge tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.8

* Enable assorted peripherals on APQ8016 SBC
* Update reserved memory on MSM8916
* Add MSM8996 peripheral support
* Add SCM firmware node on MSM8916
* Add PMU node on MSM8916
* Add PSCI cpuidle support on MSM8916

* tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (22 commits)
  arm64: dts: msm8996: add sdc2 support
  arm64: dts: msm8996: add sdc2 pinctrl
  arm64: dts: msm8996: add support to blsp2_spi5
  arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
  arm64: dts: msm8996: add support to blsp1_spi0
  arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c0
  arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c1
  arm64: dts: msm8996: add blsp2_i2c1 pinctrl
  arm64: dts: msm8996: add support to blsp1_i2c2 device
  arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
  arm64: dts: msm8996: add support blsp2_uart2
  arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
  arm64: dts: msm8996: add blsp2_uart1 pinctrl
  arm64: dts: msm8996: add msmgpio label
  ARM: dts: msm8916: Update reserved-memory
  arm64: dts: msm8916: Add SCM firmware node
  arm64: dts: qcom: Add msm8916 PMU node
  ARM64: dts: Add PSCI cpuidle support for MSM8916
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-04 22:24:30 -07:00
Olof Johansson
b6aec2b94d First part of X-Gene DTS changes queued for v4.8
The changes include:
 + 2 clean-up and style-fix patches from Bjorn
 + Correct timer interrupt polarity for X-Gene 2
 + Remove unused qmlclk node on X-Gene 1
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Merge tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64

First part of X-Gene DTS changes queued for v4.8

The changes include:
+ 2 clean-up and style-fix patches from Bjorn
+ Correct timer interrupt polarity for X-Gene 2
+ Remove unused qmlclk node on X-Gene 1

* tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
  arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
  arm64: dts: apm: Remove leading '0x' from unit addresses
  arm64: dts: apm: Use lowercase consistently for hex constants

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-04 21:33:31 -07:00
Gregory CLEMENT
5f4beef6db arm64: dts: marvell: add peripherals clocks for Armada 37xx
Add two new blocks of clocks. The peripheral clocks are the source clocks
of the peripheral of the Armada 3700 SoC.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-04 22:21:13 +02:00
Gregory CLEMENT
e3e1a55eda arm64: dts: marvell: add tbg clocks for Armada 37xx
Add a new block of clocks. The Time Base Generators clocks can be the
parent of the peripheral clocks.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-04 22:21:03 +02:00
Gregory CLEMENT
ddeba40b05 arm64: dts: marvell: Add xtal clock support for Armada 3700
The configuration of the clock depend of the gpio latch. This information
is stored in the gpio block registers. That's why the block is shared
using a syscon node.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-04 22:19:34 +02:00
Mars Cheng
aea1c315b6 arm64: dts: mediatek: add mt6755 support
This adds basic chip support for MT6755 SoC.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-07-03 07:57:21 +02:00
Thomas Petazzoni
c7f2735547 arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-06-30 13:50:30 +02:00
Thomas Petazzoni
7eec659478 arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
As suggested by Rob Herring, we should:

 1/ Use a SoC-specific compatible string in addition to the more generic
    one.

 2/ The generic compatible string has been changed from
    "marvell,mv-xor-v2" to "marvell,xor-v2".

We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-06-30 13:49:55 +02:00
David S. Miller
ee58b57100 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Several cases of overlapping changes, except the packet scheduler
conflicts which deal with the addition of the free list parameter
to qdisc_enqueue().

Signed-off-by: David S. Miller <davem@davemloft.net>
2016-06-30 05:03:36 -04:00
Xinliang Liu
339d00cb17 arm64: dts: hi6220: Add media subsystem reset dts
Add media subsystem reset dts support.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-29 23:39:08 +02:00
Linus Walleij
bbaf867e2d arm64: dts: hikey: name the GPIO lines
This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".

This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.

Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.

Cc: devicetree@vger.kernel.org
Cc: John Stultz <john.stultz@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-06-28 17:36:04 +01:00
Huang Tao
1e8567d53d arm64: dts: rockchip: Add rktimer device node for rk3399
Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC.

Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:17:09 +02:00
Douglas Anderson
5d26ad9cfb arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.

These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.

Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention".  On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288.  Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-27 01:07:40 +02:00
Srinivas Kandagatla
a670279898 arm64: dts: msm8996: add sdc2 support
This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
84ddf1ee1e arm64: dts: msm8996: add sdc2 pinctrl
This patch adds pinctrl required for sdhci for external sd card
controller.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
db6c8c8325 arm64: dts: msm8996: add support to blsp2_spi5
This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
7dba64a23e arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
This patch adds pinctrl required for blsp2_spi5 device.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
604677b415 arm64: dts: msm8996: add support to blsp1_spi0
This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
9f05d8ff8a arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
This patch adds pinctrl nodes required for blsp1_spi0.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
bf5443bcaa arm64: dts: msm8996: add support to blsp2_i2c0
This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
e25d57c106 arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
This patch adds support to blsp2_i2c0 pinctrl.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
d41d0cee9a arm64: dts: msm8996: add support to blsp2_i2c1
This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
0e7f196083 arm64: dts: msm8996: add blsp2_i2c1 pinctrl
This patch adds support to blsp2_i2c1 pinctrl nodes.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
21a4038461 arm64: dts: msm8996: add support to blsp1_i2c2 device
This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
5f9d54ffc1 arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
This patch adds pinctrl nodes required for blsp1_i2c2.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
fda48e6109 arm64: dts: msm8996: add support blsp2_uart2
This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
96f86b7d68 arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
This patch adds blsp2_uart2 pinctrl nodes.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
22e6789f94 arm64: dts: msm8996: add blsp2_uart1 pinctrl
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
84361086df arm64: dts: msm8996: add msmgpio label
This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Kevin Hilman
f3abd62961 ARM64: DTS: meson-gxbb: switch ethernet to real clock
With the clock driver upstream, switch to the real clock.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-23 15:59:31 -07:00
Michael Turquette
ba6a6c7fa6 arm64: dts: gxbb clock controller
Add the clock controller node for the AmLogic GXBB machine.

Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-23 15:23:04 -07:00
Douglas Anderson
ed388cdd2e arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY.  Hook things up in the main rk3399 dtsi file.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 18:24:33 +02:00
Douglas Anderson
64e3481c8a arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component.  Specify the syscon to enable that.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 18:24:05 +02:00
Javi Merino
f7b636a8d8 arm64: dts: juno: add thermal zones for scpi sensors
The juno dts have entries for the hwmon scpi, let's create thermal zones
for the temperature sensors described in the Juno ARM Development
Platform Implementation Details.

Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-06-21 15:17:31 +01:00
Sudeep Holla
bdeaa21aff arm64: dts: juno: add SCPI power domains for device power management
This patch adds power domain information to coresight devices using
SCPI power domains.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-06-21 15:17:16 +01:00
Sudeep Holla
3e287cf6ef arm64: dts: juno: add coresight support
Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.

Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.

The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).

The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
  memory space

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-06-21 15:10:56 +01:00
Li Yang
2983e625bf arm64: dts: ls2080a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-21 14:33:34 +08:00
Li Yang
ec049f3348 arm64: dts: ls1043a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-21 14:33:30 +08:00
Duc Dang
ddbc71d960 arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
Node qmlclk has no consumer, so remove it.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:41:49 -07:00
Duc Dang
f0a78909bd arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
Correct X-Gene 2 timer interrupt polarity as low-level triggered.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:26:35 -07:00
Bjorn Helgaas
0e999c79c0 arm64: dts: apm: Remove leading '0x' from unit addresses
Unit addresses should not have a leading '0x'.  Remove them.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:15:25 -07:00
Bjorn Helgaas
cafc4cd0c8 arm64: dts: apm: Use lowercase consistently for hex constants
The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.

Use lowercase consistently for the hex constants.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:13:54 -07:00
Olof Johansson
7a4fad480d This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
 
 - Dhanajay enables pinctrl for the Northstar2 SoCs
 
 - Jon Mason enables all of the UART peripherals found in the NS2 SVK and
   finally adds the CCI-400 and PMU nodes
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Merge tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:

- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs

- Dhanajay enables pinctrl for the Northstar2 SoCs

- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
  finally adds the CCI-400 and PMU nodes

* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: Add CCI-400 PMU support
  arm64: dts: NS2: Add all of the UARTs
  arm64: dts: Enable GPIO for Broadcom NS2 SoC
  arm64: dts: enable pinctrl for Broadcom NS2 SoC
  arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
  dt-bindings: ata: add compatible string for iProc AHCI controller

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-19 22:48:17 -07:00
Olof Johansson
4fb92c60eb Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
 - add reset driver
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Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
- add reset driver

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
  ARM64: dts: amlogic: gxbb: add ethernet
  ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
  ARM64: dts: amlogic: add pins for EMMC, SD
  ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
  documentation: Add compatibles for Amlogic Meson GXBB pin controllers
  ARM64: dts: amlogic: Add hiu and periphs buses

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-19 22:30:16 -07:00
Caesar Wang
ad1cfdf518 arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
The 2nd additional region is the GIC virtual cpu interface register
base and size.

As the gic400 of rk3368 says, the cpu interface register map as below

:

-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR

Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.

Fixes: b790c2cab5 ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: stable@vger.kernel.org

[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-18 14:54:23 +02:00
David Wu
69e5a8fe8c arm64: dts: rockchip: add i2c nodes for rk3399
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals.  Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.

Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates.  200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates.  If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
  their i2c bus was slow anyway.  Since we gate the functional clock
  when the i2c bus is not active, power savings would only be while i2c
  transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
  clock to make divisions work out perfectly, accounting for the rise /
  fall time measured on an actual board.

Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-18 14:00:23 +02:00
Liu Gang
f8ed1d9b0f arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.

Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16 08:43:10 +08:00
Neil Armstrong
4b7bed3852 ARM64: dts: meson-gxbb: Add Hardware Random Generator node
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-15 08:53:33 -07:00
Masahiro Yamada
ffd8a5ed57 arm64: dts: uniphier: add /memreserve/ for spin-table release address
As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:31 -07:00
Masahiro Yamada
1388ea2a8d arm64: dts: uniphier: change cpu-release-address
At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:29 -07:00
Masahiro Yamada
ed6cca5f9a arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
This node consists of various system-level configuration registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:15 -07:00
Olof Johansson
045ab0c54c Renesas ARM64 Based SoC DT Updates for v4.8
* Fix W=1 dtc warnings and other cleanups
 * Enable watchdog timer
 * Enable DMA for I2C
 * Increase the size of GIC-400 mapped registers: be nicer to hypervisors
 * Support RTS/CTS hardware flow control
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Merge tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC DT Updates for v4.8

* Fix W=1 dtc warnings and other cleanups
* Enable watchdog timer
* Enable DMA for I2C
* Increase the size of GIC-400 mapped registers: be nicer to hypervisors
* Support RTS/CTS hardware flow control

* tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: Drop 0x from unit address of gic
  arm64: dts: salvator-x: Fix W=1 dtc warnings
  arm64: dts: r8a7795: Fix W=1 dtc warnings
  arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
  arm64: dts: salvator-x: Enable watchdog timer
  arm64: dts: r8a7795: Add RWDT node
  arm64: dts: r8a7795: enable DMA for I2C
  arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
  arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-13 15:29:12 -07:00
Bjorn Andersson
7258e10e6a ARM: dts: msm8916: Update reserved-memory
Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12 00:48:11 -05:00
Andy Gross
ea49e164b5 arm64: dts: msm8916: Add SCM firmware node
This adds the devicetree node for the SCM firmware.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-12 00:48:11 -05:00
Stephen Boyd
5daa7a6031 arm64: dts: qcom: Add msm8916 PMU node
Add the PMU so we can get proper perf event support on this SoC.

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12 00:48:11 -05:00
Lina Iyer
a0df399fee ARM64: dts: Add PSCI cpuidle support for MSM8916
Add device bindings for CPUs to suspend using PSCI as the enable-method.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Tested-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12 00:48:11 -05:00
Srinivas Kandagatla
3f452fe71f arm64: dts: qcom: apq8016-sbc: enable bam dma node.
This patch enables bam dma node, dma is used for both tx and rx on spi
and on high speed serial.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12 00:46:49 -05:00
Georgi Djakov
a9f91b40e2 arm64: dts: apq8016-sbc: Add DT node for the uSD SDHC interface
Add the necessary properties to enable the SD-card on db410c boards.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12 00:46:49 -05:00
Rajesh Bhagat
bf26225fc6 arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-11 22:11:24 +08:00
Rajesh Bhagat
1cd78dd6bd arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-11 22:10:59 +08:00
Pramod Kumar
5f1a067bfa dt: mdio-mux: Add mdio multiplexer driver node
Add integrated MDIO multiplexer driver node which contains
two mux PCIe bus and one ethernet bus along with phys
lying on these bus.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-06-10 23:24:54 -07:00
Alison Wang
e6d66c50b9 arm64: dts: fsl: Update address-cells and reg properties of cpu nodes
MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-09 10:18:25 +08:00
Gerd Hoffmann
02d0860364 ARM: bcm2837: dt: Add the ethernet to the device trees
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-06-07 15:23:08 -07:00
Eric Anholt
9d56c22a78 ARM: bcm2835: Add devicetree for the Raspberry Pi 3.
While this devicetree also works for booting in 32-bit mode, it's
placed in arm64 since it's a 64-bit CPU (as suggested by Arnd).

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org> (v1)
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-07 15:21:55 -07:00
Horia Geantă
63dac35b58 arm64: dts: ls1043a: add crypto node
LS1043A has a SEC v5.4 security engine.
For now don't add rtic or sec_mon subnodes, since these features
haven't been tested yet.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-06-07 18:42:44 +08:00
Caesar Wang
95c27ba7bd arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.

The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.

The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls

* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.

* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.

* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.

* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-06 13:02:00 +02:00
Chanho Min
95b384f91a arm64: dts: Add dts files for LG Electronics's lg1313 SoC
Add dtsi file to support lg1313 SoC which based on Cortex-A53.
Also add dts file to support lg1312 reference board which based
on lg1313 SoC.

Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-03 12:21:54 -07:00
Masahiro Yamada
15b7cc78f0 arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2
Tree-wide replacement was done by commit 2ef7d5f342 (ARM, ARM64:
dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some
new users of "arm,amba-bus" at Linux 4.7-rc1.  Eliminate them now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-03 12:13:15 -07:00
CK Hu
81ad4dbaf7 arm64: dts: mt8173: Add display subsystem related nodes
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Cawa Cheng <cawa.cheng@mediatek.com>
Signed-off-by: Jie Qiu <jie.qiu@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-06-03 17:39:23 +02:00
Neil Armstrong
6d1a5c9381 ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
Update DTSI file to add the reset controller node.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01 10:57:35 -07:00
Kevin Hilman
8c5509f019 ARM64: dts: amlogic: gxbb: add ethernet
Add node for ethernet interface and pinctrl pins.
Enable on odroid-C2 and P20x boards.

Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01 10:57:29 -07:00
Kevin Hilman
8e6320dd4a ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins
for all EE domain UARTs.

Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01 10:57:19 -07:00
Kevin Hilman
a8025ed696 ARM64: dts: amlogic: add pins for EMMC, SD
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01 10:57:08 -07:00
Carlo Caione
f40d437f55 ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
Update DTS and DTSI files to enable the pin controller. We also now
support the blinking blue LED on the Odroid-C2.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01 10:56:43 -07:00
Carlo Caione
fab6b48cca ARM64: dts: amlogic: Add hiu and periphs buses
Add two new buses in the DTS: hiu and periphs buses.
In the Amlogic S905/GXBB SoC several devices (clock / eth / pin
controllers, etc...) are mapped under these two buses. Add them in the
DT before starting to add new devices.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01 10:56:14 -07:00
Jon Mason
5dcc9c7618 arm64: dts: NS2: Add CCI-400 PMU support
Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31 11:00:28 -07:00
Jon Mason
1e0fdee81e arm64: dts: NS2: Add all of the UARTs
Add all of the UARTs present on NS2 and enable them in the SVK device
tree file.  Also, do some magic to make sure that uart3 is discovered as
ttyS0 (as that is the console UART).

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31 11:00:27 -07:00
Yendapally Reddy Dhananjaya Reddy
5f2fb24141 arm64: dts: Enable GPIO for Broadcom NS2 SoC
This enables the GPIO support for Broadcom NS2 SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31 11:00:26 -07:00
Yendapally Reddy Dhananjaya Reddy
97b1504a30 arm64: dts: enable pinctrl for Broadcom NS2 SoC
This enables the pinctrl support for Broadcom NS2 SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31 11:00:25 -07:00
Anup Patel
ac9aae00f0 arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
We have one dual-port SATA3 AHCI controller present in
NS2 SoC.

This patch enables SATA3 AHCI controller and SATA3 PHY
for NS2 SoC in NS2 DT.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31 11:00:24 -07:00
Heiko Stuebner
6d0e3a45de arm64: dts: rockchip: add rk3399 io-domain core nodes
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Heiko Stuebner
39e5f7bb98 arm64: dts: rockchip: add rk3368-r88 iodomains
Add the supply-links according to the R88 schematics.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Heiko Stuebner
d1ab05aba9 arm64: dts: rockchip: add rk3368 io-domain core nodes
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Heiko Stuebner
4cca3d9448 arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
settings, there are also a lot of them containing some bigger function
blocks. To be able to define these as sub-devices, make them simple-mfds.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: David Wu <david.wu@rock-chips.com>
2016-05-30 09:43:30 +02:00
Brian Norris
13b2b3e23d arm64: dts: rockchip: enable eMMC for rk3399 EVB
Rockchip's rk3399 evaluation board has eMMC. Let's enable the
newly-added nodes.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Brian Norris
b4e87c097c arm64: dts: rockchip: add sdhci/emmc for rk3399
Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to
200 MHz, to support all supported timing modes.

Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably
have a compliant Arasan controller, but let's have a rockchip property
as the canonical backup/precautionary measure. Per Heiko's previous
suggestion, let's not clutter the arasan doc with it.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Brian Norris
1675926249 arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
Per the examples in
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the
grf node to be a simple-mfd in order to properly enumerate child devices
like our eMMC PHY.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

[directly mimic for the pmugrf, which will need the same change later
and there is no need to pollute commit history with another patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Xing Zheng
a09906cd8c arm64: dts: rockchip: assign default rates for core rk3399 clocks
These clocks are all core clocks used by many blocks/peripherals, many
of whose drivers don't set their clock rates at all. Let's assign
reasonable default clock rates for these core clocks, so that these
peripherals get something reasonable by default, and also so that if
child devices want to select a clock rate themselves, their muxes have
some reasonable parent clock rates to branch off of (rather than just
the boot-time defaults).

This helps the eMMC PHY, for one, to get a reasonable ACLK rate.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Simon Horman
21cc405c8a arm64: dts: r8a7795: Drop 0x from unit address of gic
Drop 0x from unit address of gic as this is the desired form for
a unit address.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-05-30 10:18:01 +09:00
Geert Uytterhoeven
4a4e2138d6 arm64: dts: salvator-x: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:51 +09:00
Geert Uytterhoeven
6f7bf82cc9 arm64: dts: r8a7795: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property

Move the cache-controller nodes under the cpus node, and make their unit
names and reg properties match the MPIDR values.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:50 +09:00
Geert Uytterhoeven
b186fbb6cc arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
Hook up the RWDT device node to the SYSC "always-on" PM Domain, for a
more consistent device-power-area description in DT.

Cfr. commit 38dbb45ee4 ("arm64: dts: r8a7795: Use SYSC "always-on" PM
Domain")

Fixes: f43838a7ae014cba ("arm64: dts: r8a7795: Add RWDT node")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:50 +09:00
Wolfram Sang
329260d5c4 arm64: dts: salvator-x: Enable watchdog timer
This patch enables watchdog timer for Salvator-X board.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:50 +09:00
Wolfram Sang
3114815f63 arm64: dts: r8a7795: Add RWDT node
This patch adds the RWDT device node for r8a7795.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:50 +09:00
Niklas Söderlund
d78a1cfa61 arm64: dts: r8a7795: enable DMA for I2C
Add DMA properties to the I2C nodes.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:50 +09:00
Pooya Keshavarzi
457f47b765 arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
There are some requirements about the GIC-400 memory layout and its
mapping if using 64k aligned base addresses like on r8a7795.

See e.g.

http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9

Map the whole memory range instead of only 0x2000. This will fix
the issue that some hypervisors, e.g. Xen, fail to handle the
interrupts correctly.

Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:49 +09:00
Geert Uytterhoeven
3cac478cce arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control
On the Salvator-X development board, the RTS and CTS pins of debug
serial-1 port SCIF1 are wired to the CP2102 Serial-USB bridge.  Reflect
this in the DTS by adding the "uart-has-rtscts" property to the scif1
device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-30 09:34:49 +09:00