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arm64: dts: ls2080a: Add cache nodes for cacheinfo support

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Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Li Yang 2016-06-16 18:35:04 -05:00 committed by Shawn Guo
parent ec049f3348
commit 2983e625bf
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
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@ -67,6 +67,7 @@
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
cpu@1 {
@ -74,6 +75,7 @@
compatible = "arm,cortex-a57";
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
cpu@100 {
@ -81,6 +83,7 @@
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
cpu@101 {
@ -88,6 +91,7 @@
compatible = "arm,cortex-a57";
reg = <0x101>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
cpu@200 {
@ -95,6 +99,7 @@
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
cpu@201 {
@ -102,6 +107,7 @@
compatible = "arm,cortex-a57";
reg = <0x201>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
cpu@300 {
@ -109,6 +115,7 @@
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
cpu@301 {
@ -116,6 +123,23 @@
compatible = "arm,cortex-a57";
reg = <0x301>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
};