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First part of X-Gene DTS changes queued for v4.8

Browse Source 
The changes include:
 + 2 clean-up and style-fix patches from Bjorn
 + Correct timer interrupt polarity for X-Gene 2
 + Remove unused qmlclk node on X-Gene 1
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Merge tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64

First part of X-Gene DTS changes queued for v4.8

The changes include:
+ 2 clean-up and style-fix patches from Bjorn
+ Correct timer interrupt polarity for X-Gene 2
+ Remove unused qmlclk node on X-Gene 1

* tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
  arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
  arm64: dts: apm: Remove leading '0x' from unit addresses
  arm64: dts: apm: Use lowercase consistently for hex constants

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-07-04 21:33:31 -07:00
commit b6aec2b94d
3 changed files with 53 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/net/apm-xgene-enet.txt
View File

@ -59,8 +59,8 @@ Example:
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
<0x0 0X17030000 0x0 0X400>,
<0x0 0X10000000 0x0 0X200>;
<0x0 0x17030000 0x0 0x400>,
<0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
port-id = <0>;

68
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View File

@ -106,88 +106,88 @@
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
<0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
<0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
<0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
v2m0: v2m@0x00000 {
<0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
<0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
<0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
v2m0: v2m@00000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x0 0x0 0x1000>;
};
v2m1: v2m@0x10000 {
v2m1: v2m@10000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x10000 0x0 0x1000>;
};
v2m2: v2m@0x20000 {
v2m2: v2m@20000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x20000 0x0 0x1000>;
};
v2m3: v2m@0x30000 {
v2m3: v2m@30000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x30000 0x0 0x1000>;
};
v2m4: v2m@0x40000 {
v2m4: v2m@40000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x40000 0x0 0x1000>;
};
v2m5: v2m@0x50000 {
v2m5: v2m@50000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x50000 0x0 0x1000>;
};
v2m6: v2m@0x60000 {
v2m6: v2m@60000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x60000 0x0 0x1000>;
};
v2m7: v2m@0x70000 {
v2m7: v2m@70000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x70000 0x0 0x1000>;
};
v2m8: v2m@0x80000 {
v2m8: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x80000 0x0 0x1000>;
};
v2m9: v2m@0x90000 {
v2m9: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x90000 0x0 0x1000>;
};
v2m10: v2m@0xA0000 {
v2m10: v2m@a0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xA0000 0x0 0x1000>;
reg = <0x0 0xa0000 0x0 0x1000>;
};
v2m11: v2m@0xB0000 {
v2m11: v2m@b0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xB0000 0x0 0x1000>;
reg = <0x0 0xb0000 0x0 0x1000>;
};
v2m12: v2m@0xC0000 {
v2m12: v2m@c0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xC0000 0x0 0x1000>;
reg = <0x0 0xc0000 0x0 0x1000>;
};
v2m13: v2m@0xD0000 {
v2m13: v2m@d0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xD0000 0x0 0x1000>;
reg = <0x0 0xd0000 0x0 0x1000>;
};
v2m14: v2m@0xE0000 {
v2m14: v2m@e0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xE0000 0x0 0x1000>;
reg = <0x0 0xe0000 0x0 0x1000>;
};
v2m15: v2m@0xF0000 {
v2m15: v2m@f0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xF0000 0x0 0x1000>;
reg = <0x0 0xf0000 0x0 0x1000>;
};
};
@ -198,10 +198,10 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
<1 13 0xff04>, /* Non-secure Phys IRQ */
<1 14 0xff04>, /* Virt IRQ */
<1 15 0xff04>; /* Hyp IRQ */
interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
<1 13 0xff08>, /* Non-secure Phys IRQ */
<1 14 0xff08>, /* Virt IRQ */
<1 15 0xff08>; /* Hyp IRQ */
clock-frequency = <50000000>;
};
@ -629,8 +629,8 @@
compatible = "apm,xgene2-sgenet";
status = "disabled";
reg = <0x0 0x1f610000 0x0 0x10000>,
<0x0 0x1f600000 0x0 0Xd100>,
<0x0 0x20000000 0x0 0X20000>;
<0x0 0x1f600000 0x0 0xd100>,
<0x0 0x20000000 0x0 0x20000>;
interrupts = <0 96 4>,
<0 97 4>;
dma-coherent;
@ -643,8 +643,8 @@
compatible = "apm,xgene2-xgenet";
status = "disabled";
reg = <0x0 0x1f620000 0x0 0x10000>,
<0x0 0x1f600000 0x0 0Xd100>,
<0x0 0x20000000 0x0 0X220000>;
<0x0 0x1f600000 0x0 0xd100>,
<0x0 0x20000000 0x0 0x220000>;
interrupts = <0 108 4>,
<0 109 4>,
<0 110 4>,
@ -684,7 +684,7 @@
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10640000 0x0 0x1000>;
interrupts = <0 0x3A 0x4>;
interrupts = <0 0x3a 0x4>;
clocks = <&i2c4clk 0>;
bus_num = <4>;
};

44
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -199,16 +199,6 @@
clock-output-names = "sdioclk";
};
qmlclk: qmlclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clock-names = "qmlclk";
reg = <0x0 0x1703C000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "qmlclk";
};
ethclk: ethclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
@ -226,7 +216,7 @@
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&ethclk 0>;
reg = <0x0 0x1702C000 0x0 0x1000>;
reg = <0x0 0x1702c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "menetclk";
};
@ -925,8 +915,8 @@
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
<0x0 0X17030000 0x0 0Xc300>,
<0x0 0X10000000 0x0 0X200>;
<0x0 0x17030000 0x0 0xc300>,
<0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
dma-coherent;
@ -951,11 +941,11 @@
compatible = "apm,xgene1-sgenet";
status = "disabled";
reg = <0x0 0x1f210000 0x0 0xd100>,
<0x0 0x1f200000 0x0 0Xc300>,
<0x0 0x1B000000 0x0 0X200>;
<0x0 0x1f200000 0x0 0xc300>,
<0x0 0x1b000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0xA0 0x4>,
<0x0 0xA1 0x4>;
interrupts = <0x0 0xa0 0x4>,
<0x0 0xa1 0x4>;
dma-coherent;
clocks = <&sge0clk 0>;
local-mac-address = [00 00 00 00 00 00];
@ -966,11 +956,11 @@
compatible = "apm,xgene1-sgenet";
status = "disabled";
reg = <0x0 0x1f210030 0x0 0xd100>,
<0x0 0x1f200000 0x0 0Xc300>,
<0x0 0x1B000000 0x0 0X8000>;
<0x0 0x1f200000 0x0 0xc300>,
<0x0 0x1b000000 0x0 0x8000>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0xAC 0x4>,
<0x0 0xAD 0x4>;
interrupts = <0x0 0xac 0x4>,
<0x0 0xad 0x4>;
port-id = <1>;
dma-coherent;
clocks = <&sge1clk 0>;
@ -982,8 +972,8 @@
compatible = "apm,xgene1-xgenet";
status = "disabled";
reg = <0x0 0x1f610000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0Xc300>,
<0x0 0x18000000 0x0 0X200>;
<0x0 0x1f600000 0x0 0xc300>,
<0x0 0x18000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x60 0x4>,
<0x0 0x61 0x4>,
@ -1005,11 +995,11 @@
compatible = "apm,xgene1-xgenet";
status = "disabled";
reg = <0x0 0x1f620000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0Xc300>,
<0x0 0x18000000 0x0 0X8000>;
<0x0 0x1f600000 0x0 0xc300>,
<0x0 0x18000000 0x0 0x8000>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x6C 0x4>,
<0x0 0x6D 0x4>;
interrupts = <0x0 0x6c 0x4>,
<0x0 0x6d 0x4>;
port-id = <1>;
dma-coherent;
clocks = <&xge1clk 0>;