- at91sam9rl and at91sam9261 fixes about PLL ranges
- at91sam9261 more comprehensive support for SSC
- sama5d3 Xplained: addition of pull-ups, PWM and PMIC (regulator)
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Merge tag 'at91-dt2' of git://github.com/at91linux/linux-at91 into next/dt
Merge "at91: DT for 3.16 #2" from Nicolas Ferre:
3.16: second DT series:
- at91sam9rl and at91sam9261 fixes about PLL ranges
- at91sam9261 more comprehensive support for SSC
- sama5d3 Xplained: addition of pull-ups, PWM and PMIC (regulator)
* tag 'at91-dt2' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: at91-sama5d3_xplained: add the regulator device node
ARM: at91: add 2 PWM outputs to SAMA5D3 Xplained
ARM: at91: add PWM pinctrl to SAMA5D3
ARM: at91: add pull-up to i2c[02] on SAMA5D3 Xplained
ARM: at91/dt: sam9rl: Fix PLL output range and mck divisors
ARM: at91/dt: sam9261: Add ssc2, SSC clocks and pcks
ARM: at91/dt: sam9261: Fix PLL output ranges and other clocks divisors
Signed-off-by: Olof Johansson <olof@lixom.net>
- Few of address cell warning fixes.
- Add Lamarr and Edision EVM NOR flash and NAND devices.
- Update dts to make use of dma-ranges and dma-coherent properties.
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Merge tag 'keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/dt
Merge "ARM: Keystone DTS updates for 3.16" from Santosh Shilimkar:
Keystone DTS updates for 3.16
- Few of address cell warning fixes.
- Add Lamarr and Edision EVM NOR flash and NAND devices.
- Update dts to make use of dma-ranges and dma-coherent properties.
* tag 'keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: dts: keystone-evm: add spi nor flash support
ARM: dts: k2l-evm: add AEMIF/NAND device entry
ARM: dts: k2e-evm: add AEMIF/NAND device entry
ARM: dts: keystone: Update USB node for dma properties
ARM: dts: keystone: Use dma-ranges property
ARM: dts: keystone: add cell's information to spi nodes
ARM: dts: keystone: move i2c0 device node from SoC to board files
ARM: dts: keystone: add cell's information to i2c nodes
ARM: dts: keystone: drop address and size cells from GIC node
Signed-off-by: Olof Johansson <olof@lixom.net>
as well as the dts portions of the pinctrl rework.
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Merge tag 'v3.16-rockchip-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "ARM: rockchip: devicetree changes for v3.16" from Heiko Stübner:
Addition of missing board compatible names and their vendor-prefixes
as well as the dts portions of the pinctrl rework.
* tag 'v3.16-rockchip-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: convert pinctrl nodes to new bindings
ARM: dts: rockchip: add root compatible properties
of: add mundoreader and radxa vendor prefixes
Signed-off-by: Olof Johansson <olof@lixom.net>
- orion5x
- convert to DT
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Merge tag 'mvebu-soc-orion5x-3.16' of git://git.infradead.org/linux-mvebu into next/soc
Merge "ARM: mvebu: SoC orion5x DT conversion for v3.16" from Jason Cooper:
mvebu SoC orion5x DT conversion for v3.16
- orion5x
- convert to DT
* tag 'mvebu-soc-orion5x-3.16' of git://git.infradead.org/linux-mvebu: (29 commits)
ARM: orion: remove no longer needed gpio DT code
ARM: orion: remove no longer needed DT IRQ code
ARM: orion5x: convert Maxtor Shared Storage II to the Device Tree
ARM: orion5x: convert d2net to Device Tree
ARM: orion5x: convert RD-88F5182 to Device Tree
ARM: orion5x: remove unneeded code for edmini_v2
ARM: orion5x: keep TODO list in edmini_v2 DT
ARM: orion5x: use DT to describe NOR on edmini_v2
ARM: orion5x: use DT to describe EHCI on edmini_v2
ARM: orion5x: use DT to describe I2C devices on edmini_v2
ARM: orion5x: convert edmini_v2 to DT pinctrl
ARM: orion5x: add standard pinctrl configs for sata0 and sata1
ARM: orion5x: add Device Bus description at SoC level
ARM: orion5x: update I2C description at SoC level
ARM: orion5x: enable pinctrl driver at SoC level
ARM: orion5x: switch to DT interrupts and timer
ARM: orion: switch to a per-platform handle_irq() function
ARM: orion5x: convert to use 'clocks' property for UART controllers
ARM: orion5x: switch to use the clock driver for DT platforms
ARM: orion5x: add interrupt for Ethernet in Device Tree
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Since commit 7adb0933b1 (ARM: dts: omap4: Set all audio related
IP's status to disabled as default) all audio related device are
disabled by default. Most boards were updated to enable devices
explicitly, but DuoVero was missed.
mcpdm is used for twl6040 and mcbsp1 is used for BlueTooth audio.
Cc: florian.vaussard@epfl.ch
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
MTD NAND partition for file-system should start at offset=0xA00000
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah <minalkshah@gmail.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add CPSW ethernet support for AM437x GP EVM which has one slave pinned out
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add cpsw phy sel device tree node for selecting phy mode in control module
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Both the VAR-STK-OM44 and VAR-DVK-OM44 boards comes with the
WLAN/BT version of the system on module VAR-SOM-OM44.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for VAR-SOM-OM44[1] SODIMM system on module from
Variscite. SoM features a OMAP4460, 1GB RAM, Gigabit Ethernet
(LAN7500) and optional WLAN/BT.
Also add support for VAR-STK-OM44 development board from
Variscite. This kit features a VAR-SOM-OM44 and the carrier board
VAR-OM44CustomBoard[2]. The VAR-STK-OM44 is the same as
VAR-DVK-OM44 but without the LCD display.
omap4-var-stk-om44.dts replace the old and very limited
omap4-var-som.dts.
[1] http://www.variscite.com/products/system-on-module-som/cortex-a9/var-som-om44-cpu-ti-omap-4-omap4460
[2] http://www.variscite.com/products/single-board-computers/var-om44customboard
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The OMAP4/5 TRMs primarily list address offsets from the padconf
physical address (which is not driver base address) and not
always the absolute physical address for padconf registers like
some other OMAP TRMs. So create a new macro to use this offset
and to avoid confusion between different OMAP parts.
For more information, see the tables in TRM for named something like
"Device Core Control Module Pad Configuration Register Fields"
and "Device Wake-Up Control Module Pad Configuration Register Fields"
Note that we now also have to update cm-t54 for the fixed up
offsets.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
[tony@atomide.com: updated comments, updated cm-t54]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable the SD Card reader and the internal eMMC on the Berlin BG2Q DMP
using two of the SDHCI nodes of the Berlin BG2Q.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add the SDHCI nodes for the Marvell Berlin BG2Q, using the mrvl,pxav3-mmc
driver.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add pinctrl bindings and system control nodes to what we currently know
about Berlin SoCs. Where available, also set default pinctrl property
for uarts, when there is only one pinmux option for it.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Berlin BG2Q SoC dtsi to make use of the new DT clock
nodes for Berlin SoCs.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Berlin BG2 SoC dtsi to make use of the new DT clock
nodes for Berlin SoCs. While at it, also fix up twdclk which is
running at cpuclk/3 instead of sysclk.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Berlin BG2CD SoC dtsi to make use of the new DT clock
nodes for Berlin SoCs. Also add a binding include to ease core clock
references.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Berlin BG2CD has 32 GPIOs in SoC power domain and 16 in the SM one.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Berlin BG2 has 32 GPIOs in SoC power domain and 16 in the SM one.
Only the first 8 SM GPIOs have interrupt support.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Berlin BG2Q has 6 GPIO ports compatible with the snps,dw-apb-gpio
driver. This patch adds the corresponding device tree nodes.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now. Also add corresponding binding documentation.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
LDO4 regulator was getting disabled preventing the system from
going into low power states. Keep it always on to fix it.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch fixed incorrect compatible for ak8975 magnetic sensor.
ak8975 magnetic sensor use compatible "ak8975" or "asahi-kasei,ak8975"
In this patch, use "asahi-kasei,ak8975" according to dt bindings document.
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add MFC memory banks to Exynos5420 based SMDK and Arndale-octa boards.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The audio setup on Peach-pit board is similar to Snow board, hence the
sound-card driver used on Snow board can be reused on Peach-pit board.
Peach-pit board uses MAX98090 audio codec.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The audio codec on Snow board, MAX98095 is connected on I2C7 bus.
Also it requires the GPX1-7 line to be pulled up.
Updated Snow DTS file to incorporate above changes and added a
sound node to instantiate the I2S-based sound card.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Removing the dt node for older usb3 phy driver from Exynos5250
device tree and updating the dt node for DWC3 controller to
use new phy driver based on generic phy framework.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add device tree node for new usbdrd-phy driver, which
is based on generic phy framework.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable hdmi for exynos5420 based peach-pit board.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Replace compatible string for HDMI node in Exynos5420. Since
latest restructring in Drm hdmi driver, it is agreed to use
a seperate compatible string for Exynos5420 HDMI IP siince it
uses APB mapped Phy.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable support for HDMI for exynos5250 based Snow board.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Allwinner sunxi support has been split into the various SoCs in Kconfig.
Adapt the new symbols for the device trees.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that the DTS file r7s72100-genmai.dts can be used with
board-genmai.c and board-genmai-reference.c, proceed with removing
r7s72100-genmai-reference.dts.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Let the multiplatform Genmai support boot with the unified DTS.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Copy the device nodes from Genmai reference into the Genmai device tree
file. This will allow us to use a single DTS file regardless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
will be used.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that r7s72100 has CCF support, remove the legacy Genmai reference
Kconfig bits for the non-multiplatform case.
Starting from this commit Genmai board support is always enabled via
CONFIG_MACH_GENMAI, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-genmai.c and board-genmai-reference.c
The file board-genmai-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- localize GPIO header in mach-at91 directory
- big update on the CCF front with main and slow clocks
- a cleanup of ADC and touchscreen driver with unification on IIO and
removal of old driver
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Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/soc
Merge "at91: cleanup for 3.16 #1" from Nicolas Ferre:
First cleanup series for 3.15
- localize GPIO header in mach-at91 directory
- big update on the CCF front with main and slow clocks
- a cleanup of ADC and touchscreen driver with unification on IIO and
removal of old driver
[olof: Most of this branch is new code, not cleanups, so I'm merging this into
the SoC branch in spite of the branch name]
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91: (28 commits)
ARM: at91/dt: at91-cosino_mega2560 remove useless tsadcc node
ARM: at91: remove atmel_tsadcc platform_data
Input: atmel_tsadcc: remove driver
ARM: at91: remove atmel_tsadcc from sama5_defconfig
ARM: at91: sam9rl: switch from atmel_tsadcc to at91_adc
ARM: at91: sam9g45: switch from atmel_tsadcc to at91_adc
ARM: at91: sam9rlek add touchscreen support through at91_adc
ARM: at91: sam9rl: add at91_adc to support adc and touchscreen
iio: adc: at91: add sam9rl support
iio: adc: at91: remove unused include from include/mach
ARM: at91: sam9m10g45ek: Add touchscreen support through at91_adc
iio: adc: at91_adc: Add support for touchscreens without TSMR
iio: adc: at91: cleanup platform_data
ARM: at91: sam9260: remove unused platform_data
ARM: at91: sam9g45: remove unused platform_data
ARM: at91/dt: define sam9rlek crystal frequencies
ARM: at91/dt: move at91sam9rl SoC to the new slow/main clock models
ARM: at91/dt: define main xtal frequency of the at91sam9261ek board
ARM: at91/dt: move at91sam9261 SoC to the new main clock model
ARM: at91/dt: add xtal frequencies to sama5d3 xplained board
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Mostly DTS additions to the SOCFPGA platform from Steffan Trumtrar, and a
couple of device tree documentation updates/typo fix.
This one does not the GPIO binding patch, as that is pending further
discussion. Also, v3 fixes a rebase artifact and compile tested.
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Merge tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next into next/dt
Merge "dts: socfpga: general updates for the socfpga platform" from Dinh
Nguyen:
Mostly DTS additions to the SOCFPGA platform from Steffan Trumtrar, and a
couple of device tree documentation updates/typo fix.
This one does not the GPIO binding patch, as that is pending further
discussion. Also, v3 fixes a rebase artifact and compile tested.
* tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next:
ARM: socfpga: dts: Add div-reg to the main_pll clocks
ARM: socfpga: dts: add reset-controller
Documentation: dt: reset: move socfpga-reset
Documentation: dt: socfpga: add reset-cells property
ARM: socfpga: dts: Add DTS entries for USB
ARM: socfpga: dts: Remove hard coded clock-frequency property
ARM: socfpga: dts: add eeprom and rtc on i2c0
ARM: socfpga: dts: convert to preprocessor includes
ARM: socfpga: dts: add rtc on i2c0 to socrates
ARM: socfpga: dts: add support for EBV SOCrates
ARM: socfpga: dts: add can0+1
ARM: socfpga: dts: add i2c busses
ARM: socfpga: dts: add remaining interrupts for pdma
ARM: socfpga: dts: fix pdma interrupt
Signed-off-by: Olof Johansson <olof@lixom.net>
The Armada XP Matrix board has an Ethernet PHY that isn't configurable
through the MDIO bus, so we use the newly introduced fixed-link PHY DT
binding to represent the PHY of this platform and get network working.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Besides our Kirkwood Reference design, there is another group of board
on which the eth interface is not connected to a phy but to a switch for
some board internal communication. For these designs, the memory also is
raised to 256MB.
The configuration of the switch is handled by an EEPROM or by the
bootloader, but on the kirkwood side, the port is always configured as
1000 Mbits, full duplex.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Link: https://lkml.kernel.org/r/1400230143-15620-4-git-send-email-valentin.longchamp@keymile.com
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This file allows to factor the common parts between the various Keymile
Kirkwood Designs.
kirkwood-km_common configures the peripherals that are currently
common to all our Kirkwood designs: PCIe, pinctrl, bitbang I2C, NAND
Flash controller.
The kirkwood-km_kirkwood file is then changed to include this common
file.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Link: https://lkml.kernel.org/r/1400230143-15620-3-git-send-email-valentin.longchamp@keymile.com
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The 98DX4122 dtsi file lacks the defintion of the PCIe controller which
is present on this SoC.
The SATA phys must also be explicitely disabled since they are not
present on this SoC. If they remain enabled, a hardlock occures when
their clock gates are enabled.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Link: https://lkml.kernel.org/r/1400230143-15620-2-git-send-email-valentin.longchamp@keymile.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
On imx35pdk there are two DRAM chip selects that are used:
CS0 at 0x80000000
CS1 at 0x90000000
Each bank is connected to 128MB of DRAM, giving a total of 256MB of system DRAM.
Fix the memory layout to describe the hardware appropriately.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add support for CAN based on a MCP2515 connected to ECSPI1.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
add element14s RIoTboard http://www.riotboard.org which is an i.MX6Solo
based design targeted at makers.
Signed-off-by: Iain Paton<ipaton0@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
We should use hardware ecc on i.MX. While at it, add the optional
nand-bus-width property.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The dts relied on the FEC pad ctrl settings from the bootloader by
using the NO_PAD_CTRL option. This breaks once the bootloader starts
initializing the pad ctrl settings from the same dts file. Change
to real pad ctrl settings taken from the platform based babbage
support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
USDHC4 is connected to a DDR MMC. Add support for it.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add the HDMI DT configuration for the SolidRun HummingBoard and Cubox-i.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This adds the stdout-path property to various i.MX boards. Values
of the property have been taken from barebox, so they should be
correct. Also, the older linux,stdout-path property is converted
to stdout-path.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The GW52xx supports LVDS on channel 0. Remove the obsolete crtcs node and
add display timings for the HanStar HSD100PXN1 display.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The GW54xx/GW53xx/GW52xx all support LVDS with a PWM controlled backlight.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This isn't compatible with the new binding and should be
handled via a proper regulator. It shouldn't be needed as
the driver has always ignored this property.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The new bindings drops one clock, renames the others and
drops the old interrupt mapping.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds a GPIO fixed regulator which used on RDK to
enable CSI bus.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch removes excess "#address-cells" and "#size-cells" entries
for PMIC, since these entries is not used.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
USB PWR and OC pins are used as GPIOs for different purposes,
so add "disable-over-current" property for OTG node to indicate this.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
"compatible", "#address-cells" and "#size-cells" for USB PHY are
already described in the SOM DTS. Remove these duplicate entries.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add support for the PCI express bus available on MX6 SabreSDP.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
It is not a good approach to have the USB PHY nodes inside imx27.dtsi since
the USB PHYs on mx27 are not internal to the SoC.
Place the USB PHY nodes in the board dts files instead.
Also, each board may have a different clock source for the USB PHY, so do not
hardcode it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
USB Host1, Host2 and OTG are gated via 'usb_ipg_gate' clock, so fix it in order
to avoid the following kernel oops:
usbcore: registered new interface driver usb-storage
10024000.usb supply vbus not found, using dummy regulator
Unhandled fault: external abort on non-linefetch (0x808) at 0xf4424184
Internal error: : 808 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 3.15.0-rc1-26325-g971f9fd-dirty #64
task: c7829aa0 ti: c7836000 task.ti: c7836000
PC is at ci_hdrc_probe+0x3a4/0x634
LR is at ci_hdrc_probe+0x100/0x634
pc : [<c036cc78>] lr : [<c036c9d4>] psr: 60000013
sp : c7837d48 ip : 00000001 fp : 00000000
r10: 00000000 r9 : 00000000 r8 : c791b6c0
r7 : c7945000 r6 : f4424000 r5 : c7945010 r4 : c794e010
r3 : f4424184 r2 : 00000000 r1 : 8c000004 r0 : 0c000004
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 0005317f Table: a0004000 DAC: 00000017
Process swapper (pid: 1, stack limit = 0xc78361c0)
Stack: (0xc7837d48 to 0xc7838000)
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The hardware is better described if we place the PMIC IRQ GPIO into its own
pingroup.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx27-pdk has a MC13783 PMIC connected to CSPI2 port.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds devicetree node and pinctrl group for I2C1.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch sorts nodes by name and moves "iomux" configuration at
the bottom of file.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds a regulator node and pinctrl group for USB OTG.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Move "hog" pins into corresponded pin groups for eSDHC1, eSDHC2,
eCSPI1, gpio-keys, regulator-fixed and codec clock.
Additionally, this patch fixes GPIO active level definition for
USB regulator.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch allow to define partitions onto NFC in user defined
devicetrees.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch enables UART1 on the phyFLEX connector (i.MX6 uart3).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The pins labeled UART1 on the module connector are wired to i.MX6 uart3.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds the TLV320, STMPE811, RTC8564, and MX1037 ICs to the I2C2 bus.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Note that the fec driver code currently hard-codes an active-low
reset, regardless of the flags in the device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch enables the red and green GPIO LEDs on Phytec phyFLEX i.MX6 modules.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The PBA-B-01 carrier board can be equipped with either Quad or DualLite/Solo
phyFLEX i.MX6 modules (PFL-A-02).
This moves all common devices into imx6qdl-phytec-pbab01.dtsi. The SoC specific
device trees then just include the pfla01 and pbab01 dtsi files corresponding
to the SoC variant.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Provide an entry for the UART1 pin muxing.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds support for Digi ConnectCore® i.MX51/Wi-i.MX51 SOM
and basic support for the ConnectCore for i.MX51 JumpStart Kit.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch converts all i.MX WEIM users to use single naming style
for devices.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add initial Toradex Colibri VF61 board support. Ethernet, UART
and SDHC cards are working. Cache latencies need to be a bit
higher than vf610.dtsi suggests. Those values are validated
by running multiple memory tests.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx27-pdk has 128 MB of DRAM. Pass the memory range in dt.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds display control signal definitions.
These fields are not used in the driver yet, but will be used for
reference to indicate the polarity of the signals.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Use GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW instead of 0 and 1.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fix a copy & paste error: on duckbills the GPIO used for resetting
the ethernet phy differs from FSL's MX28EVK board.
Reported-by: Stefan Wahren <info@lategoodbye.de>
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
I2SE's duckbills are only equipped with a micro SD card slot and
thus only provide a 4-bit interface.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tested by pinging from the host PC to the imx51-babbage via a g_ether
connection.
Signed-off by: Dave Ebright <dave.ebright@parsons.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This adds devicetree node for VF610, and there are 8 channels
supported.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This IP module is always present and has no external connections.
There is no reason to disable it in the device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
mx25pdk has a sgtl5000 codec connected to the I2C1 port.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The current .dts for ste-ccu8540 lacks a 'device_type = "memory"' for
its memory node, relying on an old ppc quirk in order to discover its
memory. Fix the data so that all parsing code can handle it correctly.
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Set 'ti,set-rate-parent' property for the dpll4_m5x2_mul_ck clock, which
is used for the ISP functional clock. This fixes the OMAP3 ISP driver's
clock rate configuration, which needs the rate to be propagated properly
to the divider node (dpll4_m5_ck).
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
We need to use set-rate-parent for dpll4_m5 clock path, so use the
ti,fixed-factor-clock version which supports set-rate-parent property.
The set-rate-parent flag itself is set in the following patch, this one
just changes the clock driver to ti,fixed-factor-clock without any other
changes.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Use the ti,fixed-factor-clock version so that autoidle for
dpll_per_clkdcoldo is properly controlled after power management code
is introduced. Without this the clock may be held active even when
it is gated.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
To silence the warning
cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Marvell Armada 375 SoCs contains two EHCI controllers. This commit
adds the Device Tree description of these interfaces at the SoC level,
and also enables the USB2 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-18-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 375 SoCs contain a xHCI controller. This commit
adds the Device Tree description of this interfaces at the SoC level,
and also enables the USB3 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-17-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 38x SoCs contains one EHCI controller. This commit
adds the Device Tree description of this interface at the SoC level,
and also enables the USB2 port on the Armada 385 DB platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-16-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 38x SoCs contains two xHCI controllers. This commit
adds the Device Tree description of those interfaces at the SoC level,
and also enables the two USB3 ports on the Armada 385 DB platform and
one USB3 port on the Armada 385 RD platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-15-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Create DTS files to describe the Marvell OpenRD boards.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1399836639-1918-1-git-send-email-andrew@lunn.ch
Tested-by: Francois Lorrain <francois.lorrain@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Added TPS65090 regulator related nodes to Snow board.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add device-tree bindings for the ARM CCI-400 on Exynos5420. There
are two slave interfaces: one for the A15 cluster and one for the
A7 cluster.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds the device tree to support Toradex Colibri T30, a
computer on module which can be used on different carrier boards.
The module consists of a Tegra 30 SoC, two PMIC, DDR3L RAM, eMMC,
a LM95245 temperature sensor and an AX88772B USB Ethernet
Controller. Furthermore, there is a STMPE811 and SGTL5000 audio
codec which are not yet supported. Anything that is not self
contained on the module is disabled by default.
The device tree for the Evaluation Board includes the modules
device tree and enables the supported pheripherials of the carrier
board (the Evaluation Board supports almost all of them).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch - finally, after over 6 months! :-( - addresses
Samuel's request to split the vexpress-sysreg driver into
smaller portions and define the device in a form of MFD
cells:
* LEDs code has been completely removed and replaced with
"gpio-leds" nodes in the tree (referencing dedicated
GPIO subnodes in sysreg - bindings documentation updated);
this also better fits the reality as some variants of the
motherboard don't have all the LEDs populated
* syscfg bridge code has been extracted into a separate
driver (placed in drivers/misc for no better place)
* all the ID & MISC registers are defined as sysconf
making them available for other drivers should they need
to use them (and also to the user via /sys/kernel/debug/regmap
which can be helpful in platform debugging)
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
The A31 SoC has a different pin controller for PL and PM banks.
Define this new controller in the device tree.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Make sure ethernet and mdio nodes are disabled by default and enable
them explicitly only on boards that actually use them.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add device tree nodes and pinmux for hdq/1wire on
am43x epos evm.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add USB pinmux information and USB modes
for the USB controllers.
CC: Benoît Cousson <bcousson@baylibre.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
CC: Benoît Cousson <bcousson@baylibre.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL
Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.
CC: Benoît Cousson <bcousson@baylibre.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The USB2 PHY driver expects named clocks for wakeup clock
and reference clock. Provide this information for USB2 PHY
nodes in OMAP4 and OMAP5 SoC DTS.
CC: Benoît Cousson <bcousson@baylibre.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.
[Roger Q] Clean up. Updated IRQ for interrupt crossbar.
CC: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for sata.
[Roger Q] Clean up.
CC: Benoit Cousson <bcousson@baylibre.com>
CC: Tony Lindgren <tony@atomide.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
G2D power domain also controls the CMU block of G2D. Since
clock registers can be accessed anytime for viewing
clk_summary, it can cause a system crash if g2d power domain
is disabled.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
MAU powerdomain provides clocks for Audio sub-system block.
This block comprises of the I2S audio controller, audio DMA
blocks and Audio sub-system clock registers.
Right now, there is no way to hook up power-domains with
clock providers. During late boot when this power-domain
gets disabled, we get following external abort.
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This change places MDMA1 in disabled node for Exynos5420.
If MDMA1 region is configured with secure mode, it makes
the boot failure with the following on smdk5420 board.
("Unhandled fault: imprecise external abort (0x1406) at 0x00000000")
Thus, arndale-octa board don't need to do the same thing anymore.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Tested-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic DT SRAM bindings are
used for achieving this.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch includes,
1] renaming of the HSI2C clocks
2] renaming of spi clocks according to the datasheet
3] fixes for child-parent relationships
4] adding of more clocks related to PERIC block
5] use GATE_IP_* offsets instead of GATE_BUS_*
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
We keep the UART naming backwards compatible with the legacy version.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Only essential clocks are added for now. Other clocks will be added when
needed.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
SCIF0 and SCIF1 are used as debug serial ports. Enable them and
configure pinmuxing appropriately. We can now remove the clkdev
registration hack for SCIF devices from the Koelsch reference board
file.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: added aliases to avoid device renumbering]
[horms+renesas@verge.net.au: resolved conflicts]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
SCIF0 and SCIF1 are used as debug serial ports. Enable them and
configure pinmuxing appropriately. We can now remove the clkdev
registration hack for SCIF devices from the Lager reference board file.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: updated changelog to remove references to
device renaming]
[horms+renesas@verge.net.au: resolved conflicts]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In the comments, LCD pins 16-23 were numbered in the wrong order.
Fix this and use proper pinmux constants for all entries while we
are at it.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Cc: Benoit Parrot <bparrot@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
[tony@atomide.com: updated description]
Signed-off-by: Tony Lindgren <tony@atomide.com>
The external trigger value is 0b1101 which is 13 but 0xd.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This change makes the DTS consistent with the platform data
that exists in board-marzen.c.
Empirically it does not appear to be necessary.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Seems like we've had more fixes than usual this release cycle, but
there's nothing in particular that we're doing differently. Perhaps it's
just one of those cycles where more people are finding more regressions
(and/or that the latency of when people actually test what's been in
the tree for a while is catching up so that we get the bug reports now).
The bigger changes here are are for TI and Marvell platforms:
* Timing changes for GPMC (generic localbus) on OMAP causing some largeish
DTS deltas.
* Fixes to window allocation on PCI for mvebu touching drivers/ stuff. Patches
have acks from subsystem maintainers where needed.
* A fix from Thomas for a botched DT conversion in drivers/edma.
There's a handful of other fixes for the above platforms as well as sunxi,
at91, i.MX. I also included a MAINTAINER update for Broadcom, and a trivial
move of a binding doc.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Seems like we've had more fixes than usual this release cycle, but
there's nothing in particular that we're doing differently. Perhaps
it's just one of those cycles where more people are finding more
regressions (and/or that the latency of when people actually test
what's been in the tree for a while is catching up so that we get the
bug reports now).
The bigger changes here are are for TI and Marvell platforms:
* Timing changes for GPMC (generic localbus) on OMAP causing some
largeish DTS deltas.
* Fixes to window allocation on PCI for mvebu touching drivers/
stuff. Patches have acks from subsystem maintainers where needed.
* A fix from Thomas for a botched DT conversion in drivers/edma.
There's a handful of other fixes for the above platforms as well as
sunxi, at91, i.MX. I also included a MAINTAINER update for Broadcom,
and a trivial move of a binding doc.
I know you said you'd be offline this week, but I might as well post
it for when you return. :)"
I'm not quite offline yet. Doing a few pulls in the last hour before my
internet goes away..
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits)
MAINTAINERS: update Broadcom ARM tree location and add an SoC family
ARM: dts: i.MX53: Fix ipu register space size
ARM: dts: kirkwood: fix mislocated pcie-controller nodes
ARM: sunxi: Enable GMAC in sunxi_defconfig
ARM: common: edma: Fix xbar mapping
ARM: sun7i: Fix i2c4 base address
ARM: Kirkwood: T5325: Fix double probe of Codec
ARM: mvebu: enable the SATA interface on Armada 375 DB
ARM: mvebu: specify I2C bus frequency on Armada 370 DB
ARM: mvebu: use qsgmii phy-mode for Armada XP GP interfaces
ARM: mvebu: fix NOR bus-width in Armada XP OpenBlocks AX3 Device Tree
ARM: mvebu: fix NOR bus-width in Armada XP DB Device Tree
ARM: mvebu: fix NOR bus-width in Armada XP GP Device Tree
ARM: dts: AM3517: Disable absent IPs inherited from OMAP3
ARM: dts: OMAP2: Fix interrupts for OMAP2420 mailbox
ARM: dts: OMAP5: Add mailbox dt node to fix boot warning
ARM: OMAP5: Switch to THUMB mode if needed on secondary CPU
ARM: dts: am437x-gp-evm: Do not reset gpio5
ARM: dts: omap3-igep0020: use SMSC9221 timings
PCI: mvebu: split PCIe BARs into multiple MBus windows when needed
...
There's no need to duplicate the interrupt-parent property in all DT
nodes as the kernel automatically walks parent nodes to find the
property. Specify it once in the root node only.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Conflicts:
drivers/net/ethernet/altera/altera_sgdma.c
net/netlink/af_netlink.c
net/sched/cls_api.c
net/sched/sch_api.c
The netlink conflict dealt with moving to netlink_capable() and
netlink_ns_capable() in the 'net' tree vs. supporting 'tc' operations
in non-init namespaces. These were simple transformations from
netlink_capable to netlink_ns_capable.
The Altera driver conflict was simply code removal overlapping some
void pointer cast cleanups in net-next.
Signed-off-by: David S. Miller <davem@davemloft.net>
NVIDIA SHIELD is a portable Android console containing a Tegra 4 SoC with
2GB RAM and a 720p panel.
The following hardware is enabled by this device tree: UART, eMMC, USB
(needs external power), PMIC, backlight, joystick, SD card, GPIO keys.
DSI panel, HDMI output, charger, self-powered USB, audio, wifi bluetooth
are not supported yet but might be by future patches (likely in that
order).
Touch panel and sensors will probably never be supported.
Initrd addresses are hardcoded to match the static values used by the
bootloader, since it won't add them for us. All the same, a kernel
command-line is provided to replace the one passed by the
bootloader which is filled with garbage.
NVIDIA SHIELD is typically booted with an appended DTB to avoid
modifications made by the bootloader.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
[swarren, fixed gpio-keys child node sort order, patch description]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The R7 tv-dongle is an A10s based hdmi tv dongle, with 1G RAM, 4G nand flash,
and rtl8189es sdio wifi. It has a standard male hdmi connector, an USB host
port using an USB-A receptacle and a micro-usb receptacle for both power
and USB OTG.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
As there are no pull-up resistors on the board itself it can be useful to
use the SoC pad pull-up to be able to easily connect usual i2c devices.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Argument 3 (OUT) and 4 (ICPLL) of the atmel,pll-clk-output-ranges were missing.
Also, the at91sam9rl doesn't really have a by 3 divisor.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add ssc2 support, ssc2 pinctrl and clocks for the three SSCs.
Also add support for the programmable clocks.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Argument 3 (OUT) and 4 (ICPLL) of the atmel,pll-clk-output-ranges were missing.
Also, the at91sam9261 doesn't really have a by 3 divisor.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nobody want to know the connection between io clk and timer clk,
so exposing this information to timer module is not reasonable.
this patch moves to define the timers' clk in dt.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Add a node in DT for the proper regulator which means we can move away
from the mmci platform data which currently holds the corresponding OCR
mask.
The mmci driver can then calculate the OCR mask based on the voltages
supported by the regulator, instead of relying on the platform data.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The mmci host driver supports the common mmc DT parser, which enables
us to use the use common names instead.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The mmci host driver supports the common mmc DT parser, which enables
us to use the use common names instead.
Cc: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The mmci host driver supports the common mmc DT parser, which enables
us to use the use common names instead.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add 800 MHz to the r8a7740 DTS to describe the maximum CPU frequency.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Tested-by: Geert Uytterhoeven <geert@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
make it work. The patch has been tagged for stable.
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Merge tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into fixes
Pull "DaVinci fixes for v3.15" from Sekhar Nori:
The patch fixes EDMA crossbar mapping to actually
make it work. The patch has been tagged for stable.
* tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: common: edma: Fix xbar mapping
Signed-off-by: Olof Johansson <olof@lixom.net>
Some minor things, the major thing being the enabling of the GMAC driver in
sunxi_defconfig that will un-break Olof's autobooters.
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Merge tag 'sunxi-fixes-for-3.15' of https://github.com/mripard/linux into fixes
Merge 'Allwinner fixes for 3.15' from Maxime Ripard:
Set of fixes for the Allwinner support for 3.15
Some minor things, the major thing being the enabling of the GMAC driver in
sunxi_defconfig that will un-break Olof's autobooters.
* tag 'sunxi-fixes-for-3.15' of https://github.com/mripard/linux:
ARM: sunxi: Enable GMAC in sunxi_defconfig
ARM: sun7i: Fix i2c4 base address
ARM: sun7i: fix PLL4 clock and add PLL8
Signed-off-by: Olof Johansson <olof@lixom.net>
Define the Henninger board dependent part of the MSIOF0 device node.
Add device node for Renesas R2A11302FT PMIC for which no bindings exist yet.
Based on the Koelsch MSIOF device tree patch by Geert Uytterhoeven.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Henninger board dependent part of the QSPI device node.
Add device nodes for Spansion S25FL512S SPI flash and MTD partitions on it.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Henninger board dependent part of the SDHI0/2 device nodes along with
the necessary voltage regulators (note that the Vcc regulators are dummy -- they
are required but don't actually exist on the board). Also, GPIOs have to be used
for the CD and WP signals due to the SDHI driver constraints...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Introduce the grf syscon and convert the pinctrl drivers for rk3066 and rk3188
to use it, instead of mapping the grf registers themselfs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add the missing 'compatible' property to device tree root node of
- rk3066a-bqcurie2.dts
- rk3188-radxarock.dts
and document the new values.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Adds the google peach-pit board dts file which uses
exynos5420 SoC.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adding labels to nodes which do not have it yet in exynos5420.
This is done so as to use reference based node updation in board
files.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adds the PWM nodes to 5420 pinctrl dtsi file.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables the rear facing camera (s5c73m3) on TRATS2 board
by adding the I2C0 bus controller, s5c73m3 sensor, MIPI CSI-2 receiver
and the sensor's voltage regulator supply nodes.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Remove unused /camera/clock-controller node and add required clock
properties to the camera node. This is required for a clock provider
that will be referenced by image sensor devices.
Also add required clock related changes to s5k6a3 device node and
afvdd regulator supply.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The i2c_ak8975 controller uses label i2c8.
This alias is already used for I2C controller 8 defined
in file arch/arm/boot/dts/exynos4.dtsi.
This patch renames a label for i2c_ak8975 to i2c9.
Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds missing pinctrls for I2C controllers 2-7.
Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Keystone supports dma-coherent on USB master and also needs
dma-ranges to specify the hardware alias memory range in which DMA
can be operational.
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The dma-ranges property has to be specified per bus and has format:
< DMA addr > - Base DMA address for Bus (Bus format 32-bits)
< CPU addr > - Corresponding base CPU address (CPU format 64-bits)
< DMA range size > - Size of supported DMA range
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
SPI nodes should always have #address-cells and #size-cells defined,
otherwise warnings will be produced in case of adding any child
nodes to the SPI bus in DT:
Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/spi@21000400/n25q128a11@0
Warning (avoid_default_addr_size): Relying on default #size-cells value for /soc/spi@21000400/n25q128a11@0
Hence, ensure that all SPIx nodes have #address-cells and #size-cells
properties defined.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
I2C devices are not the part of Keystone SoC and have to be
defined in board DTS files.
Hence, move i2c0 EEPROM device node from Keystone SoC to
k2hk, k2e, k2l EVM files as they all have similar EEPROM SoCs
installed.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
I2C nodes should always have #address-cells and #size-cells defined,
otherwise warnings will be produced in case of adding child
nodes to the I2C bus in DT:
Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/i2c@2530800/pca@20
Warning (avoid_default_addr_size): Relying on default #size-cells value for /soc/i2c@2530800/pca@20
Hence, ensure that all i2cX nodes have #address-cells and #size-cells
properties defined.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This is likely a copy-and-paste error from the
ARM GIC documentation, that has already been fixed.
address-cells should have been set to 0, as with the size
cells. As having those properties set to 0 is the
same thing as not specifying them, drop them completely.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
this patch fills the resets properity for dspif, gps and dsp nodes.
these nodes belong to GPS related modules.
Signed-off-by: Tao Huang <Tao.Huang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
add cortex-a9-pmu node to make the performance monitor unit work on atlas6.
Signed-off-by: Ye He <Ye.He@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
in drivers/spi/spi-sirf.c, we have moved to use generic dma dt-binding.
here the dts should be changed too.
Cc: Mark Brown <broonie@linaro.org>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
The tsadcc node is useless as it doesn't refer to anything and the touchscreen
is handled by the adc0 node.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rodolfo Giometti <giometti@linux.it>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Move at91sam9rl SoC to the new main/slow clock model.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define crystal properties of sama5d3 xplained board.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define crystal frequencies of sama5d3xcm boards.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Replace the old main and clk definitions (fixed rate clk) by the new main and
slow clk subtree definition (ck = mux(rc_osc, osc)).
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
add pin groups for USP0 only holding one of TX and RX frame sync. this patch
matches with the change in drivers/pinctrl/sirf.
commit 73f68c01f4 did this for prima2, but missed prima2. this patch fixes
the problem.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
On N900 there are nice LEDs that show the state of the
sys_clkreq and sys_off_mode pins.
These LEDs go low when the system enters deeper idle
states. The left LED shows the state of the sys_clkreq
pin, and goes off during retention idle. The right LED
shows the state of sys_off_mode pin and both go off
during off idle.
As N900 is a battery operated device, these LEDs should
be off most of the time. So let's enable them by default
so we can make sure the system is mostly idle.
This allows the maintainers to also immediately test
patches for PM regressions by looking at the LEDs,
which certainly makes my life easier.
The LED can naturally be disabled during runtime with:
# echo none > /sys/class/leds/debug::sleep/trigger
Note that we don't currently have support for omap3
errata 1.158 that remuxes GPIO pins to INPUT_PULLUP |
MUX_MODE7 for the duration of idle. This means that the
GPIO pins set high will go down during off idle. In this
case it does not matter as the sys_off_mode goes down
too, but there's still a slim chance of false off idle
LED signals. If in doubt, false LED signals can be
verified by the sys_off_mode or vdd_core values.
Also note that to allow the UARTs to autoidle, the
following needs to be run on N900 to enable off idle:
#!/bin/sh
uarts=$(find /sys/class/tty/ttyO*/device/power/ -type d)
for uart in $uarts; do
echo 3000 > $uart/autosuspend_delay_ms
done
uarts=$(find /sys/class/tty/ttyO*/power/ -type d)
for uart in $uarts; do
echo enabled > $uart/wakeup
echo auto > $uart/control
done
echo 1 > /sys/kernel/debug/pm_debug/enable_off_mode
For retention idle, change the above to set 0 to
enable_off_mode.
Also note that without the twl4030 PM scripts the actual
voltage scaling won't happen for off idle so we only get
voltage scaling over I2C4 for retention idle. I'll do
some device tree patches for those also a bit later on.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
[tony@atomide.com: also make sure the LEDs get built to see PM regressions]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Almost certainly any sane board has the twl4030 has the I2C4
pins connected as those are needed for voltage control during
idle. If the I2C4 lines are not properly muxed, any voltage
scaling over I2C4 will fail.
Let's mux those pins by default, the boards that are not using
them can still configure things separately.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee1786 (pinctrl: single: Add support for wake-up interrupts)
that recently got merged. In addition to that we also needed commit
79d9701559 (of/irq: create interrupts-extended property) and
9ec36cafe4 (of/irq: do irq resolution in platform_get_irq) that
are now also merged.
So let's fix the wake-up events for some selected omaps so devices
booted in device tree mode won't just hang if deeper power states
are enabled, and so systems can wake up from suspend to the serial
port event.
Note that there's no longer need to specify the wake-up bit in
the pinctrl settings, the request_irq on the wake-up pin takes
care of that.
Cc: devicetree@vger.kernel.org
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
[tony@atomide.com: updated comments, added board LDP]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use MATRIX_KEY macro from dt-bindings/input/input.h
to make the keyboard matrix human readable.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The VTT regulator for DDR3 termination on the am335x-evmsk is
controlled by a gpio. It is configured by the bootloader so here we
define an always-on, fixed voltage regulator to hold the gpio.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The VTT regulator for DDR3 termination on the am437x-gp-evm is
controlled by a gpio. It is configured by the bootloader so here we
define an always-on, fixed voltage regulator to hold the gpio.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add touchscreen support for AM437x GP EVM using pixcir
touchscreen controller.
CC: Benoit Cousson <bcousson@baylibre.com>
CC: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fixup Y resolution and add default pin state. Also update
the compatible id.
CC: Benoit Cousson <bcousson@baylibre.com>
CC: Tony Lindgren <tony@atomide.com>
CC: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA722 is part of DRA72x family which are single core cortex A15 devices
with most infrastructure IPs otherwise same as whats on the DRA74x family.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: linux-doc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
[tony@atomide.com: updated for Makefile sorting]
Signed-off-by: Tony Lindgren <tony@atomide.com>
"ti,dra752" is neither documented nor correct, since the device is actually a
dra742 device as rightly documented in dt bindings.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support of AW-NH387 (mwifiex) WiFi/BT chip connected to MMC3.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for CM-T54 CoM and SBC-T54 board:
http://compulab.co.il/products/computer-on-modules/cm-t54/http://compulab.co.il/products/sbcs/sbc-t54/
SBC-T54 is a single board computer based on OMAP5432 CPU.
It is implemented with a CM-T54 CoM providing most of the functions,
and SB-T54 carrier board providing connectors and several additional
functions.
Added basic support for:
* PMIC
* LED
* MMC/SD
* eMMC
* USB
* I2C1/4
* SB-T54 and CM-T54 EEPROMs
* RTC
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
[tony@atomide.com: updated for Makefile sorting]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Expose the PMU on OMAP5.
Tested with perf on OMAP5 uEVM.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The N950/N9 uses two additional regulators from the twl 4030 for CSI-2
receiver (vaux2) and cameras (vaux3).
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for the Nokia N900's sound
system.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Reviewed-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add madc node to twl4030, so that board DTS
files can simply reference the A/D converter.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add device tree support for the wireless chip
built into the Nokia N900.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable
- USB PHY
- USB
for am43x-epos-evm
Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable
- USB PHY
- USB
for am437x-gp-evm
Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add nodes for 2 instances each of
- ocp2scp
- USB PHY control module
- USB PHY
- dwc3_omap
- USB
for AM43xx.
Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add USB and USB PHY reference clock data
Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
[tony@atomide.com: tabified]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Venice2 can detect write-protect on the SD card. Add the required
DT entries to allow this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
[swarren: fixed GPIO polarity per Thierry's testing]
Tested-by: Thierry Reding <treding@nvidia.com>
With ARCH_OMAP2PLUS being separated out into OMAP2/3/4/5 etc all the TI device
tree blobs are built no matter the combination of SoCs that are enabled. This
often causes a bunch of irrelevant .dts to be built on a multi platform kernel,
this enables the building of just the ones relevant to the SoCs that are
actually enabled. It also orders the dts file alphabetically.
This also helps to avoid trivial merge conflicts when adding support
for new boards.
[tony@atomide.com: updated the order for am335x and am43x, moved am3517 to omap3]
Signed-off-by: Tony Lindgren <tony@atomide.com>
MTD NAND partition for file-system should start at offset=0xA00000
Signed-off-by: Pekon Gupta <pekon@ti.com>
[tony@atomide.com: changed to lower case hex like we tend to use]
Signed-off-by: Tony Lindgren <tony@atomide.com>
- Use generic node names
- Fix up some weird formatting and white spaces
- Update copyright info
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.
Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The timers and uart can get their clock frequencies using the common clock
driver.
Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The Altera Cyclone5 and Arria5 devkit has an EEPROM and a RTC on the
board. This patch adds support for them.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v2: Remove LCD as the driver has not been upstreamed.
