Dinh Nguyen 8cb289ed60 ARM: socfpga: dts: Add div-reg to the main_pll clocks ... The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>		2014-05-05 22:33:18 -05:00
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bootp
compressed	ARM: 7992/1: boot: compressed: ignore bswapsdi2.S	2014-03-07 22:04:10 +00:00
dts	ARM: socfpga: dts: Add div-reg to the main_pll clocks	2014-05-05 22:33:18 -05:00
.gitignore
install.sh	arm, kbuild: make "make install" not depend on vmlinux	2013-10-02 22:30:35 +02:00
Makefile	arm, kbuild: make "make install" not depend on vmlinux	2013-10-02 22:30:35 +02:00