This adds the remaining SAI instances SAI0, SAI1 and SAI3. All
instances are very similar, except that the DMA channel of SAI3
is available on MUX1 (compared to MUX0 for SAI0-SAI2). Also,
SAI3 has a slightly different memory map due to a deeper FIFO,
however in practice the current driver works for SAI3 fine.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This reverts commit 8ba671efdb.
As reported by kbuild test robot <fengguang.wu@intel.com>:
In file included from arch/arm/boot/dts/mt2701-evb.dts:16:0:
>> arch/arm/boot/dts/mt2701.dtsi:18:28: fatal error: mt2701-pinfunc.h: No such file or directory
#include "mt2701-pinfunc.h"
^
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since the switch from mmp_pdma to pxa_dma driver for pxa architectures,
the pxa_dma requires 2 arguments, namely the requestor line and the
requested priority.
Fix the only left device node which was still passing only one argument,
making the pxa3xx-nand driver misbehave in a device-tree configuration,
ie. failing all data transfers.
Fixes: c943646d1f ("ARM: dts: pxa: add dma engine node to pxa3xx-nand")
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Merge "Broadcom devicetree changes for 4.6" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoCs Device Tree changes:
- Rafal adds a Device Tree for the D-Link DIR-885L router which is based on the
BCM47094 SoC similar to the BCM4709
- Simran adds proper audio clock Device Tree nodes to the Cygnus platforms
- Martin adds the auxiliary SPI controllers, makes the UART naming convention
more standard, and finally adds the auxiliary UART found in the BCM2835 to the
BCM2835 Device Tree
- Remi adds PWM clock support to the BCM2835 Device Tree
- Lubomir adds a Device Tree for the Raspberry Pi Model A
- Alexander adds Device Tree information for the Raspberry Pi USB power domain
- Dhananjay enables the GPIO-A controller for the Northstar Plus SoCs
- Jon fixes the PCIE Device Tree nodes by pulling them out of the bus-level node,
removes duplicate CPU definitions, adds PMU nodes, SP804 timers, and SP805 watchdog
to the Northstar Plus SoCs
* tag 'arm-soc/for-4.6/devicetree' of http://github.com/Broadcom/stblinux:
ARM: bcm2835: add bcm2835-aux-uart support to DT
ARM: dts: NSP: Add SP805 Support to DT
ARM: dts: NSP: Add SP804 Support to DT
ARM: dts: NSP: Add PMU Support to DT
ARM: dts: NSP: Fix CPU DT issue
ARM: dts: NSP: Fix PCIE DT issue
ARM: dts: enable GPIO-a for Broadcom NSP
ARM: bcm2835: Add the Raspberry Pi power domain driver to the DT.
ARM: bcm2835: dt: Add Raspberry Pi Model A
ARM: bcm2835: follow dt uart node-naming convention
ARM: bcm2835: Add PWM clock support to the device tree
ARM: bcm2835: add the auxiliary spi1 and spi2 to the device tree
ARM: dts: Add audio clock to the existing Broadcom Cygnus clock DT
ARM: BCM5301X: Add DT for D-Link DIR-885L
With the newly available MSIX driver for Alpine, add the corresponding
node in the Alpine device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Declare the number of DMA requestor lines per platform :
- for pxa25x: 40 requestor lines
- for pxa27x: 75 requestor lines
- for pxa3xx: 100 requestor lines
This information will be used to activate the DMA flow control or not.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
- Add usb phy for Zybo
- Use earlycon instead of earlyprintk
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Merge tag 'zynq-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/dt
Merge "ARM: Xilinx Zynq dt patches for v4.6" from Michal Simek
- Add usb phy for Zybo
- Use earlycon instead of earlyprintk
* tag 'zynq-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: Use earlycon instead of earlyprintk
ARM: dts: zynq: Enable USB and USB PHY for ZYBO
K2G SoC family is the newest version of the Keystone family of processors.
The technical reference manual for K2G can be found here:
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf
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Merge tag 'keystone_dts_for_4.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/dt
Merge "ARM: Keystone DTS for 4.6" from Santosh Shilimkar:
ARM: DTS: Add new bindings for K2G and the K2G evm
K2G SoC family is the newest version of the Keystone family of processors.
The technical reference manual for K2G can be found here:
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf
* tag 'keystone_dts_for_4.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: dts: keystone: Add minimum support for K2G evm
ARM: dts: keystone: Add Initial DT support for TI K2G SoC family
ARM: keystone: Create new binding for K2G SoC
adding board specific devices and few new boards:
- N900 improvments for adp1653 and gpio keys
- Add missing bandgap data for omap3
- Add more devices for compulab cm-t335
- Add n950 WLAN support, enable modem, add pinctrl for SSI
- Correct dm814x and dra62x auxclk rate, add support for GPMC and NAND
- Add syscon node for PHY's on dra7
- Add support more devices on logicpd torpedo
- Add USB host support for igep and specify boot console
- Fix audio clock for am335x-sl50 and specify boot console
- Remove deprecated tx-fifo-resize for dwc3 that was only used on
omap5 es1.0
- Add dra7 thermal data
- Update am43x-epos-evm compatible string to am438
- Add support for logicpd dm3730 som-lv
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Merge tag 'omap-for-v4.6/dt-pt1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Device tree changes for omaps for v4.6 merge window. Mostly just
adding board specific devices and few new boards:
- N900 improvments for adp1653 and gpio keys
- Add missing bandgap data for omap3
- Add more devices for compulab cm-t335
- Add n950 WLAN support, enable modem, add pinctrl for SSI
- Correct dm814x and dra62x auxclk rate, add support for GPMC and NAND
- Add syscon node for PHY's on dra7
- Add support more devices on logicpd torpedo
- Add USB host support for igep and specify boot console
- Fix audio clock for am335x-sl50 and specify boot console
- Remove deprecated tx-fifo-resize for dwc3 that was only used on
omap5 es1.0
- Add dra7 thermal data
- Update am43x-epos-evm compatible string to am438
- Add support for logicpd dm3730 som-lv
* tag 'omap-for-v4.6/dt-pt1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (38 commits)
ARM: dts: am57xx-beagle-x15: Add eeprom information
ARM: dts: Add HSUSB2 EHCI Support to Logic PD DM37xx SOM-LV
ARM: dts: n900: Use linux input defines instead hardcoded constants
ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV
ARM: dts: omap3logic: Add PWM-Backlight
ARM: dts: omap3-n900: Allow gpio keys to be disabled
ARM: dts: am43x-epos-evm: Add the am438 compatible string
ARM: dts: DRA7: Add missing IVA and DSPEVE thermal domain data
ARM: dts: DRA7: Add IVA thermal data
ARM: dts: DRA7: Add DSPEVE thermal data
ARM: dts: remove deprecated property dwc3
ARM: dts: OMAP3-N950-N9: Add ssi idle pinctrl state
ARM: dts: am335x-sl50: Fix audio codec setup.
ARM: dts: am335x-sl50: Specify the device to be used for boot console output.
ARM: dts: omap3-igep0030-common: Add USB Host support
ARM: dts: igep00x0: Specify the device to be used for boot console output.
ARM: dts: LogicPD Torpedo: Set HSUSB0 Pin Mux
ARM: dts: OMAP3-N950-N9: Enable modem
ARM: dts: OMAP3-N950-N9: Enable SSI module
ARM: dts: LogicPD Torpedo: Add SPI EEPROM
...
Enable SMP support for mt7623.
Enable SMP support for mt2701
Add pinctrl for mt2701
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Merge tag 'v4.5-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt
Merge "ARM: mediatek: dts updates for v4.6" from Matthias Brugger:
Add support for mt7623 SoC.
Enable SMP support for mt7623.
Enable SMP support for mt2701
Add pinctrl for mt2701
* tag 'v4.5-next-dts' of https://github.com/mbgg/linux-mediatek:
arm: dts: Add pinctrl/GPIO/EINT node for mt2701
ARM: dts: mt2701: enable basic SMP bringup for mt2701
ARM: dts: mt7623: enable SMP bringup
ARM: dts: mediatek: add MT7623 basic support
Document: DT: Add bindings for mediatek MT7623 SoC Platform
OrangePi Plus board has dwo leds - green ("pwr") and red ("status")
and a switch ("sw4"). This patch describes them in a devicetree.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch adds correct aliases to spi and i2c buses so that they get
correct matching bus numbers.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds i2c6 device node and pinctrls required for IFC6410 on
MIPI-CSI connector.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch enables i2c bus for camera via mipi-csi connector on ifc6410.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds gsbi4 and i2c node.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds missing i2c2 pinctrl information in i2c2 node.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch enables spi device on the 30 pin expansion connector.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds spi5 device node, spi5 is used on ifc6410 on the
expansion connector.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds missing i2c pinctrl sleep states.
Also add 16mA drive strength to the pins so that we can detect wide
range of i2c devices on the other side of level shifters.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds PCIE support to APQ8064, tested with Ethernet on
Compulab QS600 board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
As there are more pinctrls to come, moving these to dedicated dtsi makes
more sense.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch fixes i2c lables to be inline with serial labels.
The reason to do this is that it would look odd if we add aliases in the
board file along with serial.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
LogicPD has two main Torpedo styles, a version with wireless and a version
without wireless. This version has Bluetooth and WiFi, but there really
isn't an easy way to identify them automatically. This simply adds
"Wireless" to the model to distinguish it from the 'base' model that will
come soon.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].
[1] dm816x TRM: SPRUGX8C: 9.2.4.12.2 NAND Device-Ready Pin
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].
[1] AM335x TRM: SPRUH73L: 7.1.3.3.12.2 NAND Device-Ready Pin
Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].
[1] AM437x TRM: SPRUHL7D: 9.1.3.3.12.2 NAND Device-Ready Pin
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
wait pin monitoring is not used for nand so it is pointless to
have the gpmc,wait-monitoring-ns property.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the 1588 timer node for ls1021a platform to
support gianfar ptp driver.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The H3 ir receiver is completely compatible with the one found in the A31.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.
After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The lamobo-r1 board, sometimes called the BPI-R1 but not labelled as such
on the PCB, is meant as a A20 based router board. As such the board comes
with a built-in switch chip giving it 5 gigabit ethernet ports, and it
has a large empty area on the pcb with mounting holes which will fit a
2.5 inch harddisk. To complete its networking features it has a
Realtek RTL8192CU for WiFi 802.11 b/g/n.
Signed-off-by: Jelle de Jong <jelledejong@powercraft.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add barebones K2G evm dts. This DTS allows the board to boot using a
ram based filesystem.
The technical reference manual for K2G can be found here:
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
K2G is the newest addition of TI's Keystone 2 product family. It is a
single core Cortex A15 and a C66x DSP.
K2G supports standard peripherals such as SPI, UART, MMC and USB 2.0.
Includes two dual-core Programmable Real-time Unit and Industrial
Communication Subsystems (PRU-ICSS).
The technical reference manual for K2G can be found here:
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf
This device is targeted for a variety of applications which include, but
are not limited to:
Home audio
Professional audio
Industrial Programmable Logic Control
The peripheral nodes that have been included in this patch have been
tested during bring-up. Since all peripherals will not necessarily be
used on all boards, disable all peripherals by default. This allow
the board dts to selectively choose which peripherals it wants to
enable.
This SoC now uses the next generation of power management architecture
with the PM functionality located in a microcontroller embedded in the SOC.
Support for this new PM architecture along with other peripherals will be
added in future patches.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Use early console instead of earlyprintk which is supposed to use for
very early debugging (DEBUG_LL).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds USB HS support in host mode only.
This port supports OTG mode, but the device more is not working
properly as of now.
Once the device mode fixed, the node will be updated to support OTG.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Make it possible to select which I2C IP core you want to run on the
EXIO-A connector. This is the reference how to use this feature. Update
the copyright while we are here.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Addition of the ADC for sama5d2 and sama5d2_xplained
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Merge tag 'at91-ab-4.6-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/dt
DT changes for 4.6:
- Addition of the ADC for sama5d2 and sama5d2_xplained
* tag 'at91-ab-4.6-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: dts: at91: sama5d2 Xplained: enable the adc device
ARM: dts: at91: sama5d2: add adc device
Signed-off-by: Olof Johansson <olof@lixom.net>
All Exynos SoCs have the same syscon reboot and poweroff device nodes so
there is no need to duplicate the same on each SoC dtsi and can be moved
to a common dtsi that can be included by all the SoCs dtsi files.
Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung,com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
- Finalize RealView the PB1176 and PB11MPCore device trees
- Move Versatile to use the power/reset driver instead of a
custom restart hook
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Merge tag 'versatile-dt-cleanup-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Versatile DT cleanups from Linus Walleij:
"this is a first pull request for my cleanups for the Versatile, as
the finished stuff should not be sitting in my tree but in ARM SoC.
This completes the ARM RealView PB1176 and PB11MPCore device trees,
and moves the Versatile to use power/reset.
The idea is to keep working on this cleanup branch and send additional
patches on top of this one as the prerequisites are merged into the MTD
and FBDEV subsystems. So please create a special versatile cleanup branch
(or suggest another approach).
As it happens, board files and device trees need to change at the same
time to make logical sense, especially for Versatile where auxdata is
replaced with DT entries, such as when reset is moved in the last patch
in this set. The MTD and CLCD changes will share this characteristic."
Versatile family cleanups step 1:
- Finalize RealView the PB1176 and PB11MPCore device trees
- Move Versatile to use the power/reset driver instead of a
custom restart hook
* tag 'versatile-dt-cleanup-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: versatile: move restart to the device tree
ARM: realview: add the DS1338 RTC to PB1176 DT
ARM: pb1176: add ethernet to devicetree
ARM: pb1176: add ISP1761 USB OTG host controller
ARM: pb1176: add AACI to the device tree
ARM: pb1176: add ICST307 clocks to the device tree
ARM: realview: fix up PB11MP flash compat strings
ARM: realview: add flash devices to the PB1176 DTS
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Add SROM controller device nodes.
2. Add Ethernet chip as child of SROM controller on SMDK5410.
3. Allow simultaneous usage exynos-rng and s5p-sss drivers on Exynos5.
4. Cleanup CPU configuration on Exynos542x/5800.
5. Add necessary nodes for cpufreq-dt driver on Exynos542x/5800 (OPPs,
regulator supplies) which allows frequency and voltage scalling
of this SoC.
6. Minor cleanups.
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Merge tag 'samsung-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DeviceTree updates and improvements for v4.6:
1. Add SROM controller device nodes.
2. Add Ethernet chip as child of SROM controller on SMDK5410.
3. Allow simultaneous usage exynos-rng and s5p-sss drivers on Exynos5.
4. Cleanup CPU configuration on Exynos542x/5800.
5. Add necessary nodes for cpufreq-dt driver on Exynos542x/5800 (OPPs,
regulator supplies) which allows frequency and voltage scalling
of this SoC.
6. Minor cleanups.
* tag 'samsung-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: Replace legacy *,wakeup property with wakeup-source for exynos boards
ARM: dts: Add GSCL block parent clock management to pm domain on exynos542x
ARM: dts: Extend existing CPU OPP for exynos5800
ARM: dts: Add CPU OPP properties for exynos542x/5800
ARM: dts: Add cluster regulator supply properties for exynos542x/5800
ARM: dts: Make CPU configuration more readable on exynos542x/5800
ARM: dts: Replace legacy *,wakeup property with wakeup-source on s5pv210
ARM: dts: Allow simultaneous usage exynos-rng and s5p-sss drivers on exynos5
ARM: dts: Add Ethernet chip to exynos5410-smdk5410
ARM: dts: Add SROM to exynos5410
ARM: dts: Add SROM device node for exynos5
ARM: dts: Add SROM device node for exynos4
ARM: dts: Add pinctrl support to exynos5410
Signed-off-by: Olof Johansson <olof@lixom.net>
* Use SCIF and USBHS fallback compatibility strings
* Add Baud Rate Generator (BRG) support for (H)SCIF
* Enable SCIF_CLK frequency and pins
* Use GIC_* defines
* Enable audio on r8a7793/gose
* Enable HDMI vidio out on r8a7793
* Enable i2c on r8a7793/gose
* Enable QSPI on alt
* Enable GPIO keys and leds on gise
* Enable audio on porter
* Enable DU on porter
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Merge tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.6
* Use SCIF and USBHS fallback compatibility strings
* Add Baud Rate Generator (BRG) support for (H)SCIF
* Enable SCIF_CLK frequency and pins
* Use GIC_* defines
* Enable audio on r8a7793/gose
* Enable HDMI vidio out on r8a7793
* Enable i2c on r8a7793/gose
* Enable QSPI on alt
* Enable GPIO keys and leds on gise
* Enable audio on porter
* Enable DU on porter
* tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (68 commits)
ARM: dts: silk: Enable SCIF_CLK frequency and pins
ARM: dts: porter: Enable SCIF_CLK frequency and pins
ARM: dts: marzen: Enable SCIF_CLK frequency and pins
ARM: dts: lager: Enable SCIF_CLK frequency and pins
ARM: dts: koelsch: Enable SCIF_CLK frequency and pins
ARM: dts: gose: Enable SCIF_CLK frequency and pins
ARM: dts: bockw: Enable SCIF_CLK frequency and pins
ARM: dts: alt: Enable SCIF_CLK frequency and pins
ARM: dts: r8a7794: Add BRG support for (H)SCIF
ARM: dts: r8a7793: Add BRG support for SCIF
ARM: dts: r8a7791: Add BRG support for (H)SCIF
ARM: dts: r8a7790: Add BRG support for (H)SCIF
ARM: dts: r8a7779: Add BRG support for SCIF
ARM: dts: r8a7778: Add BRG support for SCIF
ARM: dts: r8a7794: Rename the serial port clock to fck
ARM: dts: r8a7793: Rename the serial port clock to fck
ARM: dts: r8a7791: Rename the serial port clock to fck
ARM: dts: r8a7790: Rename the serial port clock to fck
ARM: dts: r8a7779: Rename the serial port clock to fck
ARM: dts: r8a7778: Rename the serial port clock to fck
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Initial device tree for the Artpec-6 SoC.
Signed-off-by: Lars Persson <larper@axis.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
nodes and fixes like the increased drive-strength on the firefly.
Most interesting is maybe the enablement of the pl330 option
for handling the broken flushp operation that is present on the
current Rockchip SoCs. Together with the driver-side enablement
this should give us working dma finally.
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Merge tag 'v4.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Assorted bunch of 32bit Rockchip devicetree changes. More clocks,
nodes and fixes like the increased drive-strength on the firefly.
Most interesting is maybe the enablement of the pl330 option
for handling the broken flushp operation that is present on the
current Rockchip SoCs. Together with the driver-side enablement
this should give us working dma finally.
* tag 'v4.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (30 commits)
ARM: dts: cros-ec-keyboard: Add LOCK key to keyboard matrix
ARM: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
ARM: dts: rockchip: add arm,pl330-broken-no-flushp quirk for rk3036 SoCs
ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3xxx platform
ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3288 platform
dt-bindings: rockchip-dw-mshc: add RK3036 dw-mshc description
ARM: dts: rockchip: increase the mclk_fs to 512 for kylin board
ARM: dts: rockchip: support the spi for rk3036
ARM: dts: rockchip: add mclk for rt5616 on rk3036 kylin board
ARM: dts: rockchip: add the leds control for rk3036-kylin board
ARM: dts: rockchip: add tsadc node
clk: rockchip: Add new id for rk3066 tsadc clock
ARM: dts: rockchip: add clock-cells for usb phy nodes
ARM: dts: rockchip: Assign RK3288 EDP_24M input centrally
ARM: dts: rockchip: add soc-specific compatibles for rk3036 SoCs
ARM: dts: rockchip: Bump sd card pin drive strength up on firefly boards
dt-bindings: rockchip-dw-mshc: add RK3368 dw-mshc description
ARM: dts: rockchip: Add the SDIO wifi on Radxa Rock2 square
ARM: dts: rockchip: Add the iodomains for the Rock2 SOM
ARM: dts: rockchip: add rk3288 mipi_dsi nodes
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge DT changes for lpc32xx from Vladimir Zapolskiy:
"The changes add description of clock providers and clock consumers,
define default irq types of SoC controllers and add PHY3250 board
regulators.
I'm adding an official LPC32xx maintainer Roland to Cc, however he seems
to be unresponsive for a quite long time (since 2014)."
* 'lpc32xx/dt' of https://github.com/vzapolskiy/linux:
arm: dts: phy3250: add SD fixed regulator
arm: dts: phy3250: add lcd and backlight fixed regulators
arm: dts: lpc32xx: assign interrupt types
arm: dts: lpc32xx: remove clock frequency property from UART device nodes
arm: dts: lpc32xx: add USB clock controller
arm: dts: lpc32xx: add clock properties to device nodes
arm: dts: lpc32xx: add clock controller device node
arm: dts: lpc32xx: add device nodes for external oscillators
dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it
Signed-off-by: Olof Johansson <olof@lixom.net>
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.
Few dts files assign value "1" to gpio-key,wakeup which is incorrect.
Since the presence of the boolean property indicates it is enabled,
value of "0" or "1" have no significance.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- Yet another fix for n900 onenand to avoid corruption. This time to
fix the issue of mounting onenand back and forth between the original
maemo kernel and mainline Linux kernel. And it also seems there will
be two more fixes coming via the MTD tree as issues were discovered
also in the onenand driver during testing.
- Revert tps65217 regulator clean up as it breaks MMC for am335x
variants. The proper way to clean this up is just to rename the
tps65217.dtsi file into tps65217-am335x.dtsi as a similar setup
is used on many am335x boards.
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Merge tag 'omap-for-v4.5/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Two omap fixes for omaps against v4.5-rc5:
- Yet another fix for n900 onenand to avoid corruption. This time to
fix the issue of mounting onenand back and forth between the original
maemo kernel and mainline Linux kernel. And it also seems there will
be two more fixes coming via the MTD tree as issues were discovered
also in the onenand driver during testing.
- Revert tps65217 regulator clean up as it breaks MMC for am335x
variants. The proper way to clean this up is just to rename the
tps65217.dtsi file into tps65217-am335x.dtsi as a similar setup
is used on many am335x boards.
* tag 'omap-for-v4.5/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix onenand initialization to avoid filesystem corruption
Revert "regulator: tps65217: remove tps65217.dtsi file"
Signed-off-by: Olof Johansson <olof@lixom.net>
PIN_PA15 macro has the same value as PIN_PA14 so we were overriding PA14
mux/configuration.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reported-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Fixes: 7f16cb676c ("ARM: at91/dt: add sama5d2 pinmux")
Cc: <stable@vger.kernel.org> # v4.4+
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- Drop the bogus interrupt-parent from i.MX6 CAAM node, which leads to
the CAAM IRQs not getting unmasked at the GPC level.
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Merge tag 'imx-fixes-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
The i.MX fixes for v4.5:
- Drop the bogus interrupt-parent from i.MX6 CAAM node, which leads to
the CAAM IRQs not getting unmasked at the GPC level.
* tag 'imx-fixes-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6: remove bogus interrupt-parent from CAAM node
Signed-off-by: Olof Johansson <olof@lixom.net>
- Improve omap_device error message to tell driver writers what is
wrong after commit 5de85b9d57 ("PM / runtime: Re-init runtime PM
states at probe error and driver unbind"). There will be also a
handful of driver related fixes also queued separately. But adding
this error message makes it easy to fix any omap_device using
drivers suffering from this issue so I think it's important to
have.
- Also related to commit 5de85b9d57 discussion, let's fix a bug
where disabling PM runtime via sysfs will also cause the hardware
state to be different from PM runtime state.
- Fix audio clocks for beagle-x15.
- Use wakeup-source instead of gpio-key,wakeup for the new entries
that sneaked in during the merge window.
- Fix a legacy booting vs device tree based booting regression for
n900 where the legacy user space expects to have the device
revision available in /proc/atags also when booted with device
tree.
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Merge tag 'omap-for-v4.5/fixes-rc3-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Few fixes for omaps against v4.5-rc3:
- Improve omap_device error message to tell driver writers what is
wrong after commit 5de85b9d57 ("PM / runtime: Re-init runtime PM
states at probe error and driver unbind"). There will be also a
handful of driver related fixes also queued separately. But adding
this error message makes it easy to fix any omap_device using
drivers suffering from this issue so I think it's important to
have.
- Also related to commit 5de85b9d57 discussion, let's fix a bug
where disabling PM runtime via sysfs will also cause the hardware
state to be different from PM runtime state.
- Fix audio clocks for beagle-x15.
- Use wakeup-source instead of gpio-key,wakeup for the new entries
that sneaked in during the merge window.
- Fix a legacy booting vs device tree based booting regression for
n900 where the legacy user space expects to have the device
revision available in /proc/atags also when booted with device
tree.
* tag 'omap-for-v4.5/fixes-rc3-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix omap_device for module reload on PM runtime forbid
ARM: OMAP2+: Improve omap_device error for driver writers
ARM: DTS: am57xx-beagle-x15: Select SYS_CLK2 for audio clocks
ARM: dts: am335x/am57xx: replace gpio-key,wakeup with wakeup-source property
ARM: OMAP2+: Set system_rev from ATAGS for n900
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu fixes for 4.5 (part 2)
- Fix the missing mtd flash on linkstation lswtgl
- Use unique machine name for the kirkwood ds112 (for Debian flash-kernel tool)
* tag 'mvebu-fixes-4.5-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: orion5x: fix the missing mtd flash on linkstation lswtgl
ARM: dts: kirkwood: use unique machine name for ds112
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The #size-cells for the pmics are 0, but we specify a size in the
reg property so that MPP and GPIO modules can figure out how many
pins there are. Now that we've done that by counting irqs, we can
remove the size elements in the reg properties and be DT
compliant.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds a dts file to support the Nexus7 2013
device. Its based off of the qcom-apq8064-ifc6410.dts
which is similar hardware.
Also includes some comments and context folded in
from Vinay Simha BN <simhavcs@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd.bergmann@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Andy Gross <agross@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Vinay Simha BN <simhavcs@gmail.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds address-cell and size-cell values to the i2c3 bus
in the qcom-apq8064.dtsi, which is needed to describe devices
on that bus.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd.bergmann@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Andy Gross <agross@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Vinay Simha BN <simhavcs@gmail.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
These clocks are fixed rate board sources that should be in DT.
Add them.
Cc: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the additional reserved regions found on 8974 based devices.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
All the clocks referenced by the GPIO banks were not the good ones.
Reported-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
This change does not break existing userspace or Maemo software because
isp1704_charger.c always export power supply device under isp1704 name.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Add EEPROM at 0x50 that describes the board configuration.
This is useful for userspace programs that may need to check board
revision and other similar information.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Logic PD SOM-LV has a USB Host Controller connected to 3-port
hub. This enables the pin muxing for the host controller and
ehci-phy.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This makes DTS structure more readable.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-By: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Logic PD DM37xx SOM-LV devkit consists of a base board and a SOM.
While the SOM (System on Module) supports Bluetooth and WiFi, LPD did not
obtain an FCC ID, so anyone who uses it will have to go through certification.
I have only tested the Type 28 Display, SMSC9211 Ethernet, SD/MMC and basic
power management, however the overall current seems high.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The backlight pin is shared with Timer 10 PWM. This patch allows the
pwm_bl driver to enable the pwm run by this timer to dim the backlight.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add linux,can-disable; to all gpios exported from gpio-keys driver, so
userspace can disable them
Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The "$(suffix_y)" no longer appears in the file names, but it just
specifies the method of the file compression. The "compress-y" sounds
more suitable.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The files piggy.$(suffix).S are similar enough to be merged into a
single file. This also allows clean up of the Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The object "piggy.$(suffix_y).o" is created from "piggy.$(suffix).S"
by the following pattern rule defined in scripts/Makefile.build:
$(obj)/%.o: $(src)/%.S FORCE
$(call if_changed_dep,as_o_S)
FORCE is already added to the prerequisite of the object there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This code works fine here, but it is tricky to use "extra-y" for
specifying files to be removed during "make clean". Kbuild provides
"clean-files" for this purpose.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The objects "font.o" and "misc.o" are contained in $(OBJS), and it
is already added to the "targets".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The "targets" exists to specify which files need the corresponding
".*_cmd" files to be included during the build. In other words, it
is used for files that need to detect the change of the command line
by if_changed, if_changed_dep, and if_changed_rule. While, these
files are just copied by "$(call cmd,shipped)". Adding them to the
"targets" is meaningless because $(call cmd,...) never creates
".*_cmd" files. Such files as ".lib1funcs.S.cmd", ".ashldi3.S.cmd"
do not exist in the first place.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARMv6 CPUs do not have virtualisation extensions, but hyp-stub.S is
still included into the image to keep it generic. In order to use ARMv7
instructions during HYP initialisation, add -march=armv7-a flag to
hyp-stub's build.
On an ARMv6 CPU, __hyp_stub_install returns as soon as it detects that
the mode isn't HYP, so we will never reach those instructions.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARMv6 CPUs do not have virtualisation extensions, but hyp-stub.S is
still included into the image to keep it generic. In order to use ARMv7
instructions during HYP initialisation, add -march=armv7-a flag to
hyp-stub's build.
On an ARMv6 CPU, __hyp_stub_install returns as soon as it detects that
the mode isn't HYP, so we will never reach those instructions.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enable the OTG USB controller on the A7HD.
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4.5 because required header files went through other trees, plus the
AUX uart support this time around.
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Merge tag 'bcm2835-dt-next-2016-02-17' into devicetree/next
This pull request covers mostly DT changes that didn't make it into
4.5 because required header files went through other trees, plus the
AUX uart support this time around.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The SoCs on am43x-epos-evm are named am438x.
Hence add the compatibility string and remove the am4372 string.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This reverts commit 8e6ebfaa9b.
Without the patch reverted regulators will not work. This prevents
MMC to be working for example so the boards can not boot to
MMC rootfs.
Tested it on beaglebone white and bisect also points to the
reverted commit.
The issue can be also fixed by adding "regulator-compatible =" to all board
dts file for the regulators.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Define the generic R8A7794 part of the EtherAVB device node.
Based on the commit 46ece349aa ("ARM: shmobile: r8a7791: add EtherAVB DT
support").
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the EtherAVB clock to the R8A7794 device tree.
Based on the commit eaa870b305 ("ARM: shmobile: r8a7791: add EtherAVB
clock").
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Changelog text from a similar patch by Sudeep Holla.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the L2 cache, and link the CPU node to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device nodes for the L2 caches, and link the CPU nodes to them.
The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables to use thermal-zone on r8a7793.
This thermal sensor can measure temperature from -40000 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
90000, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifying polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reaches to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the ADC device, and remove the adc_op_clk which is useless since the
adc sampling frequency is configured with sysfs.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
It's pretty similar to the STM32F429, but there are some
subtle changes required to boot successfully.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
These two targets were introduced by commit 13d5fadf45 ("[ARM]
Make 'i' and 'zi' targets work") to short-circuit the dependencies
for 'install' and 'zinstall'.
After that, commit 19514fc665 ('arm, kbuild: make "make install"
not depend on vmlinux') eventually made "(z)install" equivalent to
"(z)i".
It is true that 'i' and 'zi' might be still useful as shorthands
but the original intention had been already lost.
They do not even show up in "make ARCH=arm help", so I hope this
deletion does not have much impact.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
"PHONY += FORCE" is already cared by scripts/Makefile.build,
which this file is included from.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enable the otg/drc usb controller on the MK802.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.
Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.
Also update the regulator supply phandles.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch enables to use thermal-zone on r8a7791.
This thermal sensor can measure temperature from -40000 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
90000, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifying polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reaches to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables to use thermal-zone on r8a7790.
This thermal sensor can measure temperature from -40000 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
90000, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifying polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reaches to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When finishing the Porter sound support patch, I managed to call the JP3
jumper SW3 in the comment. Fix this along with (also miscalled) jumper
positions...
Fixes: 493b4da7c1 ("ARM: dts: porter: add sound support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for the ARM SP805 Watchdog timer to the Northstar Plus
device tree.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add support for the ARM SP804 timer to the Northstar Plus device tree.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add support for the ARM Performance Monitor Unit to the Northstar Plus
device tree.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
There is a double definition of the CPUs present in the device tree.
Remove unnecessary cpu device tree definition.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Adding the ranges value is preventing the PCI nodes from working.
Pulling them out outside makes them work again (and makes it similar to
the NS2 device tree).
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
OMAP5 has 3 thermal zones cpu, core and multimedia.
On the other hand DRA7 has 5 thermal zones cpu, gpu, core, dspeve
and iva. Currently cpu, core and multimedia are being added via device tree
and the other 2 are getting added via kernel. Add the missing thermal
domains in device tree so we can create the zones with the appropriate
trip numbers, type and temperatures.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch changes a dtsi file to contain the thermal data
for IVA domain. This data will enable a thermal shutdown at 125C.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch changes a dtsi file to contain the thermal data
for DSPEVE domain. This data will enable a thermal shutdown at 125C.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DWC3's tx-fifo-resize property has been deprecated
because of it being unnecessary to any HW other than
OMAP5 ES1.0.
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds an idle pinctrl state, which will be used
by the driver to avoid incoming data during clock
rate changes or data flushing.
Signed-off-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The MCLK is provided by an external clock of 24.576MHz.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
UART0 device is the device to be used for boot console output.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Provide RESET GPIO for the USB PHY, the USB Host port mode and
the PHY device for the controller. Also provides pin multiplexer
information for USB host pins.
Signed-off-by: Pau Pajuel <ppajuel@gmail.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
UART3 device is the device to be used for boot console output.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch defines the pin muxing to configure the hsusb0 through
the twl4030 PMIC, because we can't always assume the bootloader will
do it correctly.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Nokia N950 and Nokia N9 have a modem attached to their
first ssi port. This change adds the modem to the SSI port.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Nokia N950 and Nokia N9 have a modem attached to their
first ssi port. This change adds all necessary information
to initialize the SSI module, but does not yet add the
modem information.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The devkit has an AT25 EEPROM on MCSPI1. Enable this with default
parameters.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Setup regulator and fix pin muxing to allow Panel to sleep and
wake from sleep for some low power improvements.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Wireless version of the SOM uses an AT24 EEPROM to store product ID.
The EEPROM is readonly.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Logic PD Torpedo standard kits come with a SOM populated to us an
8-bit parallel camera interface. This patch pin muxes the omap3-isp
pins, sets the MT9P031 clicks, and configures the i2c2 bus to communicate
with the mt9p031 on address 0x48.
I have not done a lot of testing, but when modprobing
mt9p031, then omap3-isp, the board responds with
MT9P031 detected at address 0x48.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
property from SATA and USB PHY node. Also remove the unused control
module dt nodes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string "ti,dra7x-usb2-phy2" for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add "syscon-phy-power" property and "syscon-pcs" property which can
be used to perform the control module initializations and remove
the deprecated "ctrl-module" property from PCIe PHY dt nodes.
Phandle to "sysclk" clock node is also added to the PCIe PHY node
since some of the syscon initializations is based on system clock
frequency.
Since "omap_control_pcie1phy" and "omap_control_pcie2phy" devicetree
nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit adds the Device Tree description for the 1GB NAND flash
present in the Armada 370 DB and Armada XP DB evaluation boards from
Marvell.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 375 has the same SATA IP as Armada 370 and Armada XP, which
requires the PHY speed to be set in the LP_PHY_CTL register for SATA
hotplug to work.
Therefore, this commit updates the compatible string used to describe
the SATA IP in Armada 375 from marvell,orion-sata to
marvell,armada-370-sata.
Fixes: 4de5908509 ("ARM: mvebu: add Device Tree description of the Armada 375 SoC")
Cc: <stable@vger.kernel.org>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Recent versions of libfdt add a dependency on strnlen. Copy the
implementation in lib/string.c here, so we can update libfdt.
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Rob Herring <robh@kernel.org>
This enables the GPIO-a support for Broadcom NSP SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The PB1176 device tree was missing the SMSC9118 ethernet adapter,
so add it. Since this peripheral is not in either development
chip but on the board itself, it gets defined in the root node
of the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The USB host controller was missing from the device tree so add
it. This device is not inside either the development chip or the
FPGA but mounted on the board, so it ends up in the root node of
the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The device tree was missing the definition of the AACI
Advanced Audio Codec Interface, so add it. Tested on the hardware
and it works.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The two flash memories in the PB11MPCore have their VPP/WP
lines controlled from the system controller add-on in the MTD
subsystem. "arm,versatile-flash" is the first compatible string
to use to get the right support.
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the flash memories and ROM to the PB1175 DTS file.
The secure flash is marked as "disabled" by default so as to
protect the user from overwriting the boot monitor.
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0,
by writing 0x4 to SYSCFG_MEMRMP register.
As mentionned in the reference manual (see chapter 9.3.1), the performance
gain is really interresting:
"In remap mode at address 0x0000 0000, the CPU can access the external
memory via ICode bus instead of System bus which boosts up the
performance."
These are the dhrystone results with and without the remap enabled:
Default (SDRAM in 0xc0000000):
---------------------------------
Microseconds for one run through Dhrystone: 31.8
Dhrystones per Second: 31416.9
Remap (SDRAM in 0x0000000):
-----------------------------
Microseconds for one run through Dhrystone: 20.6
Dhrystones per Second: 48520.1
This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL
board, and also set the dma-range property as the other masters than the M4
CPU still see SDRAM in 0xc0000000.
Note that the Discovery board cannot benefit from this feature, since the
SDRAM is connected to Bank 2.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Add support for booting secondary CPUs on MT7623.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This adds basic chip support for Mediatek MT7623.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The change adds fixed voltage regulator for SD controller, ARM MMCI
controller driver uses it to control card power management.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Phytec PHY3250 board has GPIO controlled regulators for LCD and
backlight, add their descriptions to board DTS file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
LPC32xx interrupt controller has two cells, instead of zero
specify proper irq types for all consumers.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
If clock-frequency property is given, then it substitutes calculation
of supplying clock frequency from parent clock, this may break UART,
if parent clock is given and managed by common clock framework.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The change adds device node of LPC32xx USB clock controller and adds
clock properties to USB OHCI, USB device and I2C controller to USB phy
device nodes.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The change adds clock properties to all described peripheral devices,
clock ids are taken from dt-bindings/clock/lpc32xx-clock.h
Some existing drivers expect to get clock names, in those cases
clock-names are added as well.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part
of system control block (SCB). CPC is supplied by two external
oscillators and it manages core and most of peripheral clocks, the
change adds SCB and CPC descriptions to shared LPC32xx dtsi file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
NXP LPC32xx SoC has two external oscillators - one is mandatory and
always on 32768 Hz oscillator and one optional 10-20MHz oscillator,
which is practically always present on LPC32xx boards, because its
presence is needed to supply USB controller clock and by default it
supplies ARM and most of the peripheral clocks, LPC32xx User's Manual
references it as a main oscillator.
The change adds device nodes for both oscillators, frequency of
the main oscillator is selected to be 13MHz by default, this variant
is found on all LPC32xx reference boards.
The device nodes for external oscillators are needed to describe input
clocks of LPC32xx clock controller.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The tlv320aic3104 codec's master clock is coming from the SoC's CLKOUT2.
Select the SYS_CLK2 (via divider) as parent clock for CLKOUT2 and select
the same clock (SYS_CLK2) for McASP3 AHCLKX clock as well.
SYS_CLK2 is sourced from an external oscillator running 22.5792MHz and it
is coming in to the SoC via the X1_OSC1.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 3efda00129 ("ARM: dts: am335x: replace gpio-key,wakeup with
wakeup-source property") replaces all the legacy "gpio-key,wakeup" with
the unified "wakeup-source" property to prevent any further copy-paste
duplication.
However couple of use of these legacy property sneaked in during the
merge window. This patch replaces them too.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: linux-omap@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices
that use the Chrome OS EC keyboard matrix.
Signed-off-by: James Chao <james_chao@asus.com>
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.
Few dts files assign value "1" to gpio-key,wakeup and in one instance a
value "0" is assigned probably assuming it won't be enabled as a wakeup
source. Since the presence of the boolean property indicates it is
enabled, value of "0" have no value.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates:
- SCIF:
- Supports now 50, 75, 110, 1152000, 1500000, 2000000, and
4000000 bps,
- Perfect match for standard 50-460800, and 9216000 bps.
- More accurate 576000 bps.
- HSCIF:
- Supports now 50, 75, 110, 134, 150, and 200 bps,
- Perfect match for standard 50-460800, and 9216000 bps.
- More accurate 576000, 1152000, 3000000, 3500000, and 4000000
bps.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.
Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF and HSCIF device nodes.
This increases the range and accuracy of supported baud rates on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.
Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF and HSCIF device nodes.
This increases the range and accuracy of supported baud rates on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.
Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF and HSCIF device nodes.
This increases the range and accuracy of supported baud rates on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.
Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF and HSCIF device nodes.
This increases the range and accuracy of supported baud rates on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.
Add the two optional clock sources (S1 and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF device nodes.
This increases the range and accuracy of supported baud rates on SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.
Add the two optional clock sources (S1 and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF device nodes.
This increases the range and accuracy of supported baud rates on SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
