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ARM: dts: r8a7793: Add L2 cache-controller node

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Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2015-06-03 10:36:39 +02:00 committed by Simon Horman
parent 8ffe93a5b2
commit fdd0dbd8a2
1 changed files with 7 additions and 0 deletions
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7
arch/arm/boot/dts/r8a7793.dtsi
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@ -51,6 +51,7 @@
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
next-level-cache = <&L2_CA15>;
};
};
@ -73,6 +74,12 @@
};
};
L2_CA15: cache-controller@0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;