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Author	SHA1	Message	Date
Stefan	9d170cc8d3	Update README.md	2021-05-28 17:14:10 +00:00
Stefan	6c8c33ada0	Create LICENSE	2021-05-28 17:10:08 +00:00
Stefan	43000d5d2e	plz read me	2021-05-28 19:07:45 +02:00
Stefan	cf50244181	support for all necessary CSRs, privilege modes, traps, atomics ... ...plus some cleanups and debug improvements (single-step mode) All tests specified in test.sh now pass! This pretty much means full compliance with the RV32I base spec, M and A extensions, as well as correct machine, supervisor and user mode traps/switches. Next up is the SV32 MMU and external devices (UART, CLINT timer).	2021-05-28 19:02:11 +02:00
Stefan	64e2d0b45c	initial commit ... passes all RV32IM tests (run './test.sh all') instructions.txt is extracted from takahirox/riscv-rust	2021-05-28 15:10:51 +02:00