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A 32 bit RISC-V emulator made using a shader
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cf50244181
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Stefan cf50244181 support for all necessary CSRs, privilege modes, traps, atomics 
...plus some cleanups and debug improvements (single-step mode)

All tests specified in test.sh now pass! This pretty much means full
compliance with the RV32I base spec, M and A extensions, as well as correct
machine, supervisor and user mode traps/switches.

Next up is the SV32 MMU and external devices (UART, CLINT timer).
2021-05-28 19:02:11 +02:00
elfy initial commit 2021-05-28 15:10:51 +02:00
riscv-opcodes@7d1a0e3153 initial commit 2021-05-28 15:10:51 +02:00
riscv-rust@b4895fc56b support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
riscv-tests@09cfdaacd9 initial commit 2021-05-28 15:10:51 +02:00
src support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
.gitignore initial commit 2021-05-28 15:10:51 +02:00
.gitmodules support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
instructions.txt initial commit 2021-05-28 15:10:51 +02:00
Makefile initial commit 2021-05-28 15:10:51 +02:00
parse_ins.pl initial commit 2021-05-28 15:10:51 +02:00
test.sh support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00