9 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Stefan	30bd88dbbf	fix riscv-tests and add flag for exit call	2021-08-17 09:36:49 +02:00
Stefan	cb6d05178b	add MMU support (SV32) and fix a bunch of bugs	2021-08-17 09:31:46 +02:00
Stefan	7f47c7655d	Add rust_payload and fixes to allow running it as supervisor ... Note that the 'riscv32ima-unknown-none-elf' target is not available by default in rustc, you need a patched version. I'm also pretty sure just converting the ELF binary to raw using objdump messes with stack and heap addresses, but it seems to work fine for now.	2021-06-09 18:38:46 +02:00
Stefan	ed82c5487f	implement UART, CLINT, device tree, opensbi build ... ...plus some comfort improvements, more testing. This now successfully boots OpenSBI when built like specified in the Makefile!	2021-06-03 22:45:13 +02:00
Stefan	9d170cc8d3	Update README.md	2021-05-28 17:14:10 +00:00
Stefan	6c8c33ada0	Create LICENSE	2021-05-28 17:10:08 +00:00
Stefan	43000d5d2e	plz read me	2021-05-28 19:07:45 +02:00
Stefan	cf50244181	support for all necessary CSRs, privilege modes, traps, atomics ... ...plus some cleanups and debug improvements (single-step mode) All tests specified in test.sh now pass! This pretty much means full compliance with the RV32I base spec, M and A extensions, as well as correct machine, supervisor and user mode traps/switches. Next up is the SV32 MMU and external devices (UART, CLINT timer).	2021-05-28 19:02:11 +02:00
Stefan	64e2d0b45c	initial commit ... passes all RV32IM tests (run './test.sh all') instructions.txt is extracted from takahirox/riscv-rust	2021-05-28 15:10:51 +02:00