Commit Graph

1966 Commits

Author SHA1 Message Date
Masahiro Yamada
1950b04887 pinctrl: UniPhier: add UniPhier PH1-Pro5 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC.

Changes in v2:
  - sort groups and funcs alphabetically
  - add i2c pin-mux settings
  - sort members of platform_driver
  - change to tristate
  - add THIS_MODULE to pinctrl_desc
  - use module_platform_driver

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:40:08 +02:00
Masahiro Yamada
95372f9dc8 pinctrl: UniPhier: add UniPhier PH1-sLD8 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.

Changes in v2:
  - sort groups and funcs alphabetically
  - add i2c pin-mux settings
  - sort members of platform_driver
  - change to tristate
  - add THIS_MODULE to pinctrl_desc
  - use module_platform_driver

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:40:07 +02:00
Masahiro Yamada
b5cf4161ca pinctrl: UniPhier: add UniPhier PH1-Pro4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.

Changes in v2:
  - sort groups and funcs alphabetically
  - add i2c pin-mux settings
  - sort members of platform_driver
  - change to tristate
  - add THIS_MODULE to pinctrl_desc
  - use module_platform_driver

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:40:07 +02:00
Masahiro Yamada
edd95a4a95 pinctrl: UniPhier: add UniPhier PH1-LD4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.

Changes in v2:
  - sort groups and funcs alphabetically
  - add missing "emmc_dat8" group
  - add i2c pin-mux settings
  - sort members of platform_driver
  - change to tristate
  - add THIS_MODULE to pinctrl_desc
  - use module_platform_driver

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:40:06 +02:00
Masahiro Yamada
6e90889202 pinctrl: UniPhier: add UniPhier pinctrl core support
The core support for the pinctrl drivers for all the UniPhier SoCs.

Changes in v2:
  - drop vogus THIS_MODULE because this file is always built-in
  - drop vogus "include <linux/module.h> because this file is
    always built-in

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:38 +02:00
Bjorn Andersson
0e948042c4 pinctrl: qcom: spmi-mpp: Implement support for sink mode
The MPP supports three modes; digital, analog and sink mode. This patch
implements support for the latter.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:04 +02:00
Bjorn Andersson
eaaf5dd464 pinctrl: qcom: spmi-mpp: Introduce defines for MODE_CTL
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:04 +02:00
Bjorn Andersson
7682b3740d pinctrl: qcom: spmi-mpp: Fixes related to enable handling
There's currently no way to re-enable a mpp block once you've entered a state
that disables the state, this patch makes it possible to leave the
bias-high-impedance state.

Also read the enable state from the hardware on probe.

With this in place the is_enabled variable is accurately tracking the state of
the hardware and we can use that for the debug output as well.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:04 +02:00
Bjorn Andersson
ba5f94cd56 pinctrl: qcom: spmi-mpp: Transition to generic dt binding parser
Use the newly introduced extensible generic dt parser instead of rolling
our own dt parsing functions.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:03 +02:00
Masahiro Yamada
fb00de771b pinctrl: simplify of_pinctrl_get()
This commit does not change the logic at all.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:03 +02:00
Frank Li
9612327c1f pinctrl: imx: add i.mx6ul subdriver
Add i.MX6UL pinctrl driver support.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:02 +02:00
Laurent Pinchart
441f77dcf8 sh-pfc: r8a7791: remove non-existing GPIO pins
GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:02 +02:00
Laurent Pinchart
b5599df20f sh-pfc: r8a7790: remove non-existing GPIO pins
GPIO banks 1 and 2 are missing pins 30 and 31. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:01 +02:00
Mario Bambagini
13b8a68a9c added tabs instead of spaces
Tabs have been inserted instead of spaces to indent the code
correctly. Same error fixed four times.

Signed-off-by: Mario Bambagini <mario.bambagini@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:01 +02:00
Linus Torvalds
d5fb82137b Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
 "This contains:

   - a series of fixes for interrupt drivers to prevent a potential race
     when installing a chained interrupt handler

   - a fix for cpumask pointer misuse

   - a fix for using the wrong interrupt number from struct irq_data

   - removal of unused code and outdated comments

   - a few new helper functions which allow us to cleanup the interrupt
     handling code further in 4.3

   I decided against doing the cleanup at the end of this merge window
   and rather do the preparatory steps for 4.3, so we can run the final
   ABI change at the end of the 4.3 merge window with less risk"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits)
  ARM/LPC32xx: Use irq not hwirq for __irq_set_handler_locked()
  genirq: Implement irq_set_handler_locked()/irq_set_chip_handler_name_locked()
  genirq: Introduce helper irq_desc_get_irq()
  genirq: Remove irq_node()
  genirq: Clean up outdated comments related to include/linux/irqdesc.h
  mn10300: Fix incorrect use of irq_data->affinity
  MIPS/ralink: Fix race in installing chained IRQ handler
  MIPS/pci: Fix race in installing chained IRQ handler
  MIPS/ath25: Fix race in installing chained IRQ handler
  MIPS/ath25: Fix race in installing chained IRQ handler
  m68k/psc: Fix race in installing chained IRQ handler
  avr32/at32ap: Fix race in installing chained IRQ handler
  sh/intc: Fix race in installing chained IRQ handler
  sh/intc: Fix potential race in installing chained IRQ handler
  pinctrl/sun4i: Fix race in installing chained IRQ handler
  pinctrl/samsung: Fix race in installing chained IRQ handler
  pinctrl/samsung: Fix race in installing chained IRQ handler
  pinctrl/exynos: Fix race in installing chained IRQ handler
  pinctrl/st: Fix race in installing chained IRQ handler
  pinctrl/adi2: Fix race in installing chained IRQ handler
  ...
2015-07-01 15:19:35 -07:00
Linus Torvalds
f5dcb68086 ARM: SoC: driver updates for v4.2
Some of these are for drivers/soc, where we're now putting
 SoC-specific drivers these days. Some are for other driver subsystems
 where we have received acks from the appropriate maintainers.
 
 Some highlights:
 
 - simple-mfd: document DT bindings and misc updates
 - migrate mach-berlin to simple-mfd for clock, pinctrl and reset
 - memory: support for Tegra132 SoC
 - memory: introduce tegra EMC driver for scaling memory frequency
 - misc. updates for ARM CCI and CCN busses
 
  Conflicts:
 	arch/arm64/boot/dts/arm/juno-motherboard.dtsi
 
  Trivial add/add conflict with our dt branch.
  Resolution: take both sides.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVi4RRAAoJEFk3GJrT+8ZljIcQAIsqxM/o0drd90xTJ6ex9h0B
 RmqVLTDgesHmBacJ+SBsa9/ybFIM1uErByftc1dmKankEQVXW3wcH7keQnoStPT2
 zTEjadHgZ/ARYjV/oG5oohjfDZpO1kECVHL8O8RmcWxgzRB3az1IW2eD+dzrga/Y
 R7K6D8rDHMADIUmv0e0DzvQEbSUYdCx3rBND1qZznwZDP3NoivLkOG5MTraccLbQ
 ouCRoZtyNYD5Lxk+BHLBepnxAa0Ggc6IjEmiUv8fF2OYdu0OruMliT4rcAtOSmzg
 2Y7pP85h8u0CxbJDkOyc+2BELyKo7Hv97XtDNNbRYABTMXdskRIadXt4Sh4mwFtM
 nvlhB4ovbIX7noECJToEkSAgmStLSUwA3R6+DVdLbeQY4uSuXuTRhiWHMyQB6va9
 CdjJDk2RE0dZ77c5ZoUnUDtBe4cULU/n4agpYkKMf/HcpnqMUwZzP4KZbbPMBpgL
 0CVTt3YrEcjoU7g0SFHhOGPSgl4yIXKU2eHEscokyFYLrS5zRWepmUEmlSoaWn+W
 p7pJE65TvOGf2xbaWI+UBeK/3ZG7XAP8qUfhsi7NS4bV6oFCk/foqsWAuru0H7OW
 2Gk8fuF0qLgE1eFWQp8BHZ4IUeytoWbnGhhHXh8zH39SKAVncOiAGDNfuEP9CyXJ
 fZFfruYrnz2emOwj2v9m
 =02Gm
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Kevin Hilman:
 "Some of these are for drivers/soc, where we're now putting
  SoC-specific drivers these days.  Some are for other driver subsystems
  where we have received acks from the appropriate maintainers.

  Some highlights:

   - simple-mfd: document DT bindings and misc updates
   - migrate mach-berlin to simple-mfd for clock, pinctrl and reset
   - memory: support for Tegra132 SoC
   - memory: introduce tegra EMC driver for scaling memory frequency
   - misc. updates for ARM CCI and CCN busses"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  drivers: soc: sunxi: Introduce SoC driver to map SRAMs
  arm-cci: Add aliases for PMU events
  arm-cci: Add CCI-500 PMU support
  arm-cci: Sanitise CCI400 PMU driver specific code
  arm-cci: Abstract handling for CCI events
  arm-cci: Abstract out the PMU counter details
  arm-cci: Cleanup PMU driver code
  arm-cci: Do not enable CCI-400 PMU by default
  firmware: qcom: scm: Add HDCP Support
  ARM: berlin: add an ADC node for the BG2Q
  ARM: berlin: remove useless chip and system ctrl compatibles
  clk: berlin: drop direct of_iomap of nodes reg property
  ARM: berlin: move BG2Q clock node
  ARM: berlin: move BG2CD clock node
  ARM: berlin: move BG2 clock node
  clk: berlin: prepare simple-mfd conversion
  pinctrl: berlin: drop SoC stub provided regmap
  ARM: berlin: move pinctrl to simple-mfd nodes
  pinctrl: berlin: prepare to use regmap provided by syscon
  reset: berlin: drop arch_initcall initialization
  ...
2015-06-26 11:54:29 -07:00
Thomas Gleixner
ef80e87d20 pinctrl/sun4i: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Fan Wu <fwu@marvell.com>
Cc: abdoulaye berthe <berthe.ab@gmail.com>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
2015-06-25 11:57:17 +02:00
Thomas Gleixner
623a650ebc pinctrl/samsung: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
2015-06-25 11:57:15 +02:00
Thomas Gleixner
0cfc45cfdf pinctrl/samsung: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
2015-06-25 11:57:13 +02:00
Thomas Gleixner
bb56fc3577 pinctrl/exynos: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
2015-06-25 11:57:11 +02:00
Thomas Gleixner
1b11b0cb79 pinctrl/st: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
Cc: Maxime Coquelin <maxime.coquelin@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kernel@stlinux.com
Cc: linux-gpio@vger.kernel.org
2015-06-25 11:57:09 +02:00
Thomas Gleixner
bb6d6dd386 pinctrl/adi2: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
2015-06-25 11:57:07 +02:00
Thomas Gleixner
1e10592136 pinctrl/mediatek: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Cc: Axel Lin <axel.lin@ingics.com>
Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
Cc: Maoguang Meng <maoguang.meng@mediatek.com>
Cc: Colin Ian King <colin.king@canonical.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
2015-06-25 11:57:04 +02:00
Linus Torvalds
93a4b1b946 Here is the bulk of pin control changes for the v4.2 series:
- Core functionality:
   - Enable exclusive pin ownership: it is possible to flag a pin
     controller so that GPIO and other functions cannot use a single
     pin simultaneously.
 
 - New drivers:
   - NXP LPC18xx System Control Unit pin controller
   - Imagination Pistachio SoC pin controller
 
 - New subdrivers:
   - Freescale i.MX7d SoC
   - Intel Sunrisepoint-H PCH
   - Renesas PFC R8A7793
   - Renesas PFC R8A7794
   - Mediatek MT6397, MT8127
   - SiRF Atlas 7
   - Allwinner A33
   - Qualcomm MSM8660
   - Marvell Armada 395
   - Rockchip RK3368
 
 - Cleanups:
   - A big cleanup of the Marvell MVEBU driver rectifying it to
     correspond to reality
   - Drop platform device probing from the SH PFC driver, we are now a
     DT only shop for SuperH
   - Drop obsolte multi-platform check for SH PFC
   - Various janitorial: constification, grammar etc
 
 - Improvements:
   - The AT91 GPIO portions now supports the set_multiple() feature
   - Split out SPI pins on the Xilinx Zynq
   - Support DTs without specific function nodes in the i.MX driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVin37AAoJEEEQszewGV1zIlQP/i6+C47z3OV67hYAOmlGoynl
 wsdTFbyp+GIPl3N1r0lRzxOfQsuc9t93iDMrC5ssN9VFaj8MgH/j3XKWf5A55iVn
 u7nNQzIFjzTwl58/Pu4oM+d9l5i26o44teFKh3xI4aup4AFed3+lDkQtRipgo29c
 V4y+6SaQxQ46e2qaOAM20gEagm2a8EvChn1Zo/HLQnnmZcKBxgObJna7iTZWm+fN
 LzyBWtczFYPxfQ9IqYzklyeou4ohfrcHzqN71IEtmGMXxob+i04QS9FQXaPitgBG
 UORjwFVh8690n3ETQobjLrylOF5F/3+RdCGqanYOLgaJ0aix4+EByLz9FbxLPnJk
 4Utijk2SKxLUb3dXZIfpwKtmPmvLJkFqwSazN5WDIg9Rjqz/H1p9UTWP0cfPRwJa
 9INDZeK833kjYdtK6UMBpuNFkgGtpKTlhMX/cI78KYsEwVgK8r69b7uNr+2OUMgh
 4i7dbHgb5/NpHlUlacVPTBvXf7C1iQ//vqh0Oc20lp/mAY1tVGuYRHno6QVyRtfS
 DmCNPtbAgCa9FmP/t5NA8a3wana2ObTT2NCNMGEue7tJxVX4YaLpwIAEnUSHSJOQ
 seI8HT2M1yEiSes9V+OuigHt3pKk68fMe0ZqDkovcd4QBlub6WTAPXWrXpbHtBCo
 k+hT8TlDYaDbQkNDzXtg
 =UyKm
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Here is the bulk of pin control changes for the v4.2 series: Quite a
  lot of new SoC subdrivers and two new main drivers this time, apart
  from that business as usual.

  Details:

  Core functionality:
   - Enable exclusive pin ownership: it is possible to flag a pin
     controller so that GPIO and other functions cannot use a single pin
     simultaneously.

  New drivers:
   - NXP LPC18xx System Control Unit pin controller
   - Imagination Pistachio SoC pin controller

  New subdrivers:
   - Freescale i.MX7d SoC
   - Intel Sunrisepoint-H PCH
   - Renesas PFC R8A7793
   - Renesas PFC R8A7794
   - Mediatek MT6397, MT8127
   - SiRF Atlas 7
   - Allwinner A33
   - Qualcomm MSM8660
   - Marvell Armada 395
   - Rockchip RK3368

  Cleanups:
   - A big cleanup of the Marvell MVEBU driver rectifying it to
     correspond to reality
   - Drop platform device probing from the SH PFC driver, we are now a
     DT only shop for SuperH
   - Drop obsolte multi-platform check for SH PFC
   - Various janitorial: constification, grammar etc

  Improvements:
   - The AT91 GPIO portions now supports the set_multiple() feature
   - Split out SPI pins on the Xilinx Zynq
   - Support DTs without specific function nodes in the i.MX driver"

* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: rockchip: add support for the rk3368
  pinctrl: rockchip: generalize perpin driver-strength setting
  pinctrl: sh-pfc: r8a7794: add SDHI pin groups
  pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
  pinctrl: sh-pfc: add R8A7794 PFC support
  pinctrl: make pinctrl_register() return proper error code
  pinctrl: mvebu: armada-39x: add support for Armada 395 variant
  pinctrl: mvebu: armada-39x: add missing SATA functions
  pinctrl: mvebu: armada-39x: add missing PCIe functions
  pinctrl: mvebu: armada-38x: add ptp functions
  pinctrl: mvebu: armada-38x: add ua1 functions
  pinctrl: mvebu: armada-38x: add nand functions
  pinctrl: mvebu: armada-38x: add sata functions
  pinctrl: mvebu: armada-xp: add dram functions
  pinctrl: mvebu: armada-xp: add nand rb function
  pinctrl: mvebu: armada-xp: add spi1 function
  pinctrl: mvebu: armada-39x: normalize ref clock naming
  pinctrl: mvebu: armada-xp: rename spi to spi0
  pinctrl: mvebu: armada-370: align spi1 clock pin naming
  pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
  ...
2015-06-24 19:21:02 -07:00
Heiko Stübner
daecdc6696 pinctrl: rockchip: add support for the rk3368
The rk3368 is the first ARM64 soc from Rockchip, but seems to share most
peripherals with the ARM32 soc, including the pinctrl functionality.
The only notable difference is - as with every Rockchip soc - that the
offsets in the General Register Files moved around and a split of the pmu
section of the rk3288 into pmu and pmugrf (pmu general register files)
sections. The pinctrl driver of course only needs the pmugrf registers
for controlling the pin settings.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-17 10:21:02 +02:00
Heiko Stübner
ef17f69f5b pinctrl: rockchip: generalize perpin driver-strength setting
The upcoming support for the RK3368 ARM64 SoC also supports perpin
drive strength settings (at different register positions), so generalize
the register and offset calculation to easily support this one too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-17 10:20:00 +02:00
Shinobu Uehara
7ac91bda80 pinctrl: sh-pfc: r8a7794: add SDHI pin groups
Add SDHI0/1/2 pin groups to R8A7794 PFC driver.

Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
[Sergei: renamed SD data pins to match the driver, rebased, renamed, added
changelog.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-16 10:55:09 +02:00
Shinobu Uehara
f1f74b640c pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
Add MMCIF pin groups to R8A7794 PFC driver.

Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
[Sergei: rebased, renamed, added changelog.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-16 10:54:01 +02:00
Hisashi Nakamura
43c4436e2f pinctrl: sh-pfc: add R8A7794 PFC support
Add PFC support for  the  R8A7794 SoC  including pin groups for some
on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF...

Sergei: squashed together several patches, fixed the MLB_CLK typo,
added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin
group names, removed stray new line and fixed typos in the  comments
in the pinmux_config_regs[] initializer, removed the platform device
ID, took into account limited number of signals in the GPIO1/5/6
controllers, added reasonable and removed unreasonable
copyrights, modified the bindings document, renamed, added changelog.

Changes in version 5:
- resolved rejects, refreshed the patch;
- added Laurent Pinchart's ACK.

Changes in version 4:
- reused the PORT_GP_26() macro to #define PORT_GP_28().

Changes in version 3:
- removed the platform device ID;
- added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the
  CPU_ALL_PORT() macro.

Changes in version 2:
- rebased the patch.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-16 10:53:20 +02:00
Masahiro Yamada
323de9efdf pinctrl: make pinctrl_register() return proper error code
Currently, pinctrl_register() just returns NULL on error, so the
callers can not know the exact reason of the failure.

Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
-ENOMEM on error of pinctrl_register(), although the error code
might be different from the real cause of the error.

This commit reworks pinctrl_register() to return the appropriate
error code and modifies all of the pinctrl drivers to use IS_ERR()
for the error checking and PTR_ERR() for getting the error code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Ray Jui <rjui@broadcom.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:49:52 +02:00
Thomas Petazzoni
e73ac02dc1 pinctrl: mvebu: armada-39x: add support for Armada 395 variant
The Armada 39x SoC family has grown a new variant, the Armada 395,
which sits between the Armada 390 and Armada 398 in terms of
features. This commit adds support for this additional variant to the
Armada 39x pinctrl driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:36:34 +02:00
Thomas Petazzoni
6afc0c0f5b pinctrl: mvebu: armada-39x: add missing SATA functions
The latest version of the Armada 39x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:34:56 +02:00
Thomas Petazzoni
c0adb877a2 pinctrl: mvebu: armada-39x: add missing PCIe functions
The latest version of the Armada 39x datasheet documents several new
PCIe related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:31:39 +02:00
Thomas Petazzoni
f9dbbe011c pinctrl: mvebu: armada-38x: add ptp functions
The latest version of the Armada 38x datasheet documents several new
PTP related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:30:44 +02:00
Thomas Petazzoni
f7ad5b29ce pinctrl: mvebu: armada-38x: add ua1 functions
The latest version of the Armada 38x datasheet documents several new
UART1 related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:29:54 +02:00
Thomas Petazzoni
9ce28fccb0 pinctrl: mvebu: armada-38x: add nand functions
The latest version of the Armada 38x datasheet documents several new
NAND related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:24:57 +02:00
Thomas Petazzoni
503cfd9f8a pinctrl: mvebu: armada-38x: add sata functions
The latest version of the Armada 38x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:18:27 +02:00
Thomas Petazzoni
b19bf37976 pinctrl: mvebu: armada-xp: add dram functions
The latest Armada XP datasheet documents several new DRAM related
functions on various MPPs. This commit adds the description of these
new functions in the Armada XP pinctrl driver and its DT binding
documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:11:50 +02:00
Thomas Petazzoni
fb53b61d77 pinctrl: mvebu: armada-xp: add nand rb function
The latest version of the Armada XP datasheet documents a new
NAND-related MPP function on MPP48, for which this commit adds
support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:11:01 +02:00
Thomas Petazzoni
88b355f1e4 pinctrl: mvebu: armada-xp: add spi1 function
The latest Armada XP datasheet documents that some of the MPP pins can
be used to access the second SPI bus, labelled 'spi1'. This commit
adds the corresponding pins in the pinctrl driver and its DT binding
documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:09:49 +02:00
Thomas Petazzoni
691a82161b pinctrl: mvebu: armada-39x: normalize ref clock naming
This commit normalizes the subnames of the reference clock MPP pins in
the Armada 39x pinctrl driver to match with the name used on other
SoCs.

Since only the subnames are changed, DT backward compatibility is not
affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:08:44 +02:00
Thomas Petazzoni
50a7d13d24 pinctrl: mvebu: armada-xp: rename spi to spi0
After updating to the latest Armada XP datasheet, we discovered that
there is a second SPI bus accessible from the MPP pins, called 'spi1'.

In order to be consistent with other SoCs having two SPI busses, this
commit renames the functions of the first SPI bus to 'spi0' instead of
just 'spi'.

This commit obviously breaks the DT backward compatibility for the
people using the "spi" function name in their Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:00:54 +02:00
Thomas Petazzoni
9e05db29e2 pinctrl: mvebu: armada-370: align spi1 clock pin naming
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the
'sck' subname and not 'clk', so this commit adjusts the code and
documentation accordingly.

Since this commit only changes the subname, DT backward compatibility
is not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 13:59:40 +02:00
Thomas Petazzoni
bfacb56694 pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
For consistency with the datasheet, this commit renames the VDD
function of the MPP4 pin.

While this changes the DT compatibility, it is not considered to be a
problem since this pin is unlikely to be used for anything but
debugging purposes.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 13:57:28 +02:00
Thomas Petazzoni
a361cbc575 pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins
This commit normalizes the naming of the Ethernet txclkout pin to be
the same accross Marvell SoCs. It is worth mentioning that the DT
binding documentation of the Armada XP was wrong for MPP12: it said
the function was ge1(txd0), while it is in fact ge1(txclkout). It is
however not really a fix worth sending to stable since it does not
change the behavior, and the driver itself was correct.

Since only the subnames are changed, DT backward compatibility is not
affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 13:50:17 +02:00
Thomas Petazzoni
f32f01e1ba pinctrl: mvebu: armada-{370,375}: normalize audio pins
This commit aligns the naming of the audio 'lrclk' pin accross Marvell
SoCs.

Since only the subname is changed, the DT backward compatibility is
not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 13:43:52 +02:00
Thomas Petazzoni
d4974c16ed pinctrl: mvebu: armada-{370,375}: normalize PCIe pins
This commit normalizes the naming of PCIe pins to use 'rstout' instead
of 'rstoutn' or 'rst-out'.

Since only the subnames are changed, DT compatibility is not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 13:40:27 +02:00
Thomas Petazzoni
dae5597f25 pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins
This commit normalizes the naming of the TDM pins accross the
different Marvell SoCs. Mainly it consists in:

 * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn'
   becomes 'rst'

 * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x.

 * Change the main name 'tdm-1' to 'tdm' for one of the pins of the
   Armada XP

The last two changes affect DT compatibility, but since the TDM
interface is nowhere near being supported in mainline, it should not
be considered to be a serious problem at this point.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 13:35:33 +02:00
Thomas Petazzoni
5cc0de1faf pinctrl: mvebu: armada-39x: align NAND pin naming
All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.

It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.

While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 11:11:39 +02:00
Thomas Petazzoni
7bd6a26db6 pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins
This commit modifies the definition of the Device Bus interface pins
to be consistent accross SoCs. Especially, it removes the 'n'
indicators that we don't encode in the subnames of pins:

   'dev(wen0)' becomes 'dev(we0)'
   'dev(wen1)' becomes 'dev(we1)'
   'dev(oen)' becomes 'dev(oe)'
   etc.

In addition, it fixes the Armada 375 DT binding documentation, which
forgot to document the 'dev' function for MPP46, MPP57 and MPP63.

Since only the subnames are changed, this commit does not affect DT
compatibility.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 11:10:34 +02:00
Thomas Petazzoni
ddf3f19e21 pinctrl: mvebu: armada-39x: normalize SDIO pin naming
In order to be consistent with the datasheet and some other SoCs, this
commit renames the SDIO pins of the Armada 39x from "sd" to "sd0".

While this changes the DT binding, this is not a problem since Armada
39x is a brand new SoC which isn't used in production yet (so now is
the right time to fix such things).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 11:09:33 +02:00
Thomas Petazzoni
52f83174b3 pinctrl: mvebu: armada-39x: normalize SATA present functionality naming
This commit makes the naming of SATA related MPP functions consistent
accross SoCs by adjusting the Armada 39x definition to use "prsnt"
instead of "present".

Since only the subnames are changed, the DT binding is not modified at
all.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 11:08:37 +02:00
Thomas Petazzoni
100dc5d840 pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions
This commit makes the dram functions naming (both the name and
subname) consistent accross SoC, by using:

  dram(vttctrl)
  dram(deccerr)

in all Marvell SoCs.

Due to the change to the name, it changes the DT binding, but these
functions are not used by any in-tree Device Tree file, and are very
unlikely to be used by anyone.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 11:07:36 +02:00
Thomas Petazzoni
9540cf5344 pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames
The subnames are purely informative, but it's nicer when they match
accross SoCs. This commit adjusts the Armada 375, Armada 38x and
Armada 39x MPP definitions so that the subnames of the PTP pins match
the ones used on Armada XP and Kirkwood.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:58:24 +02:00
Thomas Petazzoni
7c580311a2 pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and
a second one of 27 GPIOs. However, since there is a total of 60 MPP
pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v4.1+
Fixes: ee086577ab ("pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:57:52 +02:00
Thomas Petazzoni
27e7cd0165 pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and
a second one of 27 GPIOs. However, since there is a total of 60 MPP
pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ca6d9a084b ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:57:02 +02:00
Thomas Petazzoni
d538990ee1 pinctrl: mvebu: armada-375: remove incorrect space in pin description
There was an incorrect space in the definition of the function of one
pin in the Armada 375 pinctrl driver, which this commit fixes.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:56:28 +02:00
Thomas Petazzoni
ea78b9511a pinctrl: mvebu: armada-xp: fix functions of MPP48
There was a mistake in the definition of the functions for MPP48 on
Marvell Armada XP. The second function is dev(clkout), and not tclk.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:55:59 +02:00
Thomas Petazzoni
80b3d04fea pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
The latest version of the Armada XP datasheet no longer documents the
VDD cpu_pd functions, which might indicate they are not working and/or
not supported. This commit ensures the pinctrl driver matches the
datasheet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:55:01 +02:00
Thomas Petazzoni
bc99357f36 pinctrl: mvebu: armada-xp: remove non-existing NAND pins
After updating to a more recent version of the Armada XP datasheet, we
realized that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:54:30 +02:00
Thomas Petazzoni
e5447d2609 pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
After updating to a more recent version of the Armada 375, we realized
that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:53:34 +02:00
Thomas Petazzoni
438881dfdd pinctrl: mvebu: armada-370: fix spi0 pin description
Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly
named "spi0-1" instead of just "spi0". This commit fixes that.

This DT binding change does not affect any of the in-tree users.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 5f597bb2be ("pinctrl: mvebu: add pinctrl driver for Armada 370")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:51:45 +02:00
Thomas Petazzoni
331642fbf2 pinctrl: mvebu: armada-38x: fix PCIe functions
A new revision of the Marvell Armada 38x hardware datasheet unveiled
that the definition of some of the PCIe functions were not
correct. This commit fixes the pinctrl driver accordingly.

Some PCIe functions simply do not exist, some of the PCIe functions in
fact were corresponding to other functions, and some PCIe functions
have been added.

Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related:
this function is in fact implemented on MPP43, instead of a PCIe
function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ca6d9a084b ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:50:36 +02:00
Ludovic Desroches
9d7ebbbf22 pinctrl: don't print unavailable function groups
There is no reason to try to print groups associated to a function if
get_function_groups returns an error. Moreover, it can lead to a NULL
pointer dereference error.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:44:05 +02:00
Bjorn Andersson
6955e6b4f3 pinctrl: qcom: Add MSM8660 pinctrl definitions
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 10:18:38 +02:00
Antoine Tenart
2e89f4c3d9 pinctrl: berlin: comment the spi functions
Add comments for the SPI functions, to distinguish CLK, SDI, SDO and
C{0,1,2,3}n.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 09:17:43 +02:00
Antoine Tenart
bcb5f5b4f4 pinctrl: berlin: fix spi1 SS0n function name
Rename function ss0 to spi1 to be consistent with the other Berlin
function names.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 09:15:27 +02:00
Vishnu Patekar
7164873e7c pinctrl: sunxi: Add allwinner A33 PIO controller support
A33 PIO has 7 ports which starts from PB and has two interrupt ports.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-04 10:32:11 +02:00
Fabio Estevam
44a074ffe0 pinctrl: samsung: Fix the pointer in PTR_ERR()
PTR_ERR should access the value just tested by IS_ERR

The semantic patch that makes this change is available
in scripts/coccinelle/tests/odd_ptr_err.cocci.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-04 10:14:35 +02:00
Fabio Estevam
3944e7b78c pinctrl: Remove .owner field
platform_driver does not need to set the owner field, as it will be
populated by the driver core, so just remove it.

The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-04 10:12:42 +02:00
Masahiro Yamada
7e9236ff3d pinctrl: fix confusing debug message in pinctrl_register_map()
There are two types for pinctrl maps: pinmux and pinconfig
This debug message shows the number of maps of both types.
The string "pinmux map" is not precise.  Let's say "pinctrl map"
instead.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[also fixed %d -> %u]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-02 13:32:20 +02:00
Masahiro Yamada
4fd24e220e pinctrl: zynq: add static const to zynq_pctrl_groups
This array is only referenced in this file and never updated.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-02 13:30:33 +02:00
Masahiro Yamada
c0b8555c15 pinctrl: zynq: add static to zynq_pins
This array is only referenced in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-02 13:29:35 +02:00
Hongzhou Yang
fc63d854cb pinctrl: mediatek: Fix pinctrl register irq fail bug.
Since mt6397 is no need to support interrupt controller,
I judged "interrupt-controller" property to skip it last patch.
But the if judgement should on the contrary, this is a bug.

And find of_property_read_bool is better for this case.
So using of_property_read_bool instead of of_find_property.

Also fix bug of misuse pointer.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Reviewed-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-02 11:08:03 +02:00
Hongzhou Yang
257e961ddd pinctrl: mediatek: Fix bug of ies/smt setting for mt8173.
Add ies/smt support for MSDC3.
Also fix ies bug for pin 106 and 107.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-02 11:06:31 +02:00
Geert Uytterhoeven
5b441eba3a pinctrl: Spelling s/reseved/reserved/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01 15:49:53 +02:00
Masahiro Yamada
5cf021d520 pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL
The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830,
0xf8000834, respectively.

Each offset address must be prefixed with 0x.

Fixes: add958cee9 "pinctrl: Add driver for Zynq"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01 15:00:02 +02:00
Masahiro Yamada
4f652cea02 pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro
The offset to the mux register is missing.

Fixes: add958cee9 "pinctrl: Add driver for Zynq"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01 14:59:24 +02:00
Jon Hunter
8480c2e7b0 pinctrl: tegra-xusb: Fix allocation of pins
Commit e5b3b2d9ed ("pinctrl: allows not to define the get_group_pins
operation") allows pin controllers not to register the get_group_pins()
function. However, a side-effect of not registering this function is
that pins are not allocated and potentially multiple devices could
attempt to configure the same pins [1]. Although this problem exists in
the pinctrl core, because only a few devices are impacted by this, fix
this for tegra-xusb by adding the get_group_pins() function.

Please note that in addition to adding the get_group_pins() functions
the pins/lanes for the tegra-xusb also need to be registered when
calling pinctrl_register(). This also allows the current pinmux state
to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad
controller.

[1] http://www.spinics.net/lists/linux-gpio/msg05810.html

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01 13:57:05 +02:00
Jon Hunter
1133c6379c pinctrl: tegra-xusb: Remove unused structure
The structure tegra_xusb_padctl_group is defined but never used and so
remove this.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01 13:55:45 +02:00
Linus Walleij
8150885503 pinctrl: improve debugfs for strict controllers
If we know we are using a strict pin controller (one that cannot
mix device functions+group use and GPIO) we can be a bit more
specific in debugfs, just print either device-function-group
or GPIO consumer for the pin. Let's do that to be helpful.

Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-28 10:14:21 +02:00
Linus Walleij
a2202a4c76 pinctrl: mediatek: add OF dependency to MT6397
X86_64 allmodconfig screams like so:
warning: (PINCTRL_MT6397) selects PINCTRL_MTK_COMMON
which has unmet direct dependencies
(PINCTRL && (ARCH_MEDIATEK || COMPILE_TEST) && OF)

So add OF to dependencies to shut up this warning.

Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-20 09:11:23 +02:00
Yoshihiro Shimoda
f9784298e2 pinctrl: sh-pfc: r8a7791: Add PWM pin groups and functions
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 16:01:50 +02:00
Wei Chen
f936779329 pinctrl: sirf: add sirf atlas7 pinctrl and gpio support
The Pinctrl module (ioc) controls the Pad's function select
(each pad can have 8 functions), Pad's Drive Strength, Pad's
Pull Select and Pad's Input Disable status.

The ioc has two modules, ioc_top & ioc_rtc. Both of these two
modules have function select/clear, Pull select and Drive
Strength registers. But only ioc_rtc has input-disable
registers. The Pads on ioc_top have to access ioc_rtc to set
their input-disable status and intpu-disable-value.

So have to use one ioc driver instance to drive these two
ioc modules at the same time, and each ioc module will be
treat as one bank on the "IOC Device".

The GPIO Controller controls the GPIO status if the Pad has
been config as GPIO by Pinctrl already. Includes the GPIO
Input/output, Interrupt type, Interrupt Status, and Set/Get
Values.
The GPIO pull up/down are controlled by Pinctrl.

There are 7 GPIO Groups and splited into 3 MACROs in atlas7.
The GPIO Groups in one MACRO share one GPIO controllers, each
GPIO Group are treated as one GPIO bank.

For example:
In VDIFM macro, there is one GPIO Controller, it has 3 banks
to control 3 gpio groups. Its gpio name space is from 0 to 95.

The Device Tree can be written as following:

gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>,
<&pinctrl 64 0 0>;

gpio-ranges-group-names = "gnss_gpio_grp",
"lcd_vip_gpio_grp",
"sdio_i2s_gpio_grp";

bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp".
bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp".
bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp".

Signed-off-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 16:01:30 +02:00
Masahiro Yamada
5ceb41ad1d pinctrl: zynq: add static to platform_driver remove callback
This function is only referenced in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 16:01:30 +02:00
Yoshihiro Shimoda
5c89c15b74 pinctrl: sh-pfc: r8a7790: Add PWM pin groups and functions
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 16:01:25 +02:00
Carlo Caione
984cffdeae pinctrl: Fix gpio/pin mapping for Meson8b
The num_pins field in the struct meson_domain_data must include also the
missing pins in the Meson8b SoC, otherwise the GPIO <-> pin mapping is
broken on this platform. Avoid also the dinamic allocation for GPIOs.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:40:52 +02:00
Yingjoe Chen
6acdee8c13 pinctrl: mediatek: add pinctrl/GPIO/EINT driver for mt8127
MT8127 pinctrl/eint are similar to mt8135 and mt8173, add
support for mt8127 using mediatek common pinctrl driver.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:17:45 +02:00
Hongzhou Yang
fc59e66c42 pinctrl: mediatek: Add Pinctrl/GPIO driver for mt6397.
Add mt6397 support using mediatek common pinctrl driver.

mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip.
Pinctrl/GPIO driver should obtain regmap from PMIC,
so adding this support to common code.

Also, mt6397 is no need to support interrupt controller,
so changing common code to skip it.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:16:17 +02:00
Hongzhou Yang
25d76b21b1 pinctrl: mediatek: add ies/smt control to common code.
Input enable and smt setting have different register,
modify code to fix it.

Several mediatek soc use similar input enable/smt setting
procedure as mt8173, some soc use generic input enable/smt
setting, some soc has no input enable/smt setting. Adding
common code to handle all those cases, so future soc driver
can use it.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:15:03 +02:00
Yingjoe Chen
e73fe2713f pinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg common code
Several mediatek soc use similar pull setting procedure as mt8173,
the pupd enable and resistance setting are in the same register.
Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set
in mt8173 to handle this case, so future soc driver can use it.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:13:51 +02:00
Yingjoe Chen
4b9b526846 pinctrl: mediatek: data struct optimize and remove unused member
struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset
and mtk_pinctrl_devdata.chip_type are never used in code.
Remove them.

Some per-pin data are using int for pin number and offsets.
Change to short and rearrange to reduce const data size.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:12:54 +02:00
Joachim Eastwood
16a4851d8c pinctrl: lpc18xx: add the missing group function map
Add the required group function map and fill it at probe using
the pin capabilities information already present in the driver.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 11:09:31 +02:00
Ray Jui
75e9143927 pinctrl: cygnus: fixed incorrect GPIO-pin mapping
This patch fixes an incorrect GPIO-to-pin mapping in the Cygnus GPIO
driver

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 10:45:11 +02:00
Ray Jui
6dce6d2495 pinctrl: cygnus: fixed typo in the gpio driver
Fixed a small typo in the Cygnus GPIO driver

Signed-off-by: Jason Uy <jasonuy@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19 10:43:23 +02:00
Antoine Tenart
f90bec209c pinctrl: berlin: drop SoC stub provided regmap
With convertsion to simple-mfd sub-nodes, drop the regmap registration
by SoC stubs.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2015-05-18 18:10:08 +02:00
Antoine Tenart
f52bf55cba pinctrl: berlin: prepare to use regmap provided by syscon
The Berlin pin controller nodes will be simple-mfd probed sub-nodes of
soc-controller and system-controller nodes. The register bank is managed
by syscon, which provides a regmap.

Prepare to get the regmap from syscon parent node instead of SoC stub
provided regmap.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2015-05-18 17:52:46 +02:00
Mika Westerberg
e6c906dedb pinctrl: cherryview: Read triggering type from HW if not set when requested
If a driver does not set interrupt triggering type when it calls
request_irq(), it means use the pin as the hardware/firmware has
configured it. There are some drivers doing this. One example is
drivers/input/serio/i8042.c that requests the interrupt like:

	error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
			    "i8042", i8042_platform_device);

It assumes the interrupt is already properly configured. This is true in
case of interrupts connected to the IO-APIC. However, some Intel
Braswell/Cherryview based machines use a GPIO here instead for the internal
keyboard controller.

This is a problem because even if the pin/interrupt is properly configured,
the irqchip ->irq_set_type() will never be called as the triggering flags
are 0. Because of that we do not have correct interrupt flow handler set
for the interrupt.

Fix this by adding a custom ->irq_startup() that checks if the interrupt
has no triggering type set and in that case read the type directly from the
hardware and install correct flow handler along with the mapping.

Reported-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reported-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:54:32 +02:00
Andrew Bresticker
cefc03e599 pinctrl: Add Pistachio SoC pin control driver
Add a driver for the pin controller present on the IMG Pistachio SoC.
This driver provides pinmux and pinconfig operations as well as GPIO
and IRQ chips for the GPIO banks.

Changes from v4:
 - Switched to using gpiochip_add_pin_range().
 - Fixed up Kconfig entry.
Changes from v3:
 - Addressed review comments from Ezequiel.
Changes from v2:
 - Removed module stuff which would be compiled out.
Changes from v1:
 - Addressed review comments from Linus.
 - Changed compatible string to "img,pistachio-system-pinctrl".
 - Look for GPIO sub-nodes by name.
 - A couple of bug fixes.

Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:19:41 +02:00
Joachim Eastwood
403fbdee47 pinctrl: lpc18xx: create pin cap lookup helper
Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based
on the pin number. Create a common helper function that both
functions can use that also handles the case where no pin number is
found in the pins array.

This also fixes a small bug in pconf_get_pin where pconf_get_i2c0
would use the pins array index rather than the pin number.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:48 +02:00
Geert Uytterhoeven
e8e36d2f18 pinctrl: sh-pfc: r8a73a4: Remove obsolete multi-platform check
As of commit 9d07d414d4 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic ARM
multi-platform builds.  Hence CONFIG_ARCH_MULTIPLATFORM is always set,
and the check can be removed.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:44 +02:00
Ulrich Hecht
cb0ba73d09 pinctrl: sh-pfc: Enable building of r8a7793 PFC support
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:43 +02:00
Ulrich Hecht
19e1e98fbf pinctrl: sh-pfc: Add r8a7793 support
Regarding pin control, r8a7791 and r8a7793 are identical, so it is
sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:42 +02:00
Geert Uytterhoeven
992161965f pinctrl: sh-pfc: r8a7740: Fix typo SCIFAB in comment
The last serial port is called "SCIFB", not "SCIFAB".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:42 +02:00
Mika Westerberg
551fa5801e pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support
Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller
Hub). It has slightly different pin configuration compared to the LP
version. This patch adds support for Sunrisepoint-H to the existing
pinctrl-sunrisepoint.c driver.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:41 +02:00
Geert Uytterhoeven
b217e4385d pinctrl: Grammar s/used in as/used as/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:41 +02:00
Geert Uytterhoeven
592be8d3c1 pinctrl: sh-pfc: Remove r8a73a4 platform_device_id entry
As of commit 9d07d414d4 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic DT-only ARM
multi-platform builds.  The driver doesn't need to match platform
devices by name anymore, hence remove the corresponding
platform_device_id entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:17:40 +02:00
Linus Torvalds
41c64bb19c These are some GPIO fixes for the v4.1 series:
- Fix a memory leak for GPIO hotplug.
 
 - Fix a signedness bug in the ACPI GPIO pin validation.
 
 - Driver fixes: Qualcomm SPMI and OMAP MPUIO IRQ issues.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVTGkQAAoJEEEQszewGV1zDjcQAJLc5C0k53nc4oxA91B1Ldpn
 QbwKLCVrX7ex4zye4Qisw0vqPB1yZJD9yfuerNYQUJpoXFwHLGKr3925Q5NUCsRz
 7d1zFfgfw+hdHXAZv02uOmZ+xx7E1tDl95CBU0GpkFo8yJ6gms+X5TonqWRLAwP4
 2vIYjZdQLFpLI73lQ5eR3jYcMlrwCgGnPYeG5gR5Fp1dUmrpaZckhidoj7j1bxNk
 mCrv+xoGguIv/t9sUNXSusD4j1Rr0G/YX2RxbrWjTTSCCyuIV/b4MmwuTuD853sl
 I2AGiftGZOuDbaBuPRMa3371QXI2ZY7I27lUvvx2aEVKNkuxgFzqX0GSd1FUFdRc
 GZdLBVsiV1FZtXJ6rte5z18w7I+vn77GgyNQTs/0w6YS8ofWHeR2MQCF95g4uJhT
 YSo0/3O2bJxEoyQ1t2NQISSdG2/1BMxsOFejMITqxLgGYUYqL0D739aatiq53HCt
 vlmn7npUvik1r804Tun/isqkv8IRXHf3Dhy31mPFmlYRIR4sm9vuEk2SWoWcadDi
 BH+ej6YmYloklKwoj2yiC7MtOl4N+hPvLDZmZvich16eJc0BI1Wu9QfTTJ+pH895
 R5twBPioRmE67Mg+edMCrsmDv6a8ECaUnf/ODLg0qYHreE9MplSi98JJw+lfTAxb
 DWLng7tcgp8SV+6gW5pc
 =xfL0
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v4.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO fixes from Linus Walleij:
 "Here is a bunch of GPIO fixes that I collected since -rc1, nothing
  controversial, nothing special:

   - fix a memory leak for GPIO hotplug.

   - fix a signedness bug in the ACPI GPIO pin validation.

   - driver fixes: Qualcomm SPMI and OMAP MPUIO IRQ issues"

* tag 'gpio-v4.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
  gpio: omap: Fix regression for MPUIO interrupts
  gpio: sysfs: fix memory leaks and device hotplug
  pinctrl: qcom-spmi-gpio: Fix input value report
  pinctrl: qcom-spmi-gpio: Fix output type configuration
  gpiolib: change gpio pin from unsigned to signed in acpi callback
2015-05-08 19:42:59 -07:00
Doug Anderson
c5272a2856 pinctrl: Don't just pretend to protect pinctrl_maps, do it for real
Way back, when the world was a simpler place and there was no war, no
evil, and no kernel bugs, there was just a single pinctrl lock.  That
was how the world was when (57291ce pinctrl: core device tree mapping
table parsing support) was written.  In that case, there were
instances where the pinctrl mutex was already held when
pinctrl_register_map() was called, hence a "locked" parameter was
passed to the function to indicate that the mutex was already locked
(so we shouldn't lock it again).

A few years ago in (42fed7b pinctrl: move subsystem mutex to
pinctrl_dev struct), we switched to a separate pinctrl_maps_mutex.
...but (oops) we forgot to re-think about the whole "locked" parameter
for pinctrl_register_map().  Basically the "locked" parameter appears
to still refer to whether the bigger pinctrl_dev mutex is locked, but
we're using it to skip locks of our (now separate) pinctrl_maps_mutex.

That's kind of a bad thing(TM).  Probably nobody noticed because most
of the calls to pinctrl_register_map happen at boot time and we've got
synchronous device probing.  ...and even cases where we're
asynchronous don't end up actually hitting the race too often.  ...but
after banging my head against the wall for a bug that reproduced 1 out
of 1000 reboots and lots of looking through kgdb, I finally noticed
this.

Anyway, we can now safely remove the "locked" parameter and go back to
a war-free, evil-free, and kernel-bug-free world.

Fixes: 42fed7ba44 ("pinctrl: move subsystem mutex to pinctrl_dev struct")
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 16:24:28 +02:00
Krzysztof Kozlowski
e5b6095376 pinctrl: single: Constify irq_domain_ops
The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 15:32:45 +02:00
Markus Pargmann
5fcdf6a7ed pinctrl: imx: Allow parsing DT without function nodes
The old format to define pinctrl settings for imx in DT has two
hierarchy levels. The first level are function device nodes. The second
level are pingroups which contain a property fsl,pins. The original
intention was to define all pin functions in a single dtsi file and just
reference the correct ones in the board files.
This idea was rejected some time ago leading to the current design to
have all the pinfunctions defined in the board files. So we don't need
the function device nodes anymore.

This patch changes the pinctrl driver to accept devicetrees which do not
have the first hierarchy level, function device nodes. For example
karo-tx25 already has such a devicetree. Old devicetrees are still
parsed and supported.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 15:30:24 +02:00
Helmut Buchsbaum
83a21727c3 pinctrl: zynq: configure SPI SSx pins separately
Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.

This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:

pinctrl_spi0_default: spi0-default {
	mux_spi {
		function = "spi0";
		groups = "spi0_0_grp";
	};

	mux_ss {
		function = "spi0_ss";
		groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
	}

	conf-output {
		pins = "MIO16", "MIO21";
		slew-rate = <0>;
		bias-disable;
		low-power-disable;
		io-standard = <1>;
	};

	conf-input {
		pins = "MIO17";
		slew-rate = <0>;
		bias-high-impedance;
		low-power-disable;
		io-standard = <1>;
	};

	conf-select {
		pins = "MIO18", "MIO19";
		slew-rate = <0>;
		bias-pull-up;
		low-power-disable;
		io-standard = <1>;
	};
};

pinctrl_gpio0_default {
	mux {
		function = "gpio0";
		groups = "gpio0_20_grp"
	};

	conf {
		pins = "MIO20";
		slew-rate = <0>;
		bias-pull-up;
		low-power-disable;
		io-standard = <1>;
	};
};

Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 15:26:52 +02:00
Linus Walleij
3007d941be pinctrl: nomadik: assign chips dynamically
Assign GPIO chip and irqchip to the GPIO container dynamically,
so we can set a unique name for each GPIO irqchip and see what
chip the hwirq offset actually relates to.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:48:22 +02:00
Linus Walleij
a21763a0b1 pinctrl: nomadik: activate strict mux mode
This activates strict mode muxing for the Nomadik pin controllers,
as these do not allow GPIO and functions to use the same pin
simultaneously.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:19 +02:00
Linus Walleij
8c4c201634 pinctrl: move strict option to pinmux_ops
While the pinmux_ops are ideally just a vtable for pin mux
calls, the "strict" setting belongs so intuitively with the
pin multiplexing that we should move it here anyway. Putting
it in the top pinctrl_desc makes no sense.

Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:19 +02:00
Sonic Zhang
fa76a3db70 pinctrl: allow exlusive GPIO/mux pin allocation
Disallow simultaneous use of the the GPIO and peripheral mux
functions by setting a flag "strict" in struct pinctrl_desc.

The blackfin pinmux and gpio controller doesn't allow user to
set up a pin for both GPIO and peripheral function. So, add flag
strict in struct pinctrl_desc to check both gpio_owner and
mux_owner before approving the pin request.

v2-changes:
- if strict flag is set, check gpio_owner and mux_onwer in if and
  else clause

v3-changes:
- add kerneldoc for this struct
- augment Documentation/pinctrl.txt

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:19 +02:00
Frank Li
c30024a644 pinctrl: add imx7d support
Add i.MX7D pinctrl driver support

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:19 +02:00
Joachim Eastwood
2f77ac93a9 pinctrl: add lpc18xx pinctrl driver
Pinctrl driver for the System Control Unit (SCU) found on NXP
LPC18xx/43xx devices.

Driver uses the generic pinctrl DT bindings for multiplexing
and property settings.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:18 +02:00
Alexander Stein
1893b2cfad pinctrl: at91: Add set_multiple GPIO chip feature
This adds the callback for set_multiple.

As this controller has a separate set and clear register, we
can't write directly to PIO_ODSR as this would required a cached
variable and would race with at91_gpio_set.

So build masks for the PIO_SODR and PIO_CODR registers and
write them together.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:18 +02:00
Colin Ian King
74d77e50f2 pinctrl: mediatek: mtk-common: initialize unmask
cppcheck detected an uninitialized variable:

[drivers/pinctrl/mediatek/pinctrl-mtk-common.c:897]:
  (error) Uninitialized variable: unmask

unmask should be initialized to zero to ensure unmasking
only occurs if a previous mask occurred. The current situation
is that the unmask variable could contain any random garbage
causing random unexpected unmasking.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-04 15:20:22 +02:00
Ivan T. Ivanov
4e637ac212 pinctrl: qcom-spmi-mpp: Fix input value report
Fix interpretation of the pmic_mpp_read() return code,
negative value means an error.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-28 14:52:50 +02:00
Ivan T. Ivanov
24a66618d6 pinctrl: qcom-spmi-gpio: Fix input value report
Read input buffer when input is enabled, not when it is
disabled. Also fix interpretation of the pmic_gpio_read()
return code, negative value means an error.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-28 14:51:45 +02:00
Ivan T. Ivanov
982df6aec0 pinctrl: qcom-spmi-gpio: Fix output type configuration
GPIO output type configuration was incorrectly overwritten
by strength value. Fix this.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-28 14:51:11 +02:00
Ivan T. Ivanov
dc391502fd pinctrl: qcom-spmi: Fix pin direction configuration
Pin direction configuration was incorrectly overwritten
by output and function values in set_mux(). Fix this.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-27 15:33:42 +02:00
Andrew Andrianov
a526973e02 pinctrl: mvebu: Fix mapping of pin 63 (gpo -> gpio)
Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-27 15:23:58 +02:00
Linus Walleij
b99e6fb865 pinctrl: fix allmodconfig noise
There was some mess in the dependencies in the pinctrl
Kconfig for compile tests under allmodconfig. Mea Culpa.

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-15 10:02:42 +02:00
Linus Torvalds
07e492eb89 This is the bulk of pin control changes for the v4.1 development
cycle:
 
 New drivers:
   - Intel Sunrisepoint
   - AMD KERNCZ GPIO
   - Broadcom Cygnus IOMUX
 
 New subdrivers:
   - Marvell MVEBU Armada 39x SoCs
   - Samsung Exynos 5433
   - nVidia Tegra 210
   - Mediatek MT8135
   - Mediatek MT8173
   - AMLogic Meson8b
   - Qualcomm PM8916
 
 On top of this cleanups and development history for the above
 drivers as issues were fixed after merging.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVLSiSAAoJEEEQszewGV1z/nMP/jXyxCb8THuAyCFkJoY+Hgzz
 dj3eMt+TPPyqt6lG3WODq/lQFxEdE28TqHYf2eGVdpriCpuyecFxyf9MPzY3P60E
 v6XfzIeUOIGovw781qsg9TxJAZ0C+DLmNgpS8kWhnK7Igs3EJrRcz5Zz00F32olv
 1dojVIQF6Nsn3M2Cc6bzF2wkJre3tLsUT7KXGZw4e3yA0K1XMZI3jYYXZ25GgLW0
 CpZ1vKdKgwuBsgV5waJ8XZuFMqo3FRhjcD/f8ubk5hhMK6Wx6gszBcrLKVlkbz+2
 XJzhn5tZSupSKmBtl0gCzP7pgVc0JeV8P12hHv6imT82rCU0YGBidNX2s3GrscnF
 Nfwpw/BsaOXcu9CttI5LndvDlvCH2hUAal6i4IghiL5sRzlcW4jUoWHkIa8e6dHe
 e/zjJSo7tXrWio30Dl6++qklcDimP3sbaaFseENhLUSl7hDGJ09Tx8yxEOFN3PX6
 29i7ZC+ifZFzS30E3E+MOlFrxp3MB7j/z/ig3HL7XYr/TTiCKMNbKJNOlmGEfiTV
 VI3GvTAJgt/1U+AOJI7a5xrxivaGL5GWXuoonQHY1gPrvjqkL54w4j+XBpj4tXIV
 LBh6AS6G6AJDUOEU00EroCxOt1FPMW24zQvTKP18sgXsKWqHTIKT9B5RZbDXM9D7
 pLfOIy0H1RWdQGvGgK7X
 =MGqe
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pincontrol updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.1 development
  cycle.  Nothing really exciting this time: we basically added a few
  new drivers and subdrivers and stabilized them in linux-next.  Some
  cleanups too.  With sunrisepoint Intel has a real fine fully featured
  pin control driver for contemporary hardware, and the AMD driver is
  also for large deployments.  Most of the others are ARM devices.

  New drivers:
    - Intel Sunrisepoint
    - AMD KERNCZ GPIO
    - Broadcom Cygnus IOMUX

  New subdrivers:
    - Marvell MVEBU Armada 39x SoCs
    - Samsung Exynos 5433
    - nVidia Tegra 210
    - Mediatek MT8135
    - Mediatek MT8173
    - AMLogic Meson8b
    - Qualcomm PM8916

  On top of this cleanups and development history for the above drivers
  as issues were fixed after merging"

* tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits)
  pinctrl: sirf: move sgpio lock into state container
  pinctrl: Add support for PM8916 GPIO's and MPP's
  pinctrl: bcm2835: Fix support for threaded level triggered IRQs
  sh-pfc: r8a7790: add EtherAVB pin groups
  pinctrl: Document "function" + "pins" pinmux binding
  pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
  pinctrl: fsl: imx: Check for 0 config register
  pinctrl: Add support for Meson8b
  documentation: Extend pinctrl docs for Meson8b
  pinctrl: Cleanup Meson8 driver
  Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion.
  pinctrl: at91: convert __raw to endian agnostic IO
  pinctrl: constify of_device_id array
  pinctrl: pinconf-generic: add dt node names to error messages
  pinctrl: pinconf-generic: scan also referenced phandle node
  pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
  pinctrl: st: Display pin's function when printing pinctrl debug information
  pinctrl: st: Show correct pin direction also in GPIO mode
  pinctrl: st: Supply a GPIO get_direction() call-back
  pinctrl: st: Move st_get_pio_control() further up the source file
  ...
2015-04-14 17:58:15 -07:00
Linus Torvalds
d0bbe0dd35 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree from Jiri Kosina:
 "Usual trivial tree updates.  Nothing outstanding -- mostly printk()
  and comment fixes and unused identifier removals"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial:
  goldfish: goldfish_tty_probe() is not using 'i' any more
  powerpc: Fix comment in smu.h
  qla2xxx: Fix printks in ql_log message
  lib: correct link to the original source for div64_u64
  si2168, tda10071, m88ds3103: Fix firmware wording
  usb: storage: Fix printk in isd200_log_config()
  qla2xxx: Fix printk in qla25xx_setup_mode
  init/main: fix reset_device comment
  ipwireless: missing assignment
  goldfish: remove unreachable line of code
  coredump: Fix do_coredump() comment
  stacktrace.h: remove duplicate declaration task_struct
  smpboot.h: Remove unused function prototype
  treewide: Fix typo in printk messages
  treewide: Fix typo in printk messages
  mod_devicetable: fix comment for match_flags
2015-04-14 09:50:27 -07:00
Linus Walleij
1dfe0d159d pinctrl: sirf: move sgpio lock into state container
Instead of referring to a global static variable for the sgpio
locking, use the state container to contain the lock.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-09 10:16:13 +02:00
Ivan T. Ivanov
7414b0993c pinctrl: Add support for PM8916 GPIO's and MPP's
Add compatible string definitions and supported pin functions.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-08 17:00:18 +02:00
Charles Keepax
b8a19382ac pinctrl: bcm2835: Fix support for threaded level triggered IRQs
Currently, the driver uses handle_simple_irq for all IRQ types and hard
codes the acknowledge for different IRQ types into the handler. It is
better to use the IRQ core as intended and let it handle the differences
between the various types of IRQ. For example the current system does
not work for threaded level triggered IRQs as these need to be masked
until the threaded handler has run.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-08 16:41:59 +02:00
Sergei Shtylyov
19ef697d1e sh-pfc: r8a7790: add EtherAVB pin groups
Add EtherAVB pin groups to R8A7790 PFC driver.

Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 15:21:26 +02:00
Mika Westerberg
7981c0015a pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a
Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO
interrupts).

The driver is split into core and platform parts so that the same core
driver can be reused in other drivers for other Intel GPIO hardware that is
based on the same host controller design.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 15:15:23 +02:00
Markus Pargmann
16837f9588 pinctrl: fsl: imx: Check for 0 config register
0 is used in all pinfunction definitions when a config register is not
available, for example imx25-pinfunc.h. If a configuration value is used
for such a pinfunction the driver will always write it to the
configuration register if it is not -1. For a 0 configuration register
the configuration value is written to offset 0x0. This can lead to a
crashing/hanging system without any warning message.

This patch checks for 0 config register and sets the internal value to
-1. If the configuration value is not NO_PADCTL this leads to an error
message that applying the configuration failed.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 15:11:00 +02:00
Carlo Caione
0fefcb6876 pinctrl: Add support for Meson8b
This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:44:40 +02:00
Carlo Caione
faa246debf documentation: Extend pinctrl docs for Meson8b
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:42:38 +02:00
Carlo Caione
0cf6f3c2b5 pinctrl: Cleanup Meson8 driver
This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:40:42 +02:00
Ken Xue
25a853d037 Fix inconsistent spinlock of AMD GPIO driver which can be
recognized by static analysis tool smatch. Declare constant
Variables with Sparse's suggestion.

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:36:49 +02:00
Ben Dooks
d480239ba4 pinctrl: at91: convert __raw to endian agnostic IO
Use endian agnostic _relaxed IO accessors instead of the __raw ones.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:05:53 +02:00
Fabian Frederick
baa9946e32 pinctrl: constify of_device_id array
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)

Signed-off-by: Fabian Frederick <fabf@skynet.be>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Lee Jones <lee@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:58:35 +01:00
Baruch Siach
4024efb404 pinctrl: pinconf-generic: add dt node names to error messages
This makes the error message much more useful.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:53:10 +01:00
Baruch Siach
c7289500e2 pinctrl: pinconf-generic: scan also referenced phandle node
Make pinconf_generic_dt_node_to_map() also scan the dt pin configuration node
directly referenced by phandle, not only its child nodes.

The "parent scan" feature needs a few other changes:

   * Move the pinconf_generic_dt_node_to_map() error handling code to a common
     place, under the 'exit' label.

   * Move the pins/groups strings count earlier in
     pinconf_generic_dt_subnode_to_map(), to allow us to bail out early when
     these properties are missing or wrong

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:51:22 +01:00
Thomas Petazzoni
12149a20b8 pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
This commit adds suspend/resume support to the Armada XP pinctrl
driver, by simply saving and restoring the MPP registers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:35:08 +01:00
Lee Jones
a8381faca5 pinctrl: st: Display pin's function when printing pinctrl debug information
Great for easily determining which mode a pin is operating in.
This patch was particularly helpful when debugging a recent GPIO/
Pinctrl disparity issue.

Before:
    $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
      pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
             [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

After [GPIO]:
    $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
      pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] GPIO
             [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

After [Alt]:
    $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
      pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] Alt Fn 2
             [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:39:17 +01:00
Lee Jones
e2ed0e88ec pinctrl: st: Show correct pin direction also in GPIO mode
Until now ST's pinconf_dbg_show() call-back has displayed the PIO
alternate function direction, which is only relevant if a pin is
operating in an alternate function mode i.e not GPIO mode.  If a
pin is in GPIO mode its direction is both set and status is
obtained by a completely different/unrelated bunch of registers.

This change ensures that the correct pin direction is shown, even
if a pin is operating in GPIO mode.

Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:38:06 +01:00
Lee Jones
1e702ec2aa pinctrl: st: Supply a GPIO get_direction() call-back
ST's hardware differentiates between GPIO mode and Pinctrl alternate
functions.  When a pin is in GPIO mode, there are dedicated registers
to set and obtain direction status.  However, If a pin's alternate
function is in use then the direction is set and status is derived
from a bunch of syscon registers.  The issue is; until now there was
a lack of parity between the two.

For example:

Catting the two following information sources could result in
conflicting information (output has been snipped for simplicity):

 $ cat /sys/kernel/debug/gpio
  GPIOs 32-39, platform/961f080.pin-controller-sbc, PIO4:
   gpio-33  (?                   ) out hi

 $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
  pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
         [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

In this example GPIO-33 is a GPIO controlled LED, which is set for
output, as you'd expect.  However, when the same information is
drafted from Pinctrl, it clearly states that OE (Output Enable) is
not set i.e. the pin is set for input.  This is because OE normally
only represents alternate functions and has no bearing on how the
pin operates when in Alt-0 (GPIO mode).

This patch changes the current semantics and provides a parity link
between the two subsystems.  The get_direction() call-back firstly
determines which function a pin is operating in, then uses the
appropriate helpers for that mode.

Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:37:03 +01:00
Lee Jones
f89e68fc3b pinctrl: st: Move st_get_pio_control() further up the source file
st_get_pio_control() will be used by subsequent calls which are
to be located above its original position.  This is required to
prevent the need for an unnecessary forward-declaration/prototype.

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:36:07 +01:00
Lee Jones
c2a4bf4708 pinctrl: st: Introduce a 'get pin function' call
This call fetches the numerical function value a specified pin is
currently operating in.  Function zero is more often than not the
GPIO function.  Greater than zero values represent an alternative
function.  You'd need to either look those up in the Device Tree
sources or the Programmer's Manual.

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:35:10 +01:00
Stefan Agner
e4c02dced9 pinctrl: tegra: use signed bitfields for optional fields
Optional fields are set to -1 by various preprocessor macros. Make
sure the fields can actually store them.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-19 09:20:17 +01:00
Axel Lin
86d64dce9e pinctrl: mediatek: mt8135/mt8173: Constify of_device_id table
Also make the table a bit compact.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:09:37 +01:00
Axel Lin
0206caa81c pinctrl: mediatek: mtk-common: Use devm_kcalloc at appropriate places
Prefer devm_kcalloc over devm_kzalloc with multiply.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:08:08 +01:00
Axel Lin
0dae530ccf pinctrl: mediatek: mt8135/mt8173: Fix build error due to missing include file
Fix below build error:
  CC      drivers/pinctrl/mediatek/pinctrl-mt8135.o
In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0:
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory
compilation terminated.
make[3]: *** [drivers/pinctrl/mediatek/pinctrl-mt8135.o] Error 1
make[2]: *** [drivers/pinctrl/mediatek] Error 2
make[1]: *** [drivers/pinctrl] Error 2
make: *** [drivers] Error 2

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:06:09 +01:00
Yingjoe Chen
4a8ade1f6b pinctrl: mediatek: Adjust mt8173 pinctrl kconfig
ARM64 maintainer doesn't want to add MACH_* for each SoC.
Adjust mt8173 pinctrl kconfig entry so user can manually select it.

Also make PINCTRL_MT8135 selectable when COMPILE_TEST is enabled.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:00:16 +01:00
Axel Lin
61a3557671 pinctrl: mediatek: mtk-common: Remove kfree
Remove erroneous kfree for memory allocated by devm_kzalloc

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 12:57:48 +01:00
Guenter Roeck
d48c532eb4 pinctrl: mediatek: Fix include directive
Fix the following build failure:

In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0:
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error:
	pinctrl-mtk-common.h: No such file or directory

seen when building arm:multi_v7_defconfig.

Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.")
Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 10:58:21 +01:00
Hans de Goede
ef6d24cc7f pinctrl: sun4i: GPIOs configured as irq must be set to input before reading
On sun4i-a10, when GPIOs are configured as external interrupt the value for
them in the data register does not seem to get updated, so set their mux to
input (and restore afterwards) when reading the pin.

Missed edges seem to be buffered, so this does not introduce a race
condition.

I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to
be affected, the input value representation in the data register does seem
to correctly get updated to the actual pin value while in irq mode there.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 10:56:46 +01:00
Geert Uytterhoeven
9895afae1b pinctrl: sh-pfc: Remove r8a7790 platform_device_id entry
The r8a7790 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:18:33 +01:00
Geert Uytterhoeven
889439cddc pinctrl: sh-pfc: Remove emev2 platform_device_id entry
The emev2 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:16:53 +01:00
Geert Uytterhoeven
1f34de05e7 pinctrl: sh-pfc: Use u32 to store register addresses
Currently all PFC registers lie in low 32-bit address space. Hence use
u32 instead of unsigned long to store PFC register addresses in pinctrl
tables.  All calculations of virtual addresses use a phys_addr_t
intermediate, so we know where to add an offset if the 32-bit assumption
ever becomes false.

While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a
64-bit shmobile_defconfig kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:15:40 +01:00
Geert Uytterhoeven
17c7cbb0e7 pinctrl: sh-pfc: Use reg_width instead of reg as sentinel
All other loops over sh_pfc_soc_info.data_regs[] use
pinmux_data_reg.regwidth as the sentinel, which is safer as zero is
never a valid regwidth value (reg could be zero if we start using it to
store an offset).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:14:45 +01:00
Geert Uytterhoeven
cef28a2894 pinctrl: sh-pfc: Use unsigned int for register/field widths and offsets
As register and field widths and offsets are in the range 1..32, use
unsigned int (mostly replacing unsigned long) to store them in local
variables and for passing them around.

Move to one variable per line, move variables to the beginning of the
block where they are used, and drop superfluous initializations while we
are at it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:13:47 +01:00
Geert Uytterhoeven
dc70071550 pinctrl: sh-pfc: Store register/field widths in u8 instead of unsigned long
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.

This decreases the size of a (32-bit) shmobile_defconfig kernel
supporting 7 SoCs by 26460 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:12:47 +01:00
Ken Xue
dbad75dd1f pinctrl: add AMD GPIO driver support.
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM.
Current driver patch only support GPIO in x86.

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
[Moved back to <linux/gpio.h> header]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:21 +01:00
Abhilash Kesavan
45937b5b5e pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
The alive pin controller on exynos7 does not support external gpio
interrupts. Hence, remove the eint_gpio_init call-back for it. This
fixes the following error message seen during exynos7 boot-up:
"samsung-pinctrl 10580000.pinctrl: irq number not available"

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:19 +01:00
Ray Jui
b64333ce76 pinctrl: cygnus: add gpio/pinconf driver
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller, and the always-on GPIO
controller. Basic PINCONF configurations such as bias pull up/down, and
drive strength are also supported in this driver.

Pins from the ASIU GPIO controller can be individually muxed to GPIO
function, through interaction with the Cygnus IOMUX controller

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:19 +01:00
Hongzhou Yang
c445cac307 pinctrl: mediatek: fix build error
Due to pinconf_generic_parse_dt_config() API changes in pinctrl
devel branch, add one parameter to fix build error.

Also fix warning:
drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning:
too many arguments for format [-Wformat-extra-args]
      dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret);
      ^

by removing extra parameter when calling dev_err in mtk_pctrl_init.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:17 +01:00
Yingjoe Chen
3221f40b76 pinctrl: mediatek: emulate GPIO interrupt on both-edges
MTK EINT does not support generating interrupt on both edges.
Emulate this by changing edge polarity while enable irq,
set types and interrupt handling. This follows an example of
drivers/gpio/gpio-mxc.c.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:16 +01:00
Hongzhou Yang
30f010f5c4 arm64: mediatek: Add Pinctrl/GPIO/EINT driver for mt8173.
Add mt8173 support using mediatek common pinctrl driver.
MT8173 have a different ies_smt setting register than mt8135,
so adding this support to common code.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:16 +01:00
Maoguang Meng
d9819eb9cd pinctrl: mediatek: Add EINT support to MTK pinctrl driver.
MTK SoC support external interrupt(EINT) from most SoC pins.
Add EINT support to pinctrl driver.

Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:15 +01:00
Hongzhou Yang
a6df410d42 pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.

The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.

This driver include common driver and mt8135 part.
The common driver include the pinctrl driver and GPIO driver.
The mt8135 part contain its special device data.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:14 +01:00
Geert Uytterhoeven
fc88936ad3 pinctrl: sh-pfc: Use u32 to store register data
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly
replacing unsigned long) to store (parts of) register values and masks.

Switch the shadow register operations from {set,clear}_bit() to plain C
bit operations, as the former can operate on long data only.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:13 +01:00
Ray Jui
cbd159ed4f pinctrl: cygnus: add initial IOMUX driver support
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be muxed to GPIO individually

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:13 +01:00
Ray Jui
b17f2f9b86 pinctrl: bcm: consolidate Broadcom pinctrl drivers
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/*

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:12 +01:00
Stefan Agner
4691dd0148 pinctrl: imx: do not implicitly set pin regs to -1
Commit 3dac1918a4 ("pinctrl: imx: detect uninitialized pins") needs
the values in struct imx_pin_reg to be -1. This has been done in a
rather unorthodox way by setting the memory to 0xff using memset...
Use a proper for loop to initialize the whole array with -1.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:11 +01:00
Boris Brezillon
bd8733738c pinctrl: at91: move lock/unlock_as_irq calls into request/release
The gpiochip_lock_as_irq call can fail and return an error,
while the irq_startup is not expected to fail (returns an
unsigned int which is not checked by irq core code).

irq_request/release_resources functions have been created
to address this problem.

Move gpiochip_lock/unlock_as_irq calls into
irq_request/release_resources functions to prevent using a
gpio as an irq if the gpiochip_lock_as_irq call failed.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:01:36 +01:00
qipeng.zha
549e783f6a pinctrl: update direction_output function of cherryview driver
From the comments of gpiod_direction_output(), need to set @value
as initial output, so update the lowlevel routine to make it work.

Signed-off-by: jason.cj.chen<jason.cj.chen@intel.com>
Signed-off-by: qipeng.zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-10 09:02:23 +01:00
Stanimir Varbanov
407f5e392f pinctrl: qcom: handle input-enable pinconf property
This enables support of 'input-enable' pinconf generic property in
the pinctrl driver.

Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:11:01 +01:00
Stanimir Varbanov
38d756af72 pinctrl: qcom: enable generic pinconf
This makes the pinctrl driver to use the generic pinconf
interface. Mainly it gives us a way to use debugfs to dump
group configurations.

Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:11:01 +01:00
Baruch Siach
11131ba435 pinctrl: at91: simplify probe error handling
There is no code ender the 'err' label. Just return the error code directly.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:11:00 +01:00
Colin Ian King
28b30c306a pinctrl: sirf: fix typo in kernel warning on a bad interrupt
Fix typo, "flaged" -> "flagged"

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:59 +01:00
Stephen Warren
9184f75690 pinctrl: tegra: add a driver for Tegra210
Tegra210's pinmux supports a different set of pins/options than earlier
SoCs, so requires its own driver (well, table of pin-specific data).

Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:59 +01:00
Stephen Warren
ec654e50c6 pinctrl: tegra: support nvidia,io-hv DT property
Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular
pin's IO buffers are configured to accept "high voltage" input signals.
The TRM for different chips names the register field rcv-sel on older
SoCs and io_hv on newer SoCs. Add the new naming option into the pinctrl
driver so that DT files can use naming consistent with the TRM.

This new property name will be documented in the patch that adds support
for the new SoC.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:58 +01:00
Stephen Warren
ea62306193 pinctrl: tegra: some bits move between registers
Some of the pinmux configuration bits that exist in "drive group"
registers in Tegra30..Tegra124 move to the "pinmux" registers on future
chips. Add a flag to support this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:58 +01:00
Stephen Warren
8d4684b39b pinctrl: tegra: driver layout/consistency fixes
Various non-semantic tweaks and layout/consistency fixes for existing
Tegra pinctrl drivers.

Move the definition of DRV_PINGROUP_REG() before the definition of
PINGROUP() so that a future SoC driver can invoke the former from the
latter.

PINGROUP_BIT_Y(n) is just n, so replace it with n.

Re-wrap the parameters to *PINGROUP().

Keep various enums sorted in the Tegra124 driver.

Various white-space consistency fixes.

These changes aim to update existing drivers to be consistent with future
SoC drivers. While we could ignore these tweaks to the existing drivers,
I'd like to keep everything as consistent as possible for easy comparison.
Besides, I auto-generate the drivers, and maintaining special-cases to
keep the differences in place is annoying.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:57 +01:00
Baruch Siach
b5eec4d061 pinctrl: lantiq: fix include guard #endif comment
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:57 +01:00
Sanjeev Sharma
ace16867fa pinctrl: freescale: make of_device_id array const
Make of_device_id array const.

Signed-off-by: Sanjeev Sharma <Sanjeev_Sharma@mentor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:56 +01:00
Geert Uytterhoeven
05c5f265c6 pinctrl: sh-pfc: Do not overwrite bias configuration
After the last user of the in_pd/in_pu bias parameters of the _PCRH()
macro was removed in commit 80da8e02d2 ("sh-pfc: r8a7740: Add bias
(pull-up/down) pinconf support"), bias parameters are supposed to be
configured using the generic pinctl mechanism, which calls the
.set_bias() method.

However, the PORTCR() macro still represents the control register as
consisting of two 4-bit fields. Hence the bias configuration in the
uppermost 2 bits is always overwritten with zeroes when a pin is
configured for GPIO, disabling any previously configured bias.

Use the variable config register macro instead, to represent the
register as having 4 fields, and to make sure only the input/output
control and function fields are touched.

This affects R-Mobile APE6 (r8a73a4), R-Mobile A1 (r8a7740), SH-Mobile
AP4 (sh7372), and SH-Mobile AG5 (sh73a0).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:56 +01:00
Laurent Pinchart
eaef1279fa pinctrl: sh-pfc: Remove r8a7791 platform_device_id entry
The r8a7791 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:55 +01:00
Masanari Iida
f42cf8d6a3 treewide: Fix typo in printk messages
This patch fix spelling typo in printk messages.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2015-03-06 23:04:40 +01:00
Mika Westerberg
fcc18deb76 pinctrl: baytrail: Save pin context over system sleep
The BIOS might reconfigure pins as it needs when S3 is entered. This might
cause drivers using the GPIOs to fail because the state was wrong or
interrupts stopped working.

Fix this by saving and restoring enough pin context over system sleep.

Reported-by: Hans Holmberg <hans.holmberg@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06 12:25:07 +01:00
Mika Westerberg
31e4329f99 pinctrl: baytrail: Rework interrupt handling
Instead of handling everything in the driver's first level interrupt
handler, we can take advantage of already existing flow handlers that are
provided by the IRQ core.

This changes the functionality a bit also. Previously the driver looped
over pending interrupts in a single loop, restarting the loop if some
interrupt changed state. This caused problem with Lenovo Thinkpad 10
digitizer that it was not able to deassert the interrupt before the driver
disabled the interrupt for good (looplimit was exhausted).

Rework the interrupt handling logic a bit so that we provide proper mask,
ack and unmask operations in terms of Baytrail GPIO hardware and loop over
pending interrupts only once. If the interrupt remains asserted the first
level handler will be re-triggered automatically.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06 12:22:41 +01:00
Mika Westerberg
95f0972c7e pinctrl: baytrail: Clear interrupt triggering from pins that are in GPIO mode
If the pin is already configured as GPIO and it has any of the triggering
flags set, we may get spurious interrupts depending on the state of the
pin.

Prevent this by clearing the triggering flags on such pins. However, if the
pin is also configured as "direct IRQ" we leave the flags as is. Otherwise
it will prevent interrupts that are routed directly to IO-APIC.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06 12:21:09 +01:00
Mika Westerberg
f8323b6bb2 pinctrl: baytrail: Relax GPIO request rules
Zotac ZBOX PI320, a Baytrail based mini-PC, has power button connected to a
GPIO pin and it is exposed to the operating system as Windows 8 button
array. This is implemented in Linux as a driver using gpio_keys.

However, BIOS on this particula machine forgot to mux the pin to be a GPIO
instead of native function, which results following message to be seen on
the console:

 byt_gpio INT33FC:02: pin 16 cannot be used as GPIO.

This causes power button to not work as the driver was not able to request
the GPIO it needs.

So instead of completely preventing this we allow turning the pin as GPIO
but issue warning that something might be wrong.

Reported-by: Benjamin Adler <benadler@gmx.net>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06 12:19:51 +01:00
Chanwoo Choi
3c5ecc9ed3 pinctrl: exynos: Add support for Exynos5433
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.

Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-05 10:52:54 +01:00
Thomas Petazzoni
ee086577ab pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x
This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
support pin-muxing on Marvell EBU processors. Two variants of the
Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada
398), which have a few differences in the available functions for
certain pins.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-04 13:53:55 +01:00
Linus Torvalds
ce01e871a1 This is the bulk of pin control changes for the v3.20 cycle:
- Framework changes and enhancements:
   - Passing -DDEBUG recursively to subdir drivers so we get
     debug messages properly turned on.
   - Infer map type from DT property in the groups parsing code
     in the generic pinconfig code.
   - Support for custom parameter passing in generic pin config.
     This is used when you are using the generic pin config, but
     want to add a few custom properties that no other driver
     will use.
 
 - New drivers:
   - Driver for the Xilinx Zynq
   - Driver for the AmLogic Meson SoCs
 
 - New features in drivers:
   - Sleep support (suspend/resume) for the Cherryview driver
   - mvebeu a38x can now mux a UART on pins MPP19 and MPP20
   - Migrated the qualcomm driver to generic pin config handling
     of extended config options in the core code.
   - Support BUS1 and AUDIO in the Exynos pin controller.
   - Add some missing functions in the sun6i driver.
   - Add support for the A31S variant in the sun6i driver.
   - EMEv2 support in the Renesas PFC driver.
   - Ass support for Qualcomm MSM8916 in the qcom driver.
 
 - Deleted features
   - Drop support for the SiRF Marco that was never released to
     the market.
   - Drop SH7372 support as the support for this platform is
     removed from the kernel.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU2w2GAAoJEEEQszewGV1z7kYQAKw4Y4SY9Mq9O97GBq0JWvzv
 uLK4P8NvegHkgX0IDc/etAtHzBN6L+4axh7rDAsaDhug+42CbZxVZjXCfLGFClZP
 kJ/gz4II28AGWiP7TZPNHspIJYgKUdWcVfg0cTZwpM22/AEdBAo9HQ2a/FltvrCn
 eYwzFlAOKUUygmDdbfXHk5Z+ndrJw0ahLjXn8zjBe1HkD2QVaigM9ecA2aQHiG9a
 QvABUJ2qVVs9rqTIxoVzSIGTLeLzrv8cezDLQhZ4KaEasAkxtWKM4kYQSMx/PoTB
 mg+FZ5B8IXqlksnSljT+wOcSP1nmtRdjnED/MpsSLbo9RfJgHkA4Lu4Q8iqt7rZL
 +k/kKi3+p9pTE2pIi56nSpHnfgF8JHgdRAYIXBea5Ug0YnBp83/5jLrU7Fmcjr7s
 l0PH0Fk0iRFRdfn6crcs+SLrhQKtuP+Douwg+3ujVOQiKIW6m+b161GwEVYkvWlq
 1JRWPSjncpsmyg5O8dEwZDwgtzPU65UMEsLgRk9wMNJYw0TqGPugEy4+2rBdJWLy
 CYzJo2At9OcHbB2rT8UKwtErQF85IcWmfnMyfo2PANTLGaj5EFruhmSc2J0m7kOe
 ExPXtWOWxGCtWG53ZDeJUYBg9ySMyleY10LYBP9fPQnotvNB3vfyAkBwV74fnBXs
 ijxO6/Uamd4Rrs5LDRBL
 =Nbzh
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pincontrol updates from Linus Walleij:
 :This is the bulk of pin control changes for the v3.20 cycle:

  Framework changes and enhancements:
   - Passing -DDEBUG recursively to subdir drivers so we get debug
     messages properly turned on.
   - Infer map type from DT property in the groups parsing code in the
     generic pinconfig code.
   - Support for custom parameter passing in generic pin config.  This
     is used when you are using the generic pin config, but want to add
     a few custom properties that no other driver will use.

  New drivers:
   - Driver for the Xilinx Zynq
   - Driver for the AmLogic Meson SoCs

  New features in drivers:
   - Sleep support (suspend/resume) for the Cherryview driver
   - mvebeu a38x can now mux a UART on pins MPP19 and MPP20
   - Migrated the qualcomm driver to generic pin config handling of
     extended config options in the core code.
   - Support BUS1 and AUDIO in the Exynos pin controller.
   - Add some missing functions in the sun6i driver.
   - Add support for the A31S variant in the sun6i driver.
   - EMEv2 support in the Renesas PFC driver.
   - Add support for Qualcomm MSM8916 in the qcom driver.

  Deleted features
   - Drop support for the SiRF Marco that was never released to the
     market.
   - Drop SH7372 support as the support for this platform is removed
     from the kernel"

* tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits)
  sh-pfc: emev2 - Fix mangled author name
  pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs
  pinctrl: imx25: fix numbering for pins
  pinctrl: pinctrl-imx: don't use invalid value of conf_reg
  pinctrl: qcom: delete pin_config_get/set pinconf operations
  pinctrl: qcom: Add msm8916 pinctrl driver
  DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding
  pinctrl: qcom: increase variable size for register offsets
  pinctrl: hide PCONFDUMP in #ifdef
  pinctrl: rockchip: Only mask interrupts; never disable
  pinctrl: zynq: Fix usb0 pins
  pinctrl: sh-pfc: sh7372: Remove DT binding documentation
  pinctrl: sh-pfc: sh7372: Remove PFC support
  sh-pfc: Add emev2 pinmux support
  sh-pfc: add macro to define pinmux without function
  pinctrl: add driver for Amlogic Meson SoCs
  staging: drivers: pinctrl: Fixed checkpatch.pl warnings
  pinctrl: exynos: Add AUDIO pin controller for exynos7
  sh-pfc: r8a7790: add MLB+ pin group
  sh-pfc: r8a7791: add MLB+ pin group
  ...
2015-02-11 11:23:13 -08:00
Geert Uytterhoeven
f724e05baa sh-pfc: emev2 - Fix mangled author name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fixes: 1e7d5d849c ("sh-pfc: Add emev2 pinmux support")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-02-05 14:51:34 +01:00
Mika Westerberg
2479c7300e pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs
If the pin is in HiZ mode when it is requested as GPIO its value cannot be
read (it always returns 0). In order to cope with the Linux GPIO subsystem
where we do not have such state at all, turn the pin to be input instead.

Reported-by: Jerome Blin <jerome.blin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-02-04 09:59:26 +01:00
Uwe Kleine-König
34027ca2bb pinctrl: imx25: fix numbering for pins
The pin id for a given tuple listed in a fsl,pins property is calculated
by dividing the first entry (which is also a register offset) by 4.
As the first available register is at offset 0x8 and configures the pad
MX25_PAD_A10 the right id for this pin is 2. All other pins are off by
one, too.

This patch drops the definition MX25_PAD_RESERVE1 (together with its
only use) and decrements all following values by 1.

Fixes: b4a87c9b96 ("pinctrl: pinctrl-imx: add imx25 pinctrl driver")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-02-03 14:02:55 +01:00
Uwe Kleine-König
4ff0f034e9 pinctrl: pinctrl-imx: don't use invalid value of conf_reg
The right check for conf_reg to be invalid it testing against -1 not 0
as is done in the rest of the driver.

This fixes an oops that can be triggered by:

	cat /sys/kernel/debug/pinctrl/43fac000.iomuxc/*

Fixes: ae75ff8145 ("pinctrl: pinctrl-imx: add imx pinctrl core driver")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-02-03 13:57:52 +01:00
Stanimir Varbanov
fc0d8fda50 pinctrl: qcom: delete pin_config_get/set pinconf operations
The .pin_config_get/set operation are not supported in qcom pinctrl
driver. As the pinconf core is smart enough it doesn't complain
about that.

Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 14:36:33 +01:00
Joonwoo Park
5373a2c5ab pinctrl: qcom: Add msm8916 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for msm8916.

Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 14:35:09 +01:00
Joonwoo Park
981de1cb42 pinctrl: qcom: increase variable size for register offsets
On newer TLMM hardware blocks the registers are spread and
we need an offsets upper than 16 bits to address them. Increase
the register offset variables to 32 bits size.

Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 14:32:44 +01:00
Arnd Bergmann
4f06266a62 pinctrl: hide PCONFDUMP in #ifdef
The zynq and qcom-spmi pinctrl drivers both use pin_config_item arrays
to provide extra interfaces in debugfs. This structure and the
PCONFDUMP macro are not defined if CONFIG_DEBUG_FS is turned off,
so we get build errors like:

pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: error: array type has incomplete element type
 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
                                     ^
pinctrl/qcom/pinctrl-spmi-gpio.c:140:2: error: implicit declaration of function 'PCONFDUMP' [-Werror=implicit-function-declaration]
  PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
  ^
pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: warning: 'pmic_conf_items' defined but not used [-Wunused-variable]
 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {

Lacking any better idea to solve this nicely, this patch uses #ifdef
to hide the structures, just like the pinctrl core does.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 14:30:59 +01:00
Doug Anderson
5ae0c7ad06 pinctrl: rockchip: Only mask interrupts; never disable
The Rockchip GPIO interrupt controller totally throws away all status
about an interrupt when you "disable" the interrupt.  That has
unfortunate consequences in the following situation:

1. An edge-triggered interrupt is enabled and should wake the system.
2. System suspend happens: interrupt is disabled and marked for wake.
3. rockchip_irq_suspend() reenables the interrupt so we can wake.
4. Interrupt happens when asleep.
5. rockchip_irq_resume() redisables the interrupt.
6. Disabling the interrupt throws away all status about it.
7. Normal system resume happens and we enable the interrupt again,
   since we threw away status about the interrupt we don't know it
   fired while suspended.  Even worse: if we need both edges of the
   interrupt the logic to swap edges never runs.

Note: even if we somehow can post the status about wakeup interrupts
in rockchip_irq_resume() we would still have a window of losing any
edges that came in while interrupts were disabled.

If we use mask only then we don't need to worry.  The GPIO Interrupt
controller keeps track of pending interrupts that are enabled and just
masked.

There was no real strong reason to support the enable/disable
functionality (other than that it seemed right), so let's go back to
just supporting mask/unmask but actually map it to the real
mask/unmask.  This ends up with slightly different (and more correct)
behavior than before (f2dd028 pinctrl: rockchip: Fix
enable/disable/mask/unmask).

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 10:38:36 +01:00
Linus Walleij
b6afdbe8e8 Linux 3.19-rc6
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJUxbzlAAoJEHm+PkMAQRiGtqYIAJ8YlKX9cXKYmXx8/FncINH+
 2erj94KyHG080R1uwSq1+7zXWCZUUlxiJnDnsup5rG0dImcicqgOE48oHax1aN6b
 yHfPONkTjNJ1HYepuGC3YWCG9wIjPZQ5S8KHrwRjyVoE+ddhe9gWgvArA3jl/fW/
 2fYNWekoRoMcRiNb4/w2weyOOBywdSVpmj0WYiwdztysG2ymw5hUXRHJhvSf1AFm
 RQJfUHkhCOYpQGY7XFba/1uGhTJfOgDmYAfspAOLzmrXE/DJcCutsVdBZO+12fAL
 nhGpM/PkRYxMvwzDKIUoG35qsymYOMqo54oXhr0S2JjyXTGdGmB6qHxIfqnV5Tk=
 =O/Lr
 -----END PGP SIGNATURE-----

Merge tag 'v3.19-rc6' into devel

Linux 3.19-rc6
2015-01-30 10:38:15 +01:00
Andreas Färber
8090f7917b pinctrl: zynq: Fix usb0 pins
Fix usb0 pin 19 -> 29 (matching ethernet1 pins and manual).
Pin 19 is used for ethernet0 on the Parallella board.

Fixes: add958cee9 ("pinctrl: Add driver for Zynq")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 10:31:49 +01:00
Magnus Damm
62476634d7 pinctrl: sh-pfc: sh7372: Remove PFC support
Remove sh7372 PFC support as part of the sh7372 and Mackerel
legacy code removal.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 10:40:38 +01:00
Niklas Söderlund
1e7d5d849c sh-pfc: Add emev2 pinmux support
Add PFC support for the EMMA Mobile EV2 SoC including pin groups for
on-chip devices.

Signed-off-by: Niklas Söderlund <niso@kth.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-27 08:50:22 +01:00
Niklas Söderlund
4c9e473541 sh-pfc: add macro to define pinmux without function
Used to define pinmux configurations where the pinmux function have no
representation in the configuration registers but instead solely depends
on a group selection.

Signed-off-by: Niklas Söderlund <niso@kth.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-27 08:47:53 +01:00
Jean-Christophe PLAGNIOL-VILLARD
a0b957f306 pinctrl: at91: allow to have disabled gpio bank
Today we expect that all the bank are enabled, and count the number of banks
used by the pinctrl based on it instead of using the last bank id enabled.

So switch to it, set the chained IRQ at runtime based on enabled banks
and wait only the number of enabled gpio controllers at probe time.

Cc: <stable@vger.kernel.org> # 3.18
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-26 09:13:36 +01:00
Beniamino Galvani
6ac7309511 pinctrl: add driver for Amlogic Meson SoCs
This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-26 09:13:00 +01:00
Anjana Sasindran
40b9e4fa75 staging: drivers: pinctrl: Fixed checkpatch.pl warnings
This patch fixes two checkpatch.pl warnings

WARNING: Error trailing white space
WARNING: MIssing blank line after declaration

Signed-off-by: Anjana Sasindran <anjanasasindran123@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-21 11:02:26 +01:00
Stephen Boyd
bcd53f858d pinctrl: qcom: Don't iterate past end of function array
Timur reports that this code crashes if nfunctions is 0. Fix the
loop iteration to only consider valid elements of the functions
array.

Reported-by: Timur Tabi <timur@codeaurora.org>
Cc: Pramod Gurav <pramod.gurav@smartplayin.com>
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Cc: Ivan T. Ivanov <iivanov@mm-sol.com>
Cc: Andy Gross <agross@codeaurora.org>
Fixes: 327455817a "pinctrl: qcom: Add support for reset for apq8064"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-19 11:17:45 +01:00
Padmavathi Venna
ac5a186ebe pinctrl: exynos: Add AUDIO pin controller for exynos7
Audio IPs on Exynos7 require gpios available in AUDIO
pin controller block. So adding the AUDIO pinctrl support.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-19 11:04:47 +01:00
Sergei Shtylyov
e29a4c3a1c sh-pfc: r8a7790: add MLB+ pin group
Add MLB+ 3-pin mode pin group to R8A7790 PFC driver.

Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15 17:36:22 +01:00
Sergei Shtylyov
8271ee96d1 sh-pfc: r8a7791: add MLB+ pin group
Add MLB+ 3-pin mode pin group to R8A7791 PFC driver.

Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15 17:10:56 +01:00
Sergei Shtylyov
87f27fe1a7 sh-pfc: r8a7791: fix typo in MLB_CLK
The R8A7791 manual sometimes calls the signal MLB_CLK and sometimes MLB_CK; the
latter can only be encountered in the PFC section and  is probably  just a typo
(this  signal is always called MLB_CLK in the R8A7790  manual). Fix occurences
of MLB_CK throughout the R8A7791 PFC driver.

Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15 17:07:28 +01:00
Barry Song
a17272a46c pinctrl: sirf: drop marco support
marco chip has been dropped, clear its support.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:54 +01:00
Krzysztof Kozlowski
63b5aed37b pinctrl: bcm281xx: Constify struct regmap_config
The regmap_config struct may be const because it is not modified by the
driver and regmap_init() accepts pointer to const. Make also
of_device_id array const.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:53 +01:00
Krzysztof Kozlowski
23259f19d0 pinctrl: dove: Constify struct regmap_config and of_device_id
The regmap_config struct may be const because it is not modified by the
driver and regmap_init() accepts pointer to const. Make also
of_device_id array const.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:53 +01:00
Hans de Goede
47cf4b326c pinctrl: sun6i: Add A31s pinctrl support
The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.

The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.

Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:52 +01:00
Hans de Goede
c5abe62b76 pinctrl: sun6i: Add some missing functions
While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:52 +01:00
Vivek Gautam
d171cd02f2 pinctrl: exynos: Add BUS1 pin controller for exynos7
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:51 +01:00
Linus Walleij
f684e4ac9f pinctrl: pinconf-generic: loose DT dependence
New pin controllers such as ACPI-based may also have custom properties
to parse, and should be able to use generic pin config. Let's make the
code compile on !OF systems and rename members a bit to underscore it
is custom parameters and not necessarily DT parameters.

This fixes a build regression for x86_64 on the zeroday kernel builds.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:21:38 +01:00
Johan Hovold
41f632fe17 pinctrl: lantiq: remove bogus of_gpio_chip_add
Remove bogus call to of_gpiochip_add (and of_gpio_chip remove in error
path) which is also called when adding the gpio chip.

This prevents adding the same pinctrl range twice.

Fixes: 3f8c50c9b1 ("OF: pinctrl: MIPS: lantiq: implement lantiq/xway
pinctrl support")

Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:20:46 +01:00
Jim Lin
db93facfb0 pinctrl: Fix two deadlocks
This patch is to fix two deadlock cases.
Deadlock 1:
CPU #1
 pinctrl_register-> pinctrl_get ->
 create_pinctrl
 (Holding lock pinctrl_maps_mutex)
 -> get_pinctrl_dev_from_devname
 (Trying to acquire lock pinctrldev_list_mutex)
CPU #0
 pinctrl_unregister
 (Holding lock pinctrldev_list_mutex)
 -> pinctrl_put ->> pinctrl_free ->
 pinctrl_dt_free_maps -> pinctrl_unregister_map
 (Trying to acquire lock pinctrl_maps_mutex)

Simply to say
CPU#1 is holding lock A and trying to acquire lock B,
CPU#0 is holding lock B and trying to acquire lock A.

Deadlock 2:
CPU #3
 pinctrl_register-> pinctrl_get ->
 create_pinctrl
 (Holding lock pinctrl_maps_mutex)
 -> get_pinctrl_dev_from_devname
 (Trying to acquire lock pinctrldev_list_mutex)
CPU #2
 pinctrl_unregister
 (Holding lock pctldev->mutex)
 -> pinctrl_put ->> pinctrl_free ->
 pinctrl_dt_free_maps -> pinctrl_unregister_map
 (Trying to acquire lock pinctrl_maps_mutex)
CPU #0
 tegra_gpio_request
 (Holding lock pinctrldev_list_mutex)
 -> pinctrl_get_device_gpio_range
 (Trying to acquire lock pctldev->mutex)

Simply to say
CPU#3 is holding lock A and trying to acquire lock D,
CPU#2 is holding lock B and trying to acquire lock A,
CPU#0 is holding lock D and trying to acquire lock B.

Cc: Stable <stable@vger.kernel.org>
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:20:33 +01:00
Doug Anderson
53b1bfc76d pinctrl: rockchip: Avoid losing interrupts when supporting both edges
I was seeing cases where I was losing interrupts when inserting and
removing SD cards.  Sometimes the card would get "stuck" in the
inserted state.

I believe that the problem was related to the code to handle the case
where we needed both rising and falling edges.  This code would
disable the interrupt as the polarity was switched.  If an interrupt
came at the wrong time it could be lost.

We'll match what the gpio-dwapb.c driver does upstream and change the
interrupt polarity without disabling things.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:20:32 +01:00
Soren Brinkmann
7382b62315 pinctrl: qcom-spmi-gpio: Migrate to pinconf-generic
Instead of the driver caring about implementation details like device
tree, just provide information about driver specific pinconf parameters
to pinconf-generic which takes care of parsing the DT.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-14 14:10:09 +01:00
Soren Brinkmann
add958cee9 pinctrl: Add driver for Zynq
This adds a pin-control driver for Zynq.

Changes since v2:
- driver-specific DT properties are passed to the core in two arrays,
  one for the actual DT parsing one for the debugfs representation.
  Issue a compiler warning when the number of entries is not the same
  for both arrays.

Changes since v1:
 - fix EMIO_SD1_CD pin name
 - add USB to pinmux options

changes since RFCv2:
 - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
   present in DT but no driver available.
 - add #defines to get rid of magical constants
 - add commas at end of initializers
 - separate changes in mach-zynq in separate patch
 - add driver specific io-standard DT property
 - refactored pinconf set function to not require arguments for
   argument-less properties
 - squash other patches in
   - support for IO-standard property
   - support for low-power mode property
   - migration to pinconf_generic_dt_node_to_map_all()
 - use newly created infrastructure to add pass driver-specific DT
   params to pinconf-generic

changes since RFC:
 - use syscon/regmap to access registers in SLCR space
 - rebase to 3.18: rename enable -> set_mux
 - add kernel-doc
 - support pinconf
   - supported attributes
     - pin-bias: pull up, tristate, disable
     - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
       argument

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-11 22:35:19 +01:00
Soren Brinkmann
dd4d01f7ba pinctrl: pinconf-generic: Allow driver to specify DT params
Additionally to the generic DT parameters, allow drivers to provide
driver-specific DT parameters to be used with the generic parser
infrastructure.

To achieve this 'struct pinctrl_desc' is extended to pass custom pinconf
option to the core. In order to pass this kind of information, the
related data structures - 'struct pinconf_generic_dt_params',
'pin_config_item' - are moved from pinconf internals to the
pinconf-generic header.

Additionally pinconfg-generic is refactored to not only iterate over the
generic pinconf parameters but also take the parameters into account
that are provided through the driver's 'struct pinctrl_desc'.
In particular 'pinconf_generic_parse_dt_config()' and
'pinconf_generic_dump' helpers are split into two parts each. In order
to have a more generic helper that can be used to process the generic
parameters as well as the driver-specific ones.

v2:
 - fix typo
 - add missing documentation for @conf_items member in struct
 - rebase to pinctrl/devel: conflict in abx500
 - rename _pinconf_generic_dump() to pinconf_generic_dump_one()
 - removed '_' from _parse_dt_cfg()
 - removed BUG_ONs, error condition is handled in if statements
 - removed pinconf_generic_dump_group() & pinconf_generic_dump_pin
   helpers
   - fixed up corresponding call sites
   - renamed pinconf_generic_dump() to pinconf_generic_dump_pins()
   - added kernel-doc to pinconf_generic_dump_pins()
 - add kernel-doc
 - more verbose commit message

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-11 22:32:19 +01:00
Soren Brinkmann
31c89c9596 pinctrl: pinconf-generic: Infer map type from DT property
With the new 'groups' property, the DT parser can infer the map type
from the fact whether 'pins' or 'groups' is used to specify the pin
group to work on.

To maintain backwards compatibitliy with current usage of the DT
binding, this is only done when PIN_MAP_TYPE_INVALID is passed to the
parsing function as type.

Also, a new helper 'pinconf_generic_dt_node_to_map_all()' is introduced,
which can be used by drivers as generic callback for dt_node_to_map() to
leverage the new feature.

Changes since v2:
 - rename dt_pin_specifier to subnode_target_type
 - add additional comment in header file explaining passing an invalid
   map type
 - mention map_all() helper in commit message
Changes since RFC v2:
 - none

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-11 22:30:04 +01:00
Linus Walleij
e2821bee40 pinctrl: pass -DDEBUG in subdirs
When drivers are compiled in subdirectories the -DDEBUG flag need
to be passed in the individual Makefiles.

Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Suggested-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-10 22:52:01 +01:00
Maxime Ripard
a95308d88c pinctrl: mvebu: a38x: Add UART1 muxing options
The MPP19 and MMP20 pins also have the ability to be muxed to the uart1
function.

Add this case to the pinctrl driver.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-10 22:47:23 +01:00
Wolfram Sang
1ee68af8a5 pinctrl: intel: drop owner assignment from platform_drivers
This platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-10 22:47:23 +01:00
Mika Westerberg
9eb457b547 pinctrl: cherryview: Save and restore pin configs over system sleep
Before resuming from system sleep BIOS restores its view of pin
configuration. If we have configured some pins differently from that, for
instance some driver requested a pin as a GPIO but it was not in GPIO mode
originally, our view of the pin configuration will not match the hardware
state anymore.

This patch saves the pin configuration and interrupt mask registers on
suspend and restores them on exit. This should make sure that the
previously configured state is still in effect.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-10 22:47:22 +01:00
Patrice CHOTARD
fce7fcc785 pinctrl: st: Add irq_disable hook to st_gpio_irqchip
Currently disable_irq() doesn't work for pinctrl-st driver, due to
missing irq_disable hook in the driver.
disable_irq() is required only for level-triggered interrupts, which
is not the case normally.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-07 10:44:39 +01:00
Francesco VIRLINZI
96d16c3088 pinctrl: st: avoid multiple mutex lock
Using the sysfs inteface to inspect the pins configuration
the system can walk around a path which acquires the same
mutex twice.

On STiH407 platform, for example :
cat /sys/kernel/debug/pinctrl/920f080.pin-controller-front0/pinconf-pins
hangs the kernel and never returns.

With this patch the mutex is temporary freed.

Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-07 10:43:41 +01:00
Doug Anderson
f2dd028c26 pinctrl: rockchip: Fix enable/disable/mask/unmask
The Rockchip pinctrl driver was only implementing the "mask" and
"unmask" operations though the hardware actually has two distinct
things: enable/disable and mask/unmask.  It was implementing the
"mask" operations as a hardware enable/disable and always leaving all
interrupts unmasked.

I believe that the old system had some downsides, specifically:
- (Untested) if an interrupt went off while interrupts were "masked"
  it would be lost.  Now it will be kept track of.
- If someone wanted to change an interrupt back into a GPIO (is such a
  thing sensible?) by calling irq_disable() it wouldn't actually take
  effect.  That's because Linux does some extra optimizations when
  there's no true "disable" function: it does a lazy mask.

Let's actually implement enable/disable/mask/unmask properly.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-30 13:17:27 +01:00
Doug Anderson
68bda47c57 pinctrl: rockchip: Handle wakeup pins
The rockchip pinctrl driver was using irq_gc_set_wake() as its
implementation of irq_set_wake() but was totally ignoring everything
that irq_gc_set_wake() did (which is to upkeep gc->wake_active).

Let's fix that by setting gc->wake_active as GPIO_INTEN at suspend
time and restoring GPIO_INTEN at resume time.

NOTE a few quirks when thinking about this patch:
- Rockchip pinctrl hardware supports both "disable/enable" and
  "mask/unmask".  Right now we only use "disable/enable" and present
  those to Linux as "mask/unmask".  This should be OK because
  enable/disable is optional and Linux will implement it in terms of
  mask/unmask.  At the moment we always tell hardware all interrupts
  are unmasked (the boot default).
- At suspend time Linux tries to call "disable" on all interrupts and
  also enables wakeup on all wakeup interrupts.  One would think that
  since "disable" is implemented as "mask" when "disable" isn't
  provided and that since we were ignoring gc->wake_active that
  nothing would have woken us up.  That's not the case since Linux
  "optimizes" things and just leaves interrutps unmasked, assuming it
  could mask them later when they go off.  That meant that at suspend
  time all interrupts were actually being left enabled.

With this patch random non-wakeup interrupts no longer wake the system
up.  Wakeup interrupts still wake the system up.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-30 13:17:27 +01:00
Linus Torvalds
e6b5be2be4 Driver core patches for 3.19-rc1
Here's the set of driver core patches for 3.19-rc1.
 
 They are dominated by the removal of the .owner field in platform
 drivers.  They touch a lot of files, but they are "simple" changes, just
 removing a line in a structure.
 
 Other than that, a few minor driver core and debugfs changes.  There are
 some ath9k patches coming in through this tree that have been acked by
 the wireless maintainers as they relied on the debugfs changes.
 
 Everything has been in linux-next for a while.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM
 53kAoLeteByQ3iVwWurwwseRPiWa8+MI
 =OVRS
 -----END PGP SIGNATURE-----

Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

Pull driver core update from Greg KH:
 "Here's the set of driver core patches for 3.19-rc1.

  They are dominated by the removal of the .owner field in platform
  drivers.  They touch a lot of files, but they are "simple" changes,
  just removing a line in a structure.

  Other than that, a few minor driver core and debugfs changes.  There
  are some ath9k patches coming in through this tree that have been
  acked by the wireless maintainers as they relied on the debugfs
  changes.

  Everything has been in linux-next for a while"

* tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
  Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
  fs: debugfs: add forward declaration for struct device type
  firmware class: Deletion of an unnecessary check before the function call "vunmap"
  firmware loader: fix hung task warning dump
  devcoredump: provide a one-way disable function
  device: Add dev_<level>_once variants
  ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
  ath: use seq_file api for ath9k debugfs files
  debugfs: add helper function to create device related seq_file
  drivers/base: cacheinfo: remove noisy error boot message
  Revert "core: platform: add warning if driver has no owner"
  drivers: base: support cpu cache information interface to userspace via sysfs
  drivers: base: add cpu_device_create to support per-cpu devices
  topology: replace custom attribute macros with standard DEVICE_ATTR*
  cpumask: factor out show_cpumap into separate helper function
  driver core: Fix unbalanced device reference in drivers_probe
  driver core: fix race with userland in device_add()
  sysfs/kernfs: make read requests on pre-alloc files use the buffer.
  sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
  fs: sysfs: return EGBIG on write if offset is larger than file size
  ...
2014-12-14 16:10:09 -08:00
Linus Torvalds
e7cf773d43 USB patches for 3.19-rc1
Here's the big set of USB and PHY patches for 3.19-rc1.
 
 The normal churn in the USB gadget area is in here, as well as xhci and
 other individual USB driver updates.  The PHY tree is also in here, as
 there were dependancies on the USB tree.
 
 All of these have been in linux-next.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iEYEABECAAYFAlSOEHcACgkQMUfUDdst+ykziQCgsm1D/af2nac6CTF2pov8VMIY
 ywgAnRi8LtZ2WassrwTNxY86Avaqryis
 =UVp8
 -----END PGP SIGNATURE-----

Merge tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB updates from Greg KH:
 "Here's the big set of USB and PHY patches for 3.19-rc1.

  The normal churn in the USB gadget area is in here, as well as xhci
  and other individual USB driver updates.  The PHY tree is also in
  here, as there were dependancies on the USB tree.

  All of these have been in linux-next"

* tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (351 commits)
  arm: omap3: twl: remove usb phy init data
  usbip: fix error handling in stub_probe()
  usb: gadget: udc: missing curly braces
  USB: mos7720: delete some unneeded code
  wusb: replace memset by memzero_explicit
  usbip: remove unneeded structure
  usb: xhci: fix comment for PORT_DEV_REMOVE
  xhci: don't use the same variable for stopped and halted rings current TD
  xhci: clear extra bits from slot context when setting max exit latency
  xhci: cleanup finish_td function
  USB: adutux: NULL dereferences on disconnect
  usb: chipidea: fix platform_no_drv_owner.cocci warnings
  usb: chipidea: Fixed a few typos in comments
  Documentation: bindings: add doc for the USB2 ChipIdea USB driver
  usb: chipidea: add a usb2 driver for ci13xxx
  usb: chipidea: fix phy handling
  usb: chipidea: remove duplicate dev_set_drvdata for host_start
  usb: chipidea: parameter 'mode' isn't needed for hw_device_reset
  usb: chipidea: add controller reset API
  usb: chipidea: remove flag CI_HDRC_REQUIRE_TRANSCEIVER
  ...
2014-12-14 14:57:16 -08:00
Linus Torvalds
980f3c344f This is the bulk of GPIO changes for the v3.19 series:
- A new API that allows setting more than one GPIO at the
   time. This is implemented for the new descriptor-based
   API only and makes it possible to e.g. toggle a clock and
   data line at the same time, if the hardware can do this
   with a single register write. Both consumers and drivers
   need new calls, and the core will fall back to driving
   individual lines where needed. Implemented for the MPC8xxx
   driver initially.
 - Patched the mdio-mux-gpio and the serial mctrl driver
   that drives modems to use the new multiple-setting API
   to set several signals simultaneously.
 - Get rid of the global GPIO descriptor array, and instead
   allocate descriptors dynamically for each GPIO on a certain
   GPIO chip. This moves us closer to getting rid of the
   limitation of using the global, static GPIO numberspace.
 - New driver and device tree bindings for 74xx ICs.
 - New driver and device tree bindings for the VF610 Vybrid.
 - Support the RCAR r8a7793 and r8a7794.
 - Guidelines for GPIO device tree bindings trying to get
   things a bit more strict with the advent of combined
   device properties.
 - Suspend/resume support for the MVEBU driver.
 - A slew of minor fixes and improvements.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUjgQ7AAoJEEEQszewGV1zuJ8P+wamlDNhJbsgqXPcSCZZFgeP
 1O22VRYqoo/i8mAzNCRi2h6NogO9Da6rCRhHdH35TsuNzIbusHE+btMukj248qJ7
 WYOf25I0ImyUP8kulogW4/+7lYibRLHnN2BSLuAkApofmxDvODPS1KNWHulcOcxl
 VaVsA8wvFzQO1s1Wjv94ctVfs5rqk7mBfPwk61zHuLeETecmKg0e52p0Uzqlq6gi
 UKi9uK3sjQ7kI/+xa+qDrF9GRwRR22oJfD/9zNj8g94iU9iMs5Oh+Zp3RJcvYUSD
 y5BIb+IY2ATy20ZkijWmeP8LJz6pja+C9Ne7lKM0jkv7geGeHGAoavz0n3oUq4oz
 IvUNz6hCAP9PcxWc5a9FFqqORLWrRew6GmZmJvIkmC9K+3UQcWhkzO3vLpfl6Q9h
 S728XexkIlhxG9NcER21bFXV2dw3z/X9dm5mQ473TqJm+wQmRuYcPRg053NbqMcx
 juvkweCksx8qlpnjo/1QXQcVwFM8kuR7xAlVo7zdMDOU5F8pdxRnsTl0cUdx5cPv
 DKeMRg8+FYcHmIoe/EodemIh7cAZtEpijZNNAr9cDmAjifeBjWhCb+zri5SIc96x
 0jKVTXyY4jnHXBVoA0FIl1d2t54yVjh3PYiu0MjeLJ9tyB+Px/nOxW8FrdlFnPJ/
 oP5WK13c8h3bMkxUzsvL
 =ZAhA
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v3.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull take two of the GPIO updates:
 "Same stuff as last time, now with a fixup patch for the previous
  compile error plus I ran a few extra rounds of compile-testing.

  This is the bulk of GPIO changes for the v3.19 series:

   - A new API that allows setting more than one GPIO at the time.  This
     is implemented for the new descriptor-based API only and makes it
     possible to e.g. toggle a clock and data line at the same time, if
     the hardware can do this with a single register write.  Both
     consumers and drivers need new calls, and the core will fall back
     to driving individual lines where needed.  Implemented for the
     MPC8xxx driver initially

   - Patched the mdio-mux-gpio and the serial mctrl driver that drives
     modems to use the new multiple-setting API to set several signals
     simultaneously

   - Get rid of the global GPIO descriptor array, and instead allocate
     descriptors dynamically for each GPIO on a certain GPIO chip.  This
     moves us closer to getting rid of the limitation of using the
     global, static GPIO numberspace

   - New driver and device tree bindings for 74xx ICs

   - New driver and device tree bindings for the VF610 Vybrid

   - Support the RCAR r8a7793 and r8a7794

   - Guidelines for GPIO device tree bindings trying to get things a bit
     more strict with the advent of combined device properties

   - Suspend/resume support for the MVEBU driver

   - A slew of minor fixes and improvements"

* tag 'gpio-v3.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (33 commits)
  gpio: mcp23s08: fix up compilation error
  gpio: pl061: document gpio-ranges property for bindings file
  gpio: pl061: hook request if gpio-ranges avaiable
  gpio: mcp23s08: Add option to configure IRQ output polarity as active high
  gpio: fix deferred probe detection for legacy API
  serial: mctrl_gpio: use gpiod_set_array function
  mdio-mux-gpio: Use GPIO descriptor interface and new gpiod_set_array function
  gpio: remove const modifier from gpiod_get_direction()
  gpio: remove gpio_descs global array
  gpio: mxs: implement get_direction callback
  gpio: em: Use dynamic allocation of GPIOs
  gpio: Check if base is positive before calling gpio_is_valid()
  gpio: mcp23s08: Add simple IRQ support for SPI devices
  gpio: mcp23s08: request a shared interrupt
  gpio: mcp23s08: Do not free unrequested interrupt
  gpio: rcar: Add r8a7793 and r8a7794 support
  gpio-mpc8xxx: add mpc8xxx_gpio_set_multiple function
  gpiolib: allow simultaneous setting of multiple GPIO outputs
  gpio: mvebu: add suspend/resume support
  gpio: gpio-davinci: remove duplicate check on resource
  ..
2014-12-14 14:05:05 -08:00
Linus Torvalds
a7cb7bb664 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree update from Jiri Kosina:
 "Usual stuff: documentation updates, printk() fixes, etc"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (24 commits)
  intel_ips: fix a type in error message
  cpufreq: cpufreq-dt: Move newline to end of error message
  ps3rom: fix error return code
  treewide: fix typo in printk and Kconfig
  ARM: dts: bcm63138: change "interupts" to "interrupts"
  Replace mentions of "list_struct" to "list_head"
  kernel: trace: fix printk message
  scsi: mpt2sas: fix ioctl in comment
  zbud, zswap: change module author email
  clocksource: Fix 'clcoksource' typo in comment
  arm: fix wording of "Crotex" in CONFIG_ARCH_EXYNOS3 help
  gpio: msm-v1: make boolean argument more obvious
  usb: Fix typo in usb-serial-simple.c
  PCI: Fix comment typo 'COMFIG_PM_OPS'
  powerpc: Fix comment typo 'CONIFG_8xx'
  powerpc: Fix comment typos 'CONFiG_ALTIVEC'
  clk: st: Spelling s/stucture/structure/
  isci: Spelling s/stucture/structure/
  usb: gadget: zero: Spelling s/infrastucture/infrastructure/
  treewide: Fix company name in module descriptions
  ...
2014-12-12 10:08:06 -08:00
Linus Torvalds
c1b30e4d94 Pin control changes for the v3.19 series:
- Force conversion of the ux500 pin control device trees
   and parsers to use the generic pin control bindings.
 - New driver and device tree bindings for the Qualcomm
   PMIC MPP pin controller and GPIO.
 - Some ACPI infrastructure for pin controllers.
 - New driver for the Intel CherryView/Braswell pin controller,
   the first Intel pin controller to fully take advantage of
   the pin control subsystem.
 - Support the Freescale i.MX VF610 variant.
 - Support the sunxi A80 variant.
 - Support the Samsung Exynos 4415 and Exynos 7 variants.
 - Split out Intel pin controllers to their own subdirectory.
 - A large slew of rockchip pin control updates, including
   suspend/resume support.
 - A large slew of Samsung Exynos pin controller updates.
 - Various minor updates and fixes.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUhrHUAAoJEEEQszewGV1zPZsQAMzWjGKcZhyBDWyTsHM/E9nN
 csRIcVdXs+OggH0nr2YNm2AAh+nRlp4DAQCB7S83SLfKFHF4oWT8SlornEl7WKdN
 zcVUbV29LtHkotjtVoGQZmjuJx+uvHlWJt7moTKJsAMTeNyXv25jEp0LGETji24A
 xsIQ+Bp+G9IYZqK1dlJFPva1YMjjt9sBhJqKnOhh5Z+wjj3YdT7z5LW1x001GPju
 kwKumgxOL7qKjvyaI7n2z+9VhGu9zAvoxK2gLOgjgtFQODASLS/gk2oCuRi/fIpn
 RqE+YyfrNSeMKpOjZOXc/R0SRtOkhyvMBYbgQrAX04nio4pbT6x2XgclAe6v7O5Q
 T3GmOR2JZblwrzEPRs5mGBC9p7fd488ToHAPg5ojNH5F70hDkC8wSYYJZmaL+ORw
 umyxRlRjIbQ4vs6cZMlz/NksqpQyqCTMuBRLllo/jsSQlk0Vo3Gdci5J/T10lKd2
 ciX6AxlRKaRyRo+W6/i01xcX7SzzmNZoOCMXWSjsPv7Th+Gm7vIKyVeNOUkiqUXH
 1fVjw/M0AhIttVRbx1qTPsqFaDI/WPPk9EUvVm3W7DFuf0/w9B0HkZe6KpXdp33K
 GV6gEMvmTObvUpwYrYEi7hhKVl+cJ902ZMR/LSmK0QdADhI98pjsokDrigl+Jy93
 U1OepT70fw4mgJnqnevZ
 =sxpe
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:
 "Here is a stash of pin control changes I have collected for the v3.19
  series.  Mainly new hardware support, with Intels new embedded SoC as
  the especially interesting thing standing out, fully using the
  subsystem.

   - Force conversion of the ux500 pin control device trees and parsers
     to use the generic pin control bindings.
   - New driver and device tree bindings for the Qualcomm PMIC MPP pin
     controller and GPIO.
   - Some ACPI infrastructure for pin controllers.
   - New driver for the Intel CherryView/Braswell pin controller, the
     first Intel pin controller to fully take advantage of the pin
     control subsystem.
   - Support the Freescale i.MX VF610 variant.
   - Support the sunxi A80 variant.
   - Support the Samsung Exynos 4415 and Exynos 7 variants.
   - Split out Intel pin controllers to their own subdirectory.
   - A large slew of rockchip pin control updates, including
     suspend/resume support.
   - A large slew of Samsung Exynos pin controller updates.
   - Various minor updates and fixes"

* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
  pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
  pinctrl: meson: add device tree bindings documentation
  gpio: tz1090: Fix error handling of irq_of_parse_and_map
  pinctrl: tz1090-pinctrl.txt: Fix typo in binding
  pinctrl: pinconf-generic: Declare dt_params/conf_items const
  pinctrl: exynos: Add support for Exynos4415
  pinctrl: exynos: Add initial driver data for Exynos7
  pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
  pinctrl: exynos: Consolidate irq domain callbacks
  pinctrl: exynos: Generalize the eint16_31 demux code
  pinctrl: samsung: Separate per-bank init and runtime data
  pinctrl: samsung: Constify samsung_pin_ctrl struct
  pinctrl: samsung: Constify samsung_pin_bank_type struct
  pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
  pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
  pinctrl: Add Intel Cherryview/Braswell pin controller support
  gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
  pinctrl: Fix path error in documentation
  pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
  pinctrl: rockchip: add suspend/resume functions
  ...
2014-12-11 10:43:14 -08:00
Matthieu Crapet
853b6bf044 pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
When a pin is configured as GPIO, print also direction (input or output).

Signed-off-by: Matthieu Crapet <mcrapet@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-03 12:23:10 +01:00
Heikki Krogerus
dbc98635e0 phy: remove the old lookup method
The users of the old method are now converted to the new one.

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
[ kishon@ti.com : made phy-berlin-usb.c and phy-miphy28lp.c to use the updated
		  devm_phy_create API.]
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2014-11-22 13:58:39 +05:30
Jiri Kosina
a02001086b Merge Linus' tree to be be to apply submitted patches to newer code than
current trivial.git base
2014-11-20 14:42:02 +01:00
Soren Brinkmann
2500bcc9da pinctrl: pinconf-generic: Declare dt_params/conf_items const
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-11-11 13:00:25 +01:00
Tomasz Figa
2891ba2906 pinctrl: exynos: Add support for Exynos4415
The pin controllers of Exynos4415 are similar to Exynos4412, but certain
differences cause the need to create separate driver data for it. This
patch adds pin controller and bank descriptor arrays to the driver to
support the new SoC.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
[cw00.choi: Rebase it on mainline kernel]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
[tomasz.figa@gmail.com: Resolved merge with earlier clean-up series.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-11-09 22:28:07 +09:00