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linux/drivers/reset/Kconfig

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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 12:07:45 +00:00
# SPDX-License-Identifier: GPL-2.0-only
reset: Add reset controller API This adds a simple API for devices to request being reset by separate reset controller hardware and implements the reset signal device tree binding. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz>
2012-11-19 16:23:13 +00:00
config ARCH_HAS_RESET_CONTROLLER
bool
menuconfig RESET_CONTROLLER
bool "Reset Controller Support"
default y if ARCH_HAS_RESET_CONTROLLER
help
Generic Reset Controller support.
This framework is designed to abstract reset handling of devices
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
drivers: reset: STi SoC system configuration reset controller support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. System configuration registers are accessed through the regmap framework and the mfd/syscon driver. The implementation optionally supports waiting for the reset action to be acknowledged in a separate status register and supports both active high and active low reset lines. These properties are common across all the reset channels in a specific reset controller instance, hence all channels in a paritcular controller are expected to behave in the same way. Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-08-07 14:53:12 +00:00
reset: fix Kconfig menu to include reset drivers in sub-menu In "make menuconfig", reset drivers are currently lined up together with the reset sub-system menu, like this: -*- Reset Controller Support ---- < > Hi6220 Reset Driver (It also means, the menu "Reset Controller Support" is always empty.) "Hi6220 Reset Driver" should go into the sub-menu of the "Reset Controller Support". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-03 06:29:52 +00:00
if RESET_CONTROLLER
reset: Add Altera Arria10 SR Reset Controller This patch adds the reset controller functionality for Peripheral PHYs to the Arria10 System Resource Chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-22 17:10:17 +00:00
config RESET_A10SR
tristate "Altera Arria10 System Resource Reset"
reset: a10sr: allow building under COMPILE_TEST This driver can be built under COMPILE_TEST. Allow it. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220711130624.1217599-1-p.zabel@pengutronix.de
2022-07-11 13:06:24 +00:00
depends on MFD_ALTERA_A10SR || COMPILE_TEST
reset: Add Altera Arria10 SR Reset Controller This patch adds the reset controller functionality for Peripheral PHYs to the Arria10 System Resource Chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-22 17:10:17 +00:00
help
This option enables support for the external reset functions for
peripheral PHYs on the Altera Arria10 System Resource Chip.
reset: ath79: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Acked-by: Aban Bedel <albeu@free.fr> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:30:08 +00:00
config RESET_ATH79
bool "AR71xx Reset Driver" if COMPILE_TEST
default ATH79
help
This enables the ATH79 reset controller driver that supports the
AR71xx SoC reset controller.
ARC: reset: introduce AXS10x reset driver ARC AXS10x boards support custom IP-block which allows to control reset signals of selected peripherals. For example DW GMAC, etc... This block is controlled via memory-mapped register (AKA CREG) which represents up-to 32 reset lines. This regiter is self-clearing so we don't need to deassert line after reset. As of today only the following lines are used: - DW GMAC - line 5 Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-14 14:28:42 +00:00
config RESET_AXS10X
bool "AXS10x Reset Driver" if COMPILE_TEST
default ARC_PLAT_AXS10X
help
This enables the reset controller driver for AXS10x.
reset: add BCM6345 reset controller driver Add support for resetting blocks through the Linux reset controller subsystem for BCM63xx SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <F.fainelli@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-06-17 10:50:35 +00:00
config RESET_BCM6345
bool "BCM6345 Reset Controller"
depends on BMIPS_GENERIC || COMPILE_TEST
default BMIPS_GENERIC
help
This enables the reset controller driver for BCM6345 SoCs.
reset: berlin: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:31:12 +00:00
config RESET_BERLIN
reset: berlin: support module build Make reset-berlin driver to be tristate module, support to build as a module, this is useful for GKI. Partially reverts commit ed4dba99cae8 ("reset: berlin: make it explicitly non-modular") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20210607181015.5b8d3711@xhacker.debian Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-06-07 10:10:15 +00:00
tristate "Berlin Reset Driver"
depends on ARCH_BERLIN || COMPILE_TEST
default m if ARCH_BERLIN
reset: berlin: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:31:12 +00:00
help
This enables the reset controller driver for Marvell Berlin SoCs.
reset: Add Broadcom STB SW_INIT reset controller driver Add support for resetting blocks through the Linux reset controller subsystem when reset lines are provided through a SW_INIT-style reset controller on Broadcom STB SoCs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-23 22:54:36 +00:00
config RESET_BRCMSTB
tristate "Broadcom STB reset controller"
depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB
help
This enables the reset controller driver for Broadcom STB SoCs using
a SUN_TOP_CTRL_SW_INIT style controller.
reset: Add Broadcom STB RESCAL reset controller On BCM7216 there is a special purpose reset controller named RESCAL (reset calibration) which is necessary for SATA and PCIe0/1 to operate correctly. This commit adds support for such a reset controller to be available. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-03 19:04:29 +00:00
config RESET_BRCMSTB_RESCAL
reset: Allow building Broadcom STB RESCAL as module The driver can be built as a module and uses device managed resources. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210924030840.9650-1-f.fainelli@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-09-24 03:08:40 +00:00
tristate "Broadcom STB RESCAL reset controller"
reset: brcmstb-rescal: add unspecified HAS_IOMEM dependency Currently CONFIG_RESET_BRCMSTB_RESCAL=y implicitly depends on CONFIG_HAS_IOMEM=y; consequently, on architectures without IOMEM we get the following build error: /usr/bin/ld: drivers/reset/reset-brcmstb-rescal.o: in function `brcm_rescal_reset_probe': drivers/reset/reset-brcmstb-rescal.c:76: undefined reference to `devm_ioremap_resource' Fix the build error by adding the unspecified dependency. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-27 23:53:53 +00:00
depends on HAS_IOMEM
reset: RESET_BRCMSTB_RESCAL should depend on ARCH_BRCMSTB The Broadcom STB RESCAL reset controller is only present on Broadcom BCM7216 platforms. Hence add a dependency on ARCH_BRCMSTB, to prevent asking the user about this driver when configuring a kernel without BCM7216 support. Also, merely enabling CONFIG_COMPILE_TEST should not enable additional code, and thus should not enable this driver by default. Fixes: 4cf176e52397853e ("reset: Add Broadcom STB RESCAL reset controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-03-16 13:37:33 +00:00
depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB
reset: Add Broadcom STB RESCAL reset controller On BCM7216 there is a special purpose reset controller named RESCAL (reset calibration) which is necessary for SATA and PCIe0/1 to operate correctly. This commit adds support for such a reset controller to be available. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-03 19:04:29 +00:00
help
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
BCM7216.
reset: eyeq: add platform driver Add Mobileye EyeQ reset controller driver, for EyeQ5, EyeQ6L and EyeQ6H SoCs. Instances belong to a shared register region called OLB and gets spawned as auxiliary device to the platform driver for clock. There is one OLB instance for EyeQ5 and EyeQ6L. There are seven OLB instances on EyeQ6H; three have a reset controller embedded: - West and east get handled by the same compatible. - Acc (accelerator) is another one. Each instance vary in the number and types of reset domains. Instances with single domain expect a single cell, others two. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20240730-mbly-reset-v2-2-00b870a6a2ff@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-07-30 16:06:23 +00:00
config RESET_EYEQ
bool "Mobileye EyeQ reset controller"
depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
select AUXILIARY_BUS
default MACH_EYEQ5 || MACH_EYEQ6H
help
This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
and EyeQ6H SoCs.
It has one or more domains, with a varying number of resets in each.
Registers are located in a shared register region called OLB. EyeQ6H
has multiple reset instances.
reset: gpio: Add GPIO-based reset controller Add a simple driver to control GPIO-based resets using the reset controller API for the cases when the GPIOs are shared and reset should be coordinated. The driver is expected to be used by reset core framework for ad-hoc reset controllers. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240129115216.96479-4-krzysztof.kozlowski@linaro.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-01-29 11:52:13 +00:00
config RESET_GPIO
tristate "GPIO reset controller"
reset: gpio: Fix missing gpiolib dependency for GPIO reset controller The GPIO reset controller uses gpiolib but there is no Kconfig dependency reflecting this fact, add one. With the addition of the controller to the arm64 defconfig this is causing build breaks for arm64 virtconfig in -next: aarch64-linux-gnu-ld: drivers/reset/core.o: in function `__reset_add_reset_gpio_lookup': /build/stage/linux/drivers/reset/core.c:861:(.text+0xccc): undefined reference to `gpio_device_find_by_fwnode' Fixes: cee544a40e44 ("reset: gpio: Add GPIO-based reset controller") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240325-reset-gpiolib-deps-v2-1-3ed2517f5f53@kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-03-25 16:51:03 +00:00
depends on GPIOLIB
reset: gpio: Add GPIO-based reset controller Add a simple driver to control GPIO-based resets using the reset controller API for the cases when the GPIOs are shared and reset should be coordinated. The driver is expected to be used by reset core framework for ad-hoc reset controllers. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240129115216.96479-4-krzysztof.kozlowski@linaro.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-01-29 11:52:13 +00:00
help
This enables a generic reset controller for resets attached via
GPIOs. Typically for OF platforms this driver expects "reset-gpios"
property.
If compiled as module, it will be called reset-gpio.
ARC: reset: remove the misleading v1 suffix all over There is no plan yet to do a v2 board. And even if we were to do it only some IPs would actually change, so it be best to add suffixes at that point, not now ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-08-31 18:06:07 +00:00
config RESET_HSDK
bool "Synopsys HSDK Reset Driver"
ARC: reset: Only build on archs that have IOMEM This avoids the error: drivers/reset/reset-hsdk-v1.o: In function `hsdkv1_reset_probe': /home/thomas/git/linux/drivers/reset/reset-hsdk-v1.c:101: undefined reference to `devm_ioremap_resource' collect2: error: ld returned 1 exit status Signed-off-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-09 04:02:46 +00:00
depends on HAS_IOMEM
reset: Restrict RESET_HSDK to ARC_SOC_HSDK or COMPILE_TEST The HSDK reset driver is only useful when building for an ARC HSDK platform. While at it, drop the "default n", as that is the default. Fixes: e0be864f14240cb1 ("ARC: reset: introduce HSDKv1 reset driver") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> [p.zabel@pengutronix.de: rebased, renamed RESET_HSDK_V1 to RESET_HSDK] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-11 12:22:08 +00:00
depends on ARC_SOC_HSDK || COMPILE_TEST
ARC: reset: introduce HSDKv1 reset driver The HSDK v1 periphery IPs can be reset by accessing some registers from the CGU block. The list of available reset lines is documented in the DT bindings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-19 18:45:11 +00:00
help
ARC: reset: remove the misleading v1 suffix all over There is no plan yet to do a v2 board. And even if we were to do it only some IPs would actually change, so it be best to add suffixes at that point, not now ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-08-31 18:06:07 +00:00
This enables the reset controller driver for HSDK board.
ARC: reset: introduce HSDKv1 reset driver The HSDK v1 periphery IPs can be reset by accessing some registers from the CGU block. The list of available reset lines is documented in the DT bindings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-19 18:45:11 +00:00
reset: Add i.MX7 SRC reset driver Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-21 16:13:31 +00:00
config RESET_IMX7
reset: imx7: Support module build Use module_platform_driver(), add module device table, author, description and license to support module build, and CONFIG_RESET_IMX7 is changed to default 'y' ONLY for i.MX7D, other platforms need to select it in defconfig. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-07-20 14:21:59 +00:00
tristate "i.MX7/8 Reset Driver"
reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency This config select's MFD_SYSCON, but does not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-03-06 11:15:11 +00:00
depends on HAS_IOMEM
reset: imx7: Support module build Use module_platform_driver(), add module device table, author, description and license to support module build, and CONFIG_RESET_IMX7 is changed to default 'y' ONLY for i.MX7D, other platforms need to select it in defconfig. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-07-20 14:21:59 +00:00
depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
default y if SOC_IMX7D
reset: Add i.MX7 SRC reset driver Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-21 16:13:31 +00:00
select MFD_SYSCON
help
This enables the reset controller driver for i.MX7 SoCs.
reset: imx8mp-audiomix: Add AudioMix Block Control reset driver Add support for the resets on i.MX8MP Audio Block Control module, which includes the EARC PHY software reset and EARC controller software reset. The reset controller is created using the auxiliary device framework and set up in the clock driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1719200345-32006-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-24 03:39:05 +00:00
config RESET_IMX8MP_AUDIOMIX
tristate "i.MX8MP AudioMix Reset Driver"
reset: RESET_IMX8MP_AUDIOMIX should depend on ARCH_MXC The i.MX8MP AudioMix reset controller is only present on Freescale i.MX8 SoCs. Hence add a dependency on ARCH_MXC, to prevent asking the user about this driver when configuring a kernel without i.MX SoC support. Fixes: fe125601d17cc1ea ("reset: imx8mp-audiomix: Add AudioMix Block Control reset driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/6d8116a56186fbf468229e823c7c8dfcd9488959.1719316665.git.geert+renesas@glider.be Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-25 11:57:48 +00:00
depends on ARCH_MXC || COMPILE_TEST
reset: imx8mp-audiomix: Add AudioMix Block Control reset driver Add support for the resets on i.MX8MP Audio Block Control module, which includes the EARC PHY software reset and EARC controller software reset. The reset controller is created using the auxiliary device framework and set up in the clock driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1719200345-32006-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-24 03:39:05 +00:00
select AUXILIARY_BUS
default CLK_IMX8MP
help
This enables the reset controller driver for i.MX8MP AudioMix
reset: intel: Add system reset controller driver Add driver for the reset controller present on Intel Gateway SoCs for performing reset management of the devices present on the SoC. Driver also registers a reset handler to peform the entire device reset. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-03 10:00:18 +00:00
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
reset: RESET_INTEL_GW should depend on X86 The Intel Gateway reset controller is only present on Intel Gateway platforms. Hence add a dependency on X86, to prevent asking the user about this driver when configuring a kernel without Intel Gateway support. Fixes: c9aef213e38cde27 ("reset: intel: Add system reset controller driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-03-31 08:15:19 +00:00
depends on X86 || COMPILE_TEST
reset: intel: add unspecified HAS_IOMEM dependency Currently CONFIG_RESET_INTEL_GW=y implicitly depends on CONFIG_HAS_IOMEM=y; consequently, on architectures without IOMEM we get the following build error: /usr/bin/ld: drivers/reset/reset-intel-gw.o: in function `intel_reset_probe': drivers/reset/reset-intel-gw.c:185: undefined reference to `devm_platform_ioremap_resource' Fix the build error by adding the unspecified dependency. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-27 23:53:54 +00:00
depends on OF && HAS_IOMEM
reset: intel: Add system reset controller driver Add driver for the reset controller present on Intel Gateway SoCs for performing reset management of the devices present on the SoC. Driver also registers a reset handler to peform the entire device reset. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-03 10:00:18 +00:00
select REGMAP_MMIO
help
This enables the reset controller driver for Intel Gateway SoCs.
Say Y to control the reset signals provided by reset controller.
Otherwise, say N.
riscv: Add Canaan Kendryte K210 reset controller Add a reset controller driver for the Canaan Kendryte K210 SoC. This driver relies on its syscon compatible parent node (sysctl) for its register mapping. Default this driver compilation to y when the SOC_CANAAN option is selected. The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER" with myself listed as maintainer for this driver. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-12-13 13:50:47 +00:00
config RESET_K210
bool "Reset controller driver for Canaan Kendryte K210 SoC"
reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4,5], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ [5] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-28 17:06:13 +00:00
depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
riscv: Add Canaan Kendryte K210 reset controller Add a reset controller driver for the Canaan Kendryte K210 SoC. This driver relies on its syscon compatible parent node (sysctl) for its register mapping. Default this driver compilation to y when the SOC_CANAAN option is selected. The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER" with myself listed as maintainer for this driver. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-12-13 13:50:47 +00:00
select MFD_SYSCON
reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4,5], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ [5] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-28 17:06:13 +00:00
default SOC_CANAAN_K210
riscv: Add Canaan Kendryte K210 reset controller Add a reset controller driver for the Canaan Kendryte K210 SoC. This driver relies on its syscon compatible parent node (sysctl) for its register mapping. Default this driver compilation to y when the SOC_CANAAN option is selected. The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER" with myself listed as maintainer for this driver. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-12-13 13:50:47 +00:00
help
Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
Say Y if you want to control reset signals provided by this
controller.
reset: Add a reset controller driver for the Lantiq XWAY based SoCs The reset controllers (on xRX200 and newer SoCs have two of them) are provided by the RCU module. This was initially implemented as a simple reset controller. However, the RCU module provides more functionality (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device. The old reset controller driver implementation from arch/mips/lantiq/xway/reset.c did not honor this fact. For some devices the request and the status bits are different. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Cc: john@phrozen.org Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17125/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-19 22:18:17 +00:00
config RESET_LANTIQ
bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
default SOC_TYPE_XWAY
help
This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
reset: lpc18xx: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Acked-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:32:01 +00:00
config RESET_LPC18XX
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
default ARCH_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
reset: mchp: sparx5: add switch reset driver The Sparx5 Switch SoC has a number of components that can be reset indiviually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-04-16 08:40:53 +00:00
config RESET_MCHP_SPARX5
reset: mchp: sparx5: Allow building as a module This reset controller can be used by the LAN966x PCI device. The LAN966x PCI device driver can be built as a module and this reset controller driver has no reason to be a builtin driver in that case. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20241014124636.24221-6-herve.codina@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-10-14 12:46:34 +00:00
tristate "Microchip Sparx5 reset driver"
reset: mchp: sparx5: Add MCHP_LAN966X_PCI dependency The sparx5 reset controller depends on the SPARX5 architecture or the LAN966x SoC. This reset controller can be used by the LAN966x PCI device and so it needs to be available when the LAN966x PCI device is enabled. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20241014124636.24221-5-herve.codina@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-10-14 12:46:33 +00:00
depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
reset: mchp: sparx5: add switch reset driver The Sparx5 Switch SoC has a number of components that can be reset indiviually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-04-16 08:40:53 +00:00
default y if SPARX5_SWITCH
select MFD_SYSCON
help
This driver supports switch core reset for the Microchip Sparx5 SoC.
reset: npcm: add NPCM reset controller driver Add Nuvoton NPCM BMC reset controller driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-11-06 14:53:31 +00:00
config RESET_NPCM
bool "NPCM BMC Reset Driver" if COMPILE_TEST
default ARCH_NPCM
reset: npcm: register npcm8xx clock auxiliary bus device Add NPCM8xx clock controller auxiliary bus device registration. The NPCM8xx clock controller is registered as an aux device because the reset and the clock controller share the same register region. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Benjamin Fair <benjaminfair@google.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240912191038.981105-3-tmaimon77@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-12 19:10:37 +00:00
select AUXILIARY_BUS
reset: npcm: add NPCM reset controller driver Add Nuvoton NPCM BMC reset controller driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-11-06 14:53:31 +00:00
help
This enables the reset controller driver for Nuvoton NPCM
BMC SoCs.
reset: Add Nuvoton ma35d1 reset driver support This driver supports individual IP reset for the MA35D1. The reset control registers are a subset of the system control registers. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-05 04:07:48 +00:00
config RESET_NUVOTON_MA35D1
reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35 The Nuvoton MA35D1 reset controller is only present on Nuvoton MA35 SoCs. Hence add a dependency on ARCH_MA35, to prevent asking the user about this driver when configuring a kernel without MA35 SoC support. Also, do not enable the driver by default when merely compile-testing. While at it, fix a misspelling of "Nuvoton". Fixes: e4bb55d6ccf0f774 ("reset: Add Nuvoton ma35d1 reset driver support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-06 09:55:42 +00:00
bool "Nuvoton MA35D1 Reset Driver"
depends on ARCH_MA35 || COMPILE_TEST
default ARCH_MA35
reset: Add Nuvoton ma35d1 reset driver support This driver supports individual IP reset for the MA35D1. The reset control registers are a subset of the system control registers. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-05 04:07:48 +00:00
help
This enables the reset controller driver for Nuvoton MA35D1 SoC.
reset: pistachio: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Damien Horsley <Damien.Horsley@imgtec.com> Acked-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:33:07 +00:00
config RESET_PISTACHIO
reset: pistachio: Re-enable driver selection After the retirement of MACH_PISTACHIO, the Pistachio Reset Driver is no longer auto-enabled when building a kernel for Pistachio systems. Worse, the driver cannot be enabled by the user at all (unless compile-testing), as the config symbol is invisible. Fix this partially by making the symbol visible again when compiling for MIPS, and dropping the useless default. The user still has to enable the driver manually when building a kernel for Pistachio systems, though. Fixes: 104f942b2832ab13 ("MIPS: Retire MACH_PISTACHIO") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rahul Bedarkar <rahulbedarkar89@gmail.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lore.kernel.org/r/2c399e52540536df9c4006e46ef93fbccdde88db.1631610825.git.geert+renesas@glider.be Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-09-14 09:15:59 +00:00
bool "Pistachio Reset Driver"
depends on MIPS || COMPILE_TEST
reset: pistachio: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Damien Horsley <Damien.Horsley@imgtec.com> Acked-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:33:07 +00:00
help
This enables the reset driver for ImgTec Pistachio SoCs.
reset: add polarfire soc reset support Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
2022-09-09 12:31:14 +00:00
config RESET_POLARFIRE_SOC
bool "Microchip PolarFire SoC (MPFS) Reset Driver"
reset: mpfs: select AUXILIARY_BUS CONFIG_AUXILIARY_BUS is not a user-visible symbol, replace 'depends on' with 'select'. Cc: Daire McNamara <daire.mcnamara@microchip.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230502102041.1418397-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2023-05-02 10:20:41 +00:00
depends on MCHP_CLK_MPFS
select AUXILIARY_BUS
reset: add polarfire soc reset support Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
2022-09-09 12:31:14 +00:00
default MCHP_CLK_MPFS
help
This driver supports peripheral reset for the Microchip PolarFire SoC
reset: qcom: AOSS (always on subsystem) reset controller Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-06-27 14:24:43 +00:00
config RESET_QCOM_AOSS
reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristate Allow CONFIG_RESET_QCOM_AOSS to be set as as =m to allow for the driver to be loaded from a modules. Also replaces the builtin_platform_driver() line with module_platform_driver() and adds a MODULE_DEVICE_TABLE() entry. Cc: Todd Kjos <tkjos@google.com> Cc: Alistair Delva <adelva@google.com> Cc: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-08 00:19:13 +00:00
tristate "Qcom AOSS Reset Driver"
reset: qcom: AOSS (always on subsystem) reset controller Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-06-27 14:24:43 +00:00
depends on ARCH_QCOM || COMPILE_TEST
help
This enables the AOSS (always on subsystem) reset driver
for Qualcomm SDM845 SoCs. Say Y if you want to control
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
reset: qcom: PDC Global (Power Domain Controller) reset controller Add reset controller for SDM845 SoCs to control reset signals provided by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-08-29 19:12:11 +00:00
config RESET_QCOM_PDC
tristate "Qualcomm PDC Reset Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This enables the PDC (Power Domain Controller) reset driver
for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
to control reset signals provided by PDC for Modem, Compute,
Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
reset: Add Raspberry Pi 4 firmware reset controller Raspberry Pi 4's co-processor controls some of the board's HW initialization process, but it's up to Linux to trigger it when relevant. Introduce a reset controller capable of interfacing with RPi4's co-processor that models these firmware initialization routines as reset lines. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20200629161845.6021-3-nsaenzjulienne@suse.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-06-29 16:18:38 +00:00
config RESET_RASPBERRYPI
tristate "Raspberry Pi 4 Firmware Reset Driver"
depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
default USB_XHCI_PCI
help
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. This driver provides a reset controller capable of
interfacing with RPi4's co-processor and model these firmware
initialization routines as reset lines.
reset: renesas: Add RZ/G2L usbphy control driver Add support for RZ/G2L USBPHY Control driver. It mainly controls reset and power down of the USB/PHY. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210719121938.6532-5-biju.das.jz@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-07-19 12:19:32 +00:00
config RESET_RZG2L_USBPHY_CTRL
tristate "Renesas RZ/G2L USBPHY control driver"
reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L The USBPHY Control block is identical on Renesas RZ/G2L and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220406071647.14037-1-prabhakar.mahadev-lad.rj@bp.renesas.com
2022-04-06 07:16:47 +00:00
depends on ARCH_RZG2L || COMPILE_TEST
reset: renesas: Add RZ/G2L usbphy control driver Add support for RZ/G2L USBPHY Control driver. It mainly controls reset and power down of the USB/PHY. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210719121938.6532-5-biju.das.jz@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-07-19 12:19:32 +00:00
help
Support for USBPHY Control found on RZ/G2L family. It mainly
controls reset and power down of the USB/PHY.
reset: Add support for resets provided by SCMI On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control. System Control and Management Interface(SCMI) Message Protocol is defined for the communication between the Application Cores(AP) and the SCP. Adds support for the resets provided using SCMI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different ARM SCMI device operations provided by the ARM SCMI framework. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-07-08 08:41:08 +00:00
config RESET_SCMI
tristate "Reset driver controlled via ARM SCMI interface"
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
default ARM_SCMI_PROTOCOL
help
This driver provides support for reset signal/domains that are
controlled by firmware that implements the SCMI interface.
This driver uses SCMI Message Protocol to interact with the
firmware controlling all the reset signals.
reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 Copy reusable parts from the sunxi driver, to add a driver for simple reset controllers with reset lines that can be controlled by toggling bits in exclusive, contiguous register ranges using read-modify-write cycles under a spinlock. The following patches will replace compatible reset drivers with reset-simple, extending it where necessary. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-08-11 10:58:43 +00:00
config RESET_SIMPLE
reset: allow building of reset simple driver if expert config selected If CONFIG_EXPERT is selected, allow selection of CONFIG_RESET_SIMPLE if needed by the user. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220708165656.269507-1-ben.dooks@sifive.com
2022-07-08 16:56:56 +00:00
bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
reset: simple: add support for Sophgo SG2042 Reuse reset-simple driver for the Sophgo SG2042 reset generator. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1cfd7b3ba447942784c4f7aa595e962399e9f617.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-01-30 01:50:08 +00:00
default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
reset: reset-simple should depends on HAS_IOMEM The reset-simple driver does not build on all architecuters as it requires devm_ioremap_resource() which is only built when CONFIG_HAS_IOMEM is enabled in the kenrel. Fix the following error by depending on CONFIG_HAS_IOMEM: drivers/reset/reset-simple.o: in function `reset_simple_probe': reset-simple.c:(.text+0x3aa): undefined reference to `devm_ioremap_resource' Fixes: 18d1909be345 ("reset: allow building of reset simple driver if expert config selected") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220719085200.203688-1-ben.dooks@sifive.com
2022-07-19 08:52:00 +00:00
depends on HAS_IOMEM
reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 Copy reusable parts from the sunxi driver, to add a driver for simple reset controllers with reset lines that can be controlled by toggling bits in exclusive, contiguous register ranges using read-modify-write cycles under a spinlock. The following patches will replace compatible reset drivers with reset-simple, extending it where necessary. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-08-11 10:58:43 +00:00
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
exclusive register space.
reset: simple: Enable for ASPEED systems ASPEED BMC SoCs have a reset controller in the LPC IP that can be controlled using this driver to release the UARTs from reset. No special configuration is required, so only the compatible string is added. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-02-20 01:43:29 +00:00
Currently this driver supports:
- Altera SoCFPGAs
- ASPEED BMC SoCs
reset: simple: Keep alphabetical order Restore alphabetical order for Kconfig dependencies and help text. Compatibles got out of order too, but no functional change done here. Goal is to make it obvious where to add new platforms. Fixes: 64c47b624f64 ("reset: Add reset controller support for BM1880 SoC") Fixes: 1d7592f84f92 ("reset: simple: Enable for ASPEED systems") Fixes: 96a2f50305d1 ("reset: build simple reset controller driver for Agilex") Cc: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-10-23 10:13:09 +00:00
- Bitmain BM1880 SoC
reset: simple: Add Realtek RTD1195/RTD1295 Enable RESET_SIMPLE for ARCH_REALTEK. They can reuse the DesignWare bindings to avoid a new compatible. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-10-23 10:13:10 +00:00
- Realtek SoCs
reset: simple: Enable for ASPEED systems ASPEED BMC SoCs have a reset controller in the LPC IP that can be controlled using this driver to release the UARTs from reset. No special configuration is required, so only the compatible string is added. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-02-20 01:43:29 +00:00
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
clk: sifive: Use reset-simple in prci driver for PCIe driver We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Link: https://lore.kernel.org/r/20210504105940.100004-3-greentime.hu@sifive.com Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@kernel.org>
2021-05-04 10:59:36 +00:00
- SiFive FU740 SoCs
reset: simple: add support for Sophgo SG2042 Reuse reset-simple driver for the Sophgo SG2042 reset generator. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1cfd7b3ba447942784c4f7aa595e962399e9f617.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-01-30 01:50:08 +00:00
- Sophgo SoCs
reset: stm32: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 13:34:15 +00:00
reset: socfpga: add an early reset driver for SoCFPGA Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-13 18:50:48 +00:00
config RESET_SOCFPGA
reset: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the 32-bit ARM drivers to rely on new symbol. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-11 15:27:41 +00:00
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
default ARM && ARCH_INTEL_SOCFPGA
reset: socfpga: add an early reset driver for SoCFPGA Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-13 18:50:48 +00:00
select RESET_SIMPLE
help
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
reset: Add Sunplus SP7021 reset driver Add reset driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-06-28 06:26:43 +00:00
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS
help
This enables the reset driver support for Sunplus SoCs.
The reset lines that can be asserted and deasserted by toggling bits
in a contiguous, exclusive register space. The register is HIWORD_MASKED,
which means each register holds 16 reset lines.
reset: sunxi: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-09 07:28:44 +00:00
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
reset: sunxi: use reset-simple driver Use the newly created copies in the reset-simple driver to replace the sunxi platform driver code and reset operations. The separate sunxi driver still remains to register the early reset controllers, but it reuses the reset operations in reset-simple. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-08-11 10:58:43 +00:00
select RESET_SIMPLE
reset: sunxi: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-09 07:28:44 +00:00
help
This enables the reset driver for Allwinner SoCs.
reset: Add the TI SCI reset driver Some TI Keystone family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a reset driver that communicates to the system controller over the TI SCI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: documentation changes, revised commit message] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> [p.zabel@pengutronix.de: const struct reset_control_ops] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 18:09:30 +00:00
config RESET_TI_SCI
tristate "TI System Control Interface (TI-SCI) reset driver"
reset: ti-sci: honor TI_SCI_PROTOCOL setting when not COMPILE_TEST There is a build error when COMPILE_TEST=y, TI_SCI_PROTOCOL=m, and RESET_TI_SCI=y: drivers/reset/reset-ti-sci.o: in function `ti_sci_reset_probe': reset-ti-sci.c:(.text+0x22c): undefined reference to `devm_ti_sci_get_handle' Fix this by making RESET_TI_SCI honor the Kconfig setting of TI_SCI_PROTOCOL when COMPILE_TEST is not set. When COMPILE_TEST is set, TI_SCI_PROTOCOL must be disabled (=n). Fixes: a6af504184c9 ("reset: ti-sci: Allow building under COMPILE_TEST") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <kristo@kernel.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221030055636.3139-1-rdunlap@infradead.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-10-30 05:56:36 +00:00
depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
reset: Add the TI SCI reset driver Some TI Keystone family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a reset driver that communicates to the system controller over the TI SCI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: documentation changes, revised commit message] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> [p.zabel@pengutronix.de: const struct reset_control_ops] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 18:09:30 +00:00
help
This enables the reset driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use reset resources
managed by the TI System Controller, say Y here. Otherwise, say N.
reset: ti_syscon: Rename TI_SYSCON_RESET to RESET_TI_SYSCON Rename the current Kconfig name used for the TI SYSCON Reset driver from TI_SYSCON_RESET to RESET_TI_SYSCON to match the convention used for all the reset drivers present at the base reset folder. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 03:00:12 +00:00
config RESET_TI_SYSCON
reset: add TI SYSCON based reset driver Add a reset-controller driver for performing reset management of various devices present on the SoC, with the reset registers shared between devices in a common register memory space. This driver uses the syscon/regmap frameworks to actually implement the various reset functionalities needed by the reset consumer devices. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: add documentation, syscon name change] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-27 17:12:17 +00:00
tristate "TI SYSCON Reset Driver"
depends on HAS_IOMEM
select MFD_SYSCON
help
This enables the reset driver support for TI devices with
memory-mapped reset registers as part of a syscon device node. If
you wish to use the reset framework for such memory-mapped devices,
say Y here. Otherwise, say N.
reset: tps380x: Add TPS380x device driver supprt The TI TPS380x family [1] is a voltage supervisor with a dedicated manual reset (mr) line input and a reset output. The chip(s) have a build in reset delay, depending on the chip partnumber. This simple driver addresses this so the cosumer don't need to care about it. [1] https://www.ti.com/product/TPS3801 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> [p.zabel@pengutronix.de: drop Todo comment about min/typ/max reset time] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220530092226.748644-2-m.felsch@pengutronix.de
2022-05-30 09:22:26 +00:00
config RESET_TI_TPS380X
tristate "TI TPS380x Reset Driver"
select GPIOLIB
help
This enables the reset driver support for TI TPS380x devices. If
you wish to use the reset framework for such devices, say Y here.
Otherwise, say N.
reset: Add Delta TN48M CPLD reset controller Delta TN48M CPLD exposes resets for the following: * 88F7040 SoC * 88F6820 SoC * 98DX3265 switch MAC-s * 88E1680 PHY-s * 88E1512 PHY * PoE PSE controller Controller supports only self clearing resets. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20220131133049.77780-5-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-01-31 13:30:47 +00:00
config RESET_TN48M_CPLD
tristate "Delta Networks TN48M switch CPLD reset controller"
depends on MFD_TN48M_CPLD || COMPILE_TEST
default MFD_TN48M_CPLD
help
This enables the reset controller driver for the Delta TN48M CPLD.
It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
Microchip PD69200 PoE PSE controller.
This driver can also be built as a module. If so, the module will be
called reset-tn48m.
reset: uniphier: add reset controller driver for UniPhier SoCs This is the initial commit for UniPhier reset controller driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-02 04:18:29 +00:00
config RESET_UNIPHIER
tristate "Reset controller driver for UniPhier SoCs"
depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF && MFD_SYSCON
default ARCH_UNIPHIER
help
Support for reset controllers on UniPhier SoCs.
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
reset: uniphier-usb3: Rename to reset-uniphier-glue This driver works for controlling the reset lines including USB3 glue layer, however, this can be applied to other glue layers. Now this patch renames the driver from "reset-uniphier-usb3" to "reset-uniphier-glue". At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to CONFIG_RESET_UNIPHIER_GLUE. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-09 01:42:05 +00:00
config RESET_UNIPHIER_GLUE
tristate "Reset driver in glue layer for UniPhier SoCs"
reset: uniphier: add USB3 core reset control Add a reset line to enable USB3 core implemented in UniPhier SoCs. This reuses only the reset operations in reset-simple, because the reset-simple doesn't handle any SoC-dependent clocks and resets. This reset line is included in the USB3 glue layer, and it's necessary to enable clocks and deassert resets of the layer before using this reset line. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-10 01:14:17 +00:00
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
default ARCH_UNIPHIER
select RESET_SIMPLE
help
reset: uniphier-usb3: Rename to reset-uniphier-glue This driver works for controlling the reset lines including USB3 glue layer, however, this can be applied to other glue layers. Now this patch renames the driver from "reset-uniphier-usb3" to "reset-uniphier-glue". At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to CONFIG_RESET_UNIPHIER_GLUE. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-09 01:42:05 +00:00
Support for peripheral core reset included in its own glue layer
on UniPhier SoCs. Say Y if you want to control reset signals
provided by the glue layer.
reset: uniphier: add USB3 core reset control Add a reset line to enable USB3 core implemented in UniPhier SoCs. This reuses only the reset operations in reset-simple, because the reset-simple doesn't handle any SoC-dependent clocks and resets. This reset line is included in the USB3 glue layer, and it's necessary to enable clocks and deassert resets of the layer before using this reset line. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-10 01:14:17 +00:00
reset: zynq: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Moritz Fischer <moritz.fischer@ettus.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-09 07:28:54 +00:00
config RESET_ZYNQ
bool "ZYNQ Reset Driver" if COMPILE_TEST
default ARCH_ZYNQ
help
This enables the reset controller driver for Xilinx Zynq SoCs.
reset: zynqmp: allow building under COMPILE_TEST The ZynqMP reset driver can be compiled without ARCH_ZYNQMP being enabled. Allow it to be built under COMPILE_TEST. Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240621-reset-compile-zynqmp-v1-1-ede43ab18101@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-21 15:24:47 +00:00
config RESET_ZYNQMP
bool "ZYNQMP Reset Driver" if COMPILE_TEST
default ARCH_ZYNQMP
help
This enables the reset controller driver for Xilinx ZynqMP SoCs.
reset: amlogic: move drivers to a dedicated directory The meson reset driver will be split in two part, one implemeting the ops, the other providing the platform driver support. This will be done to facilitate the addition of the auxiliary bus support. To avoid making a mess in drivers/reset/ while doing so, move the amlogic reset drivers to a dedicated directory. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-7-60be62635d3e@baylibre.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-09-10 16:32:49 +00:00
source "drivers/reset/amlogic/Kconfig"
reset: Create subdirectory for StarFive drivers This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-01 11:19:20 +00:00
source "drivers/reset/starfive/Kconfig"
drivers: reset: STi SoC system configuration reset controller support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. System configuration registers are accessed through the regmap framework and the mfd/syscon driver. The implementation optionally supports waiting for the reset action to be acknowledged in a separate status register and supports both active high and active low reset lines. These properties are common across all the reset channels in a specific reset controller instance, hence all channels in a paritcular controller are expected to behave in the same way. Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-08-07 14:53:12 +00:00
source "drivers/reset/sti/Kconfig"
reset: hi6220: Reset driver for hisilicon hi6220 SoC Add reset driver for hi6220-hikey board,this driver supply deassert of IP on hi6220 SoC. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-20 02:10:05 +00:00
source "drivers/reset/hisilicon/Kconfig"
reset: Add Tegra BPMP reset driver This driver uses the services provided by the BPMP firmware driver to implement a reset driver based on the MRQ_RESET request. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-18 13:50:09 +00:00
source "drivers/reset/tegra/Kconfig"
reset: fix Kconfig menu to include reset drivers in sub-menu In "make menuconfig", reset drivers are currently lined up together with the reset sub-system menu, like this: -*- Reset Controller Support ---- < > Hi6220 Reset Driver (It also means, the menu "Reset Controller Support" is always empty.) "Hi6220 Reset Driver" should go into the sub-menu of the "Reset Controller Support". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-03 06:29:52 +00:00
endif
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