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ARC: reset: remove the misleading v1 suffix all over
There is no plan yet to do a v2 board. And even if we were to do it only some IPs would actually change, so it be best to add suffixes at that point, not now ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Vineet Gupta
Philipp Zabel
parent
fc9655e651
commit
13541226dc
@ -1,11 +1,11 @@
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Binding for the HSDK v1 reset controller
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Binding for the Synopsys HSDK reset controller
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This binding uses the common reset binding[1].
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[1] Documentation/devicetree/bindings/reset/reset.txt
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Required properties:
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- compatible: should be "snps,hsdk-v1.0-reset".
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- compatible: should be "snps,hsdk-reset".
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- reg: should always contain 2 pairs address - length: first for reset
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configuration register and second for corresponding SW reset and status bits
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register.
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@ -13,7 +13,7 @@ Required properties:
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Example:
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reset: reset@880 {
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compatible = "snps,hsdk-v1.0-reset";
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compatible = "snps,hsdk-reset";
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#reset-cells = <1>;
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reg = <0x8A0 0x4>, <0xFF0 0x4>;
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};
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@ -25,4 +25,4 @@ Specifying reset lines connected to IP modules:
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....
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};
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The index could be found in <dt-bindings/reset/snps,hsdk-v1-reset.h>
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The index could be found in <dt-bindings/reset/snps,hsdk-reset.h>
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@ -12915,9 +12915,9 @@ F: drivers/mmc/host/dw_mmc*
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SYNOPSYS HSDK RESET CONTROLLER DRIVER
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M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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S: Supported
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F: drivers/reset/reset-hsdk-v1.c
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F: include/dt-bindings/reset/snps,hsdk-v1-reset.h
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F: Documentation/devicetree/bindings/reset/snps,hsdk-v1-reset.txt
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F: drivers/reset/reset-hsdk.c
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F: include/dt-bindings/reset/snps,hsdk-reset.h
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F: Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt
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SYSTEM CONFIGURATION (SYSCON)
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M: Lee Jones <lee.jones@linaro.org>
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@ -34,12 +34,12 @@ config RESET_BERLIN
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help
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This enables the reset controller driver for Marvell Berlin SoCs.
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config RESET_HSDK_V1
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bool "HSDK v1 Reset Driver"
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config RESET_HSDK
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bool "Synopsys HSDK Reset Driver"
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depends on HAS_IOMEM
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default n
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help
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This enables the reset controller driver for HSDK v1.
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This enables the reset controller driver for HSDK board.
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config RESET_IMX7
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bool "i.MX7 Reset Driver" if COMPILE_TEST
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@ -5,7 +5,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o
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obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
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obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
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@ -1,7 +1,7 @@
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/*
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* Copyright (C) 2017 Synopsys.
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*
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* Synopsys HSDKv1 SDP reset driver.
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* Synopsys HSDK Development platform reset driver.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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@ -18,9 +18,9 @@
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#include <linux/slab.h>
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#include <linux/types.h>
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#define to_hsdkv1_rst(p) container_of((p), struct hsdkv1_rst, rcdev)
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#define to_hsdk_rst(p) container_of((p), struct hsdk_rst, rcdev)
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struct hsdkv1_rst {
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struct hsdk_rst {
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void __iomem *regs_ctl;
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void __iomem *regs_rst;
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spinlock_t lock;
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@ -49,12 +49,12 @@ static const u32 rst_map[] = {
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#define CGU_IP_SW_RESET_RESET BIT(0)
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#define SW_RESET_TIMEOUT 10000
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static void hsdkv1_reset_config(struct hsdkv1_rst *rst, unsigned long id)
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static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
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{
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writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
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}
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static int hsdkv1_reset_do(struct hsdkv1_rst *rst)
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static int hsdk_reset_do(struct hsdk_rst *rst)
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{
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u32 reg;
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@ -69,28 +69,28 @@ static int hsdkv1_reset_do(struct hsdkv1_rst *rst)
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!(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT);
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}
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static int hsdkv1_reset_reset(struct reset_controller_dev *rcdev,
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static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct hsdkv1_rst *rst = to_hsdkv1_rst(rcdev);
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struct hsdk_rst *rst = to_hsdk_rst(rcdev);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&rst->lock, flags);
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hsdkv1_reset_config(rst, id);
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ret = hsdkv1_reset_do(rst);
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hsdk_reset_config(rst, id);
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ret = hsdk_reset_do(rst);
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spin_unlock_irqrestore(&rst->lock, flags);
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return ret;
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}
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static const struct reset_control_ops hsdkv1_reset_ops = {
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.reset = hsdkv1_reset_reset,
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static const struct reset_control_ops hsdk_reset_ops = {
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.reset = hsdk_reset_reset,
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};
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static int hsdkv1_reset_probe(struct platform_device *pdev)
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static int hsdk_reset_probe(struct platform_device *pdev)
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{
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struct hsdkv1_rst *rst;
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struct hsdk_rst *rst;
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struct resource *mem;
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rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
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@ -110,7 +110,7 @@ static int hsdkv1_reset_probe(struct platform_device *pdev)
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spin_lock_init(&rst->lock);
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rst->rcdev.owner = THIS_MODULE;
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rst->rcdev.ops = &hsdkv1_reset_ops;
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rst->rcdev.ops = &hsdk_reset_ops;
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rst->rcdev.of_node = pdev->dev.of_node;
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rst->rcdev.nr_resets = HSDK_MAX_RESETS;
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rst->rcdev.of_reset_n_cells = 1;
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@ -118,20 +118,20 @@ static int hsdkv1_reset_probe(struct platform_device *pdev)
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return reset_controller_register(&rst->rcdev);
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}
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static const struct of_device_id hsdkv1_reset_dt_match[] = {
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{ .compatible = "snps,hsdk-v1.0-reset" },
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static const struct of_device_id hsdk_reset_dt_match[] = {
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{ .compatible = "snps,hsdk-reset" },
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{ },
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};
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static struct platform_driver hsdkv1_reset_driver = {
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.probe = hsdkv1_reset_probe,
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static struct platform_driver hsdk_reset_driver = {
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.probe = hsdk_reset_probe,
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.driver = {
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.name = "hsdk-v1.0-reset",
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.of_match_table = hsdkv1_reset_dt_match,
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.name = "hsdk-reset",
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.of_match_table = hsdk_reset_dt_match,
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},
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};
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builtin_platform_driver(hsdkv1_reset_driver);
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builtin_platform_driver(hsdk_reset_driver);
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MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
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MODULE_DESCRIPTION("Synopsys HSDKv1 SDP reset driver");
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MODULE_DESCRIPTION("Synopsys HSDK SDP reset driver");
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MODULE_LICENSE("GPL v2");
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17
include/dt-bindings/reset/snps,hsdk-reset.h
Normal file
17
include/dt-bindings/reset/snps,hsdk-reset.h
Normal file
@ -0,0 +1,17 @@
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/**
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* This header provides index for the HSDK reset controller.
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
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#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
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#define HSDK_APB_RESET 0
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#define HSDK_AXI_RESET 1
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#define HSDK_ETH_RESET 2
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#define HSDK_USB_RESET 3
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#define HSDK_SDIO_RESET 4
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#define HSDK_HDMI_RESET 5
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#define HSDK_GFX_RESET 6
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#define HSDK_DMAC_RESET 7
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#define HSDK_EBI_RESET 8
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#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/
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@ -1,17 +0,0 @@
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/**
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* This header provides index for the HSDK v1 reset controller.
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
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#define _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
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#define HSDK_V1_APB_RESET 0
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#define HSDK_V1_AXI_RESET 1
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#define HSDK_V1_ETH_RESET 2
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#define HSDK_V1_USB_RESET 3
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#define HSDK_V1_SDIO_RESET 4
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#define HSDK_V1_HDMI_RESET 5
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#define HSDK_V1_GFX_RESET 6
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#define HSDK_V1_DMAC_RESET 7
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#define HSDK_V1_EBI_RESET 8
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#endif /*_DT_BINDINGS_RESET_CONTROLLER_HSDK_V1*/
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