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clk: sifive: Use reset-simple in prci driver for PCIe driver

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We use reset-simple in this patch so that pcie driver can use
devm_reset_control_get() to get this reset data structure and use
reset_control_deassert() to deassert pcie_power_up_rst_n.

Link: https://lore.kernel.org/r/20210504105940.100004-3-greentime.hu@sifive.com
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Greentime Hu 2021-05-04 18:59:36 +08:00 committed by Lorenzo Pieralisi
parent c61287bf17
commit e4d368e0b6
4 changed files with 20 additions and 0 deletions
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2
drivers/clk/sifive/Kconfig
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@ -10,6 +10,8 @@ if CLK_SIFIVE
config CLK_SIFIVE_PRCI
bool "PRCI driver for SiFive SoCs"
select RESET_CONTROLLER
select RESET_SIMPLE
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in

13
drivers/clk/sifive/sifive-prci.c
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@ -588,6 +588,19 @@ static int sifive_prci_probe(struct platform_device *pdev)
if (IS_ERR(pd->va))
return PTR_ERR(pd->va);
pd->reset.rcdev.owner = THIS_MODULE;
pd->reset.rcdev.nr_resets = PRCI_RST_NR;
pd->reset.rcdev.ops = &reset_simple_ops;
pd->reset.rcdev.of_node = pdev->dev.of_node;
pd->reset.active_low = true;
pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
spin_lock_init(&pd->reset.lock);
r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
if (r) {
dev_err(dev, "could not register reset controller: %d\n", r);
return r;
}
r = __prci_register_clocks(dev, pd, desc);
if (r) {
dev_err(dev, "could not register clocks: %d\n", r);

4
drivers/clk/sifive/sifive-prci.h
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@ -11,6 +11,7 @@
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
#include <linux/clk-provider.h>
#include <linux/reset/reset-simple.h>
#include <linux/platform_device.h>
/*
@ -121,6 +122,8 @@
#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
#define PRCI_RST_NR 7
/* CLKMUXSTATUSREG */
#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
@ -221,6 +224,7 @@
*/
struct __prci_data {
void __iomem *va;
struct reset_simple_data reset;
struct clk_hw_onecell_data hw_clks;
};

1
drivers/reset/Kconfig
View File

@ -197,6 +197,7 @@ config RESET_SIMPLE
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- ZTE's zx2967 family
- SiFive FU740 SoCs
config RESET_STM32MP157
bool "STM32MP157 Reset Driver" if COMPILE_TEST