2017-11-03 10:28:30 +00:00
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// SPDX-License-Identifier: GPL-2.0
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
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/**
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* core.c - DesignWare USB3 DRD Controller Core file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
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#include <linux/clk.h>
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2014-09-19 20:51:11 +00:00
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#include <linux/version.h>
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2011-09-05 10:37:28 +00:00
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#include <linux/module.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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2012-01-18 16:04:09 +00:00
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#include <linux/of.h>
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2014-09-25 07:57:02 +00:00
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#include <linux/acpi.h>
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2015-08-31 15:39:08 +00:00
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#include <linux/pinctrl/consumer.h>
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usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
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#include <linux/reset.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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2013-06-30 11:29:51 +00:00
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#include <linux/usb/of.h>
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2013-07-06 12:52:49 +00:00
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#include <linux/usb/otg.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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#include "debug.h"
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2016-05-16 10:14:48 +00:00
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#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
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2011-10-18 10:54:01 +00:00
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2016-09-07 02:22:03 +00:00
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/**
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* dwc3_get_dr_mode - Validates and sets dr_mode
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* @dwc: pointer to our context structure
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*/
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static int dwc3_get_dr_mode(struct dwc3 *dwc)
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{
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enum usb_dr_mode mode;
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struct device *dev = dwc->dev;
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unsigned int hw_mode;
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if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
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dwc->dr_mode = USB_DR_MODE_OTG;
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mode = dwc->dr_mode;
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hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
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switch (hw_mode) {
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case DWC3_GHWPARAMS0_MODE_GADGET:
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if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
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dev_err(dev,
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"Controller does not support host mode.\n");
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return -EINVAL;
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}
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mode = USB_DR_MODE_PERIPHERAL;
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break;
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case DWC3_GHWPARAMS0_MODE_HOST:
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if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
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dev_err(dev,
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"Controller does not support device mode.\n");
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return -EINVAL;
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}
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mode = USB_DR_MODE_HOST;
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break;
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default:
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if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
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mode = USB_DR_MODE_HOST;
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else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
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mode = USB_DR_MODE_PERIPHERAL;
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2018-07-26 20:52:11 +00:00
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/*
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2018-11-03 01:41:42 +00:00
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* DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
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* mode. If the controller supports DRD but the dr_mode is not
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* specified or set to OTG, then set the mode to peripheral.
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2018-07-26 20:52:11 +00:00
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*/
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2018-11-03 01:41:42 +00:00
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if (mode == USB_DR_MODE_OTG &&
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2020-03-30 00:10:05 +00:00
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(!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
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!device_property_read_bool(dwc->dev, "usb-role-switch")) &&
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2018-11-03 01:41:42 +00:00
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dwc->revision >= DWC3_REVISION_330A)
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2018-07-26 20:52:11 +00:00
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mode = USB_DR_MODE_PERIPHERAL;
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2016-09-07 02:22:03 +00:00
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}
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if (mode != dwc->dr_mode) {
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dev_warn(dev,
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"Configuration mismatch. dr_mode forced to %s\n",
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mode == USB_DR_MODE_HOST ? "host" : "gadget");
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dwc->dr_mode = mode;
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}
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return 0;
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}
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2018-02-27 11:30:19 +00:00
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void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
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2011-10-31 21:25:40 +00:00
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
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reg |= DWC3_GCTL_PRTCAPDIR(mode);
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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2018-01-18 11:24:30 +00:00
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dwc->current_dr_role = mode;
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2017-04-04 09:49:18 +00:00
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}
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static void __dwc3_set_mode(struct work_struct *work)
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{
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struct dwc3 *dwc = work_to_dwc(work);
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unsigned long flags;
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int ret;
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2018-02-27 11:30:19 +00:00
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if (dwc->dr_mode != USB_DR_MODE_OTG)
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2017-04-04 09:49:18 +00:00
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return;
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2020-03-19 10:02:07 +00:00
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pm_runtime_get_sync(dwc->dev);
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2018-02-27 11:30:19 +00:00
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if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
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dwc3_otg_update(dwc, 0);
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2017-04-04 09:49:18 +00:00
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if (!dwc->desired_dr_role)
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2020-03-19 10:02:07 +00:00
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goto out;
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2017-04-04 09:49:18 +00:00
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if (dwc->desired_dr_role == dwc->current_dr_role)
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2020-03-19 10:02:07 +00:00
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goto out;
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2017-04-04 09:49:18 +00:00
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2018-02-27 11:30:19 +00:00
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if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
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2020-03-19 10:02:07 +00:00
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goto out;
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2017-04-04 09:49:18 +00:00
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switch (dwc->current_dr_role) {
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case DWC3_GCTL_PRTCAP_HOST:
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dwc3_host_exit(dwc);
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break;
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case DWC3_GCTL_PRTCAP_DEVICE:
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dwc3_gadget_exit(dwc);
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dwc3_event_buffers_cleanup(dwc);
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break;
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2018-02-27 11:30:19 +00:00
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case DWC3_GCTL_PRTCAP_OTG:
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dwc3_otg_exit(dwc);
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spin_lock_irqsave(&dwc->lock, flags);
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dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
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spin_unlock_irqrestore(&dwc->lock, flags);
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dwc3_otg_update(dwc, 1);
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break;
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2017-04-04 09:49:18 +00:00
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default:
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break;
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}
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spin_lock_irqsave(&dwc->lock, flags);
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dwc3_set_prtcap(dwc, dwc->desired_dr_role);
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2017-04-04 08:25:27 +00:00
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2017-04-04 09:49:18 +00:00
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spin_unlock_irqrestore(&dwc->lock, flags);
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switch (dwc->desired_dr_role) {
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|
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case DWC3_GCTL_PRTCAP_HOST:
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ret = dwc3_host_init(dwc);
|
2017-06-05 14:22:10 +00:00
|
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if (ret) {
|
2017-04-04 09:49:18 +00:00
|
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dev_err(dwc->dev, "failed to initialize host\n");
|
2017-06-05 14:22:10 +00:00
|
|
|
} else {
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if (dwc->usb2_phy)
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otg_set_vbus(dwc->usb2_phy->otg, true);
|
2017-09-27 11:19:22 +00:00
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phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
|
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phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
|
2017-06-05 14:22:10 +00:00
|
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}
|
2017-04-04 09:49:18 +00:00
|
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break;
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case DWC3_GCTL_PRTCAP_DEVICE:
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dwc3_event_buffers_setup(dwc);
|
2017-06-05 14:22:10 +00:00
|
|
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if (dwc->usb2_phy)
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otg_set_vbus(dwc->usb2_phy->otg, false);
|
2017-09-27 11:19:22 +00:00
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phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
|
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phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
|
2017-06-05 14:22:10 +00:00
|
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|
2017-04-04 09:49:18 +00:00
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ret = dwc3_gadget_init(dwc);
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|
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if (ret)
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dev_err(dwc->dev, "failed to initialize peripheral\n");
|
|
|
|
break;
|
2018-02-27 11:30:19 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
|
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dwc3_otg_init(dwc);
|
|
|
|
dwc3_otg_update(dwc, 0);
|
|
|
|
break;
|
2017-04-04 09:49:18 +00:00
|
|
|
default:
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|
|
break;
|
|
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|
}
|
2018-02-27 11:30:19 +00:00
|
|
|
|
2020-03-19 10:02:07 +00:00
|
|
|
out:
|
|
|
|
pm_runtime_mark_last_busy(dwc->dev);
|
|
|
|
pm_runtime_put_autosuspend(dwc->dev);
|
2017-04-04 09:49:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
dwc->desired_dr_role = mode;
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
2018-02-27 10:41:41 +00:00
|
|
|
queue_work(system_freezable_wq, &dwc->drd_work);
|
2011-10-31 21:25:40 +00:00
|
|
|
}
|
2011-10-18 10:54:01 +00:00
|
|
|
|
2016-04-14 12:03:39 +00:00
|
|
|
u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
|
|
|
|
DWC3_GDBGFIFOSPACE_NUM(dep->number) |
|
|
|
|
DWC3_GDBGFIFOSPACE_TYPE(type));
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
|
|
|
|
|
|
|
|
return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
/**
|
|
|
|
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
|
|
|
|
* @dwc: pointer to our context structure
|
|
|
|
*/
|
2014-03-03 11:38:11 +00:00
|
|
|
static int dwc3_core_soft_reset(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
|
|
|
u32 reg;
|
2016-03-11 08:51:52 +00:00
|
|
|
int retries = 1000;
|
2014-03-03 11:38:11 +00:00
|
|
|
int ret;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2012-07-19 11:09:48 +00:00
|
|
|
usb_phy_init(dwc->usb2_phy);
|
|
|
|
usb_phy_init(dwc->usb3_phy);
|
2014-03-03 11:38:11 +00:00
|
|
|
ret = phy_init(dwc->usb2_generic_phy);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = phy_init(dwc->usb3_generic_phy);
|
|
|
|
if (ret < 0) {
|
|
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
return ret;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2016-03-11 08:51:52 +00:00
|
|
|
/*
|
|
|
|
* We're resetting only the device side because, if we're in host mode,
|
|
|
|
* XHCI driver will reset the host block. If dwc3 was configured for
|
|
|
|
* host-only mode, then we can return early.
|
|
|
|
*/
|
2018-01-18 11:24:30 +00:00
|
|
|
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
|
2016-03-11 08:51:52 +00:00
|
|
|
return 0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2016-03-11 08:51:52 +00:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg |= DWC3_DCTL_CSFTRST;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2019-08-08 23:39:42 +00:00
|
|
|
/*
|
|
|
|
* For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
|
|
|
|
* is cleared only after all the clocks are synchronized. This can
|
|
|
|
* take a little more than 50ms. Set the polling rate at 20ms
|
|
|
|
* for 10 times instead.
|
|
|
|
*/
|
|
|
|
if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
|
|
|
|
retries = 10;
|
|
|
|
|
2016-03-11 08:51:52 +00:00
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
if (!(reg & DWC3_DCTL_CSFTRST))
|
2018-03-16 22:33:48 +00:00
|
|
|
goto done;
|
2012-06-21 12:14:28 +00:00
|
|
|
|
2019-08-08 23:39:42 +00:00
|
|
|
if (dwc3_is_usb31(dwc) &&
|
|
|
|
dwc->revision >= DWC3_USB31_REVISION_190A)
|
|
|
|
msleep(20);
|
|
|
|
else
|
|
|
|
udelay(1);
|
2016-03-11 08:51:52 +00:00
|
|
|
} while (--retries);
|
2014-03-03 11:38:11 +00:00
|
|
|
|
2018-01-17 21:22:49 +00:00
|
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
|
2016-03-11 08:51:52 +00:00
|
|
|
return -ETIMEDOUT;
|
2018-03-16 22:33:48 +00:00
|
|
|
|
|
|
|
done:
|
|
|
|
/*
|
2019-08-08 23:39:42 +00:00
|
|
|
* For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
|
|
|
|
* is cleared, we must wait at least 50ms before accessing the PHY
|
|
|
|
* domain (synchronization delay).
|
2018-03-16 22:33:48 +00:00
|
|
|
*/
|
2019-08-08 23:39:42 +00:00
|
|
|
if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
|
2018-03-16 22:33:48 +00:00
|
|
|
msleep(50);
|
|
|
|
|
|
|
|
return 0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
}
|
|
|
|
|
2015-09-04 04:45:58 +00:00
|
|
|
/*
|
|
|
|
* dwc3_frame_length_adjustment - Adjusts frame length if required
|
|
|
|
* @dwc3: Pointer to our controller context structure
|
|
|
|
*/
|
2016-05-16 07:42:23 +00:00
|
|
|
static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
|
2015-09-04 04:45:58 +00:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u32 dft;
|
|
|
|
|
|
|
|
if (dwc->revision < DWC3_REVISION_250A)
|
|
|
|
return;
|
|
|
|
|
2016-05-16 07:42:23 +00:00
|
|
|
if (dwc->fladj == 0)
|
2015-09-04 04:45:58 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
|
|
|
|
dft = reg & DWC3_GFLADJ_30MHZ_MASK;
|
2019-07-29 06:46:07 +00:00
|
|
|
if (dft != dwc->fladj) {
|
2015-09-04 04:45:58 +00:00
|
|
|
reg &= ~DWC3_GFLADJ_30MHZ_MASK;
|
2016-05-16 07:42:23 +00:00
|
|
|
reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
|
2015-09-04 04:45:58 +00:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
/**
|
|
|
|
* dwc3_free_one_event_buffer - Frees one event buffer
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
* @evt: Pointer to event buffer to be freed
|
|
|
|
*/
|
|
|
|
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
|
|
|
|
struct dwc3_event_buffer *evt)
|
|
|
|
{
|
2016-11-17 11:43:47 +00:00
|
|
|
dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2012-02-16 02:56:56 +00:00
|
|
|
* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
* @length: size of the event buffer
|
|
|
|
*
|
2012-02-16 02:56:56 +00:00
|
|
|
* Returns a pointer to the allocated event buffer structure on success
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
* otherwise ERR_PTR(errno).
|
|
|
|
*/
|
2013-02-22 14:31:07 +00:00
|
|
|
static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
|
|
|
|
unsigned length)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2012-10-11 10:48:36 +00:00
|
|
|
evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
if (!evt)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
evt->dwc = dwc;
|
|
|
|
evt->length = length;
|
2016-11-15 10:54:15 +00:00
|
|
|
evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
|
|
|
|
if (!evt->cache)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
2016-11-17 11:43:47 +00:00
|
|
|
evt->buf = dma_alloc_coherent(dwc->sysdev, length,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
&evt->dma, GFP_KERNEL);
|
2012-11-08 13:26:41 +00:00
|
|
|
if (!evt->buf)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
return evt;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_free_event_buffers - frees all allocated event buffers
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*/
|
|
|
|
static void dwc3_free_event_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2016-03-30 06:37:03 +00:00
|
|
|
evt = dwc->ev_buf;
|
2016-03-30 06:26:24 +00:00
|
|
|
if (evt)
|
|
|
|
dwc3_free_one_event_buffer(dwc, evt);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
|
2012-02-16 02:56:56 +00:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
* @length: size of event buffer
|
|
|
|
*
|
2012-02-16 02:56:56 +00:00
|
|
|
* Returns 0 on success otherwise negative errno. In the error case, dwc
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
* may contain some buffers allocated but not all which were requested.
|
|
|
|
*/
|
2012-11-19 18:21:48 +00:00
|
|
|
static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
2016-03-30 06:26:24 +00:00
|
|
|
struct dwc3_event_buffer *evt;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2016-03-30 06:26:24 +00:00
|
|
|
evt = dwc3_alloc_one_event_buffer(dwc, length);
|
|
|
|
if (IS_ERR(evt)) {
|
|
|
|
dev_err(dwc->dev, "can't allocate event buffer\n");
|
|
|
|
return PTR_ERR(evt);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
}
|
2016-03-30 06:37:03 +00:00
|
|
|
dwc->ev_buf = evt;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_event_buffers_setup - setup our allocated event buffers
|
2012-02-16 02:56:56 +00:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
2018-02-27 11:30:19 +00:00
|
|
|
int dwc3_event_buffers_setup(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2016-03-30 06:37:03 +00:00
|
|
|
evt = dwc->ev_buf;
|
2016-03-30 06:26:24 +00:00
|
|
|
evt->lpos = 0;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
|
|
|
|
lower_32_bits(evt->dma));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
|
|
|
|
upper_32_bits(evt->dma));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
|
|
|
|
DWC3_GEVNTSIZ_SIZE(evt->length));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-27 11:30:19 +00:00
|
|
|
void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2016-03-30 06:37:03 +00:00
|
|
|
evt = dwc->ev_buf;
|
2012-04-27 11:28:02 +00:00
|
|
|
|
2016-03-30 06:26:24 +00:00
|
|
|
evt->lpos = 0;
|
2012-04-27 11:28:02 +00:00
|
|
|
|
2016-03-30 06:26:24 +00:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
|
|
|
|
| DWC3_GEVNTSIZ_SIZE(0));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
}
|
|
|
|
|
2013-12-19 19:04:28 +00:00
|
|
|
static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
if (!dwc->has_hibernation)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!dwc->nr_scratch)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
|
|
|
|
DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
|
|
|
|
if (!dwc->scratchbuf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
dma_addr_t scratch_addr;
|
|
|
|
u32 param;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!dwc->has_hibernation)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!dwc->nr_scratch)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* should never fall here */
|
|
|
|
if (!WARN_ON(dwc->scratchbuf))
|
|
|
|
return 0;
|
|
|
|
|
2016-11-17 11:43:47 +00:00
|
|
|
scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
|
2013-12-19 19:04:28 +00:00
|
|
|
dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
2016-11-17 11:43:47 +00:00
|
|
|
if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
|
|
|
|
dev_err(dwc->sysdev, "failed to map scratch buffer\n");
|
2013-12-19 19:04:28 +00:00
|
|
|
ret = -EFAULT;
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->scratch_addr = scratch_addr;
|
|
|
|
|
|
|
|
param = lower_32_bits(scratch_addr);
|
|
|
|
|
|
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
|
|
DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
param = upper_32_bits(scratch_addr);
|
|
|
|
|
|
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
|
|
DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err1:
|
2016-11-17 11:43:47 +00:00
|
|
|
dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
|
2013-12-19 19:04:28 +00:00
|
|
|
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
|
|
|
|
err0:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
if (!dwc->has_hibernation)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!dwc->nr_scratch)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* should never fall here */
|
|
|
|
if (!WARN_ON(dwc->scratchbuf))
|
|
|
|
return;
|
|
|
|
|
2016-11-17 11:43:47 +00:00
|
|
|
dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
|
2013-12-19 19:04:28 +00:00
|
|
|
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
kfree(dwc->scratchbuf);
|
|
|
|
}
|
|
|
|
|
2011-05-05 12:53:10 +00:00
|
|
|
static void dwc3_core_num_eps(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
|
2017-01-31 20:58:10 +00:00
|
|
|
dwc->num_eps = DWC3_NUM_EPS(parms);
|
2011-05-05 12:53:10 +00:00
|
|
|
}
|
|
|
|
|
2012-11-19 18:21:48 +00:00
|
|
|
static void dwc3_cache_hwparams(struct dwc3 *dwc)
|
2011-09-30 07:58:49 +00:00
|
|
|
{
|
|
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
|
|
|
|
parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
|
|
|
|
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
|
|
|
|
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
|
|
|
|
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
|
|
|
|
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
|
|
|
|
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
|
|
|
|
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
|
|
|
|
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
|
|
|
|
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
|
|
|
|
}
|
|
|
|
|
2018-02-12 13:30:08 +00:00
|
|
|
static int dwc3_core_ulpi_init(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
int intf;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
|
|
|
|
|
|
|
|
if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
|
|
|
|
(intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
|
|
|
|
dwc->hsphy_interface &&
|
|
|
|
!strncmp(dwc->hsphy_interface, "ulpi", 4)))
|
|
|
|
ret = dwc3_ulpi_init(dwc);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-10-28 11:54:28 +00:00
|
|
|
/**
|
|
|
|
* dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
|
|
|
|
* @dwc: Pointer to our controller context structure
|
2015-05-13 12:26:51 +00:00
|
|
|
*
|
|
|
|
* Returns 0 on success. The USB PHY interfaces are configured but not
|
|
|
|
* initialized. The PHY interfaces and the PHYs get initialized together with
|
|
|
|
* the core in dwc3_core_init.
|
2014-10-28 11:54:28 +00:00
|
|
|
*/
|
2015-05-13 12:26:51 +00:00
|
|
|
static int dwc3_phy_setup(struct dwc3 *dwc)
|
2014-10-28 11:54:28 +00:00
|
|
|
{
|
2019-08-09 19:15:52 +00:00
|
|
|
unsigned int hw_mode;
|
2014-10-28 11:54:28 +00:00
|
|
|
u32 reg;
|
|
|
|
|
2019-08-09 19:15:52 +00:00
|
|
|
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
|
|
|
|
|
2014-10-28 11:54:28 +00:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
|
2016-08-03 11:16:15 +00:00
|
|
|
/*
|
|
|
|
* Make sure UX_EXIT_PX is cleared as that causes issues with some
|
|
|
|
* PHYs. Also, this bit is not supposed to be used in normal operation.
|
|
|
|
*/
|
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
|
|
|
|
|
2014-10-28 11:54:35 +00:00
|
|
|
/*
|
|
|
|
* Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
|
|
|
|
* to '0' during coreConsultant configuration. So default value
|
|
|
|
* will be '0' when the core is reset. Application needs to set it
|
|
|
|
* to '1' after the core initialization is completed.
|
|
|
|
*/
|
|
|
|
if (dwc->revision > DWC3_REVISION_194A)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
|
2019-08-09 19:15:52 +00:00
|
|
|
/*
|
|
|
|
* For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
|
|
|
|
* power-on reset, and it can be set after core initialization, which is
|
|
|
|
* after device soft-reset during initialization.
|
|
|
|
*/
|
|
|
|
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
|
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
|
2014-10-28 11:54:28 +00:00
|
|
|
if (dwc->u2ss_inp3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
|
|
|
|
|
2016-03-14 09:10:50 +00:00
|
|
|
if (dwc->dis_rxdet_inp3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
|
|
|
|
|
2014-10-28 11:54:29 +00:00
|
|
|
if (dwc->req_p1p2p3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
|
|
|
|
|
2014-10-28 11:54:30 +00:00
|
|
|
if (dwc->del_p1p2p3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
|
|
|
|
|
2014-10-28 11:54:31 +00:00
|
|
|
if (dwc->del_phy_power_chg_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
|
|
|
|
|
2014-10-28 11:54:32 +00:00
|
|
|
if (dwc->lfps_filter_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
|
|
|
|
|
2014-10-28 11:54:33 +00:00
|
|
|
if (dwc->rx_detect_poll_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
|
|
|
|
|
2014-10-31 03:11:12 +00:00
|
|
|
if (dwc->tx_de_emphasis_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
|
|
|
|
|
2014-11-06 17:31:00 +00:00
|
|
|
if (dwc->dis_u3_susphy_quirk)
|
2014-10-31 03:11:13 +00:00
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
|
2016-08-16 14:44:39 +00:00
|
|
|
if (dwc->dis_del_phy_power_chg_quirk)
|
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
|
|
|
|
|
2014-10-28 11:54:28 +00:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
|
2014-10-28 11:54:35 +00:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
|
2015-05-13 12:26:49 +00:00
|
|
|
/* Select the HS PHY interface */
|
|
|
|
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
|
|
|
|
case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
|
2015-07-02 03:03:09 +00:00
|
|
|
if (dwc->hsphy_interface &&
|
|
|
|
!strncmp(dwc->hsphy_interface, "utmi", 4)) {
|
2015-05-13 12:26:49 +00:00
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
|
2015-05-13 12:26:51 +00:00
|
|
|
break;
|
2015-07-02 03:03:09 +00:00
|
|
|
} else if (dwc->hsphy_interface &&
|
|
|
|
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
|
2015-05-13 12:26:49 +00:00
|
|
|
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
|
2015-05-13 12:26:51 +00:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
2015-05-13 12:26:49 +00:00
|
|
|
} else {
|
2015-05-13 12:26:51 +00:00
|
|
|
/* Relying on default value. */
|
|
|
|
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
|
|
|
|
break;
|
2015-05-13 12:26:49 +00:00
|
|
|
}
|
|
|
|
/* FALLTHROUGH */
|
2015-05-13 12:26:51 +00:00
|
|
|
case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
|
|
|
|
/* FALLTHROUGH */
|
2015-05-13 12:26:49 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-08-16 14:44:38 +00:00
|
|
|
switch (dwc->hsphy_mode) {
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMI:
|
|
|
|
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMIW:
|
|
|
|
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-10-28 11:54:35 +00:00
|
|
|
/*
|
|
|
|
* Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
|
|
|
|
* '0' during coreConsultant configuration. So default value will
|
|
|
|
* be '0' when the core is reset. Application needs to set it to
|
|
|
|
* '1' after the core initialization is completed.
|
|
|
|
*/
|
|
|
|
if (dwc->revision > DWC3_REVISION_194A)
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
|
2019-08-09 19:15:52 +00:00
|
|
|
/*
|
|
|
|
* For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
|
|
|
|
* power-on reset, and it can be set after core initialization, which is
|
|
|
|
* after device soft-reset during initialization.
|
|
|
|
*/
|
|
|
|
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
|
2014-11-06 17:31:00 +00:00
|
|
|
if (dwc->dis_u2_susphy_quirk)
|
2014-10-31 03:11:14 +00:00
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
|
2015-10-03 03:30:57 +00:00
|
|
|
if (dwc->dis_enblslpm_quirk)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
|
2018-11-08 02:10:30 +00:00
|
|
|
else
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
|
2015-10-03 03:30:57 +00:00
|
|
|
|
2016-08-16 14:44:37 +00:00
|
|
|
if (dwc->dis_u2_freeclk_exists_quirk)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
|
|
|
|
|
2014-10-28 11:54:35 +00:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
2015-05-13 12:26:51 +00:00
|
|
|
|
|
|
|
return 0;
|
2014-10-28 11:54:28 +00:00
|
|
|
}
|
|
|
|
|
2016-05-16 07:49:01 +00:00
|
|
|
static void dwc3_core_exit(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
|
|
|
|
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
|
|
phy_power_off(dwc->usb3_generic_phy);
|
2019-07-12 07:26:34 +00:00
|
|
|
clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
reset_control_assert(dwc->reset);
|
2016-05-16 07:49:01 +00:00
|
|
|
}
|
|
|
|
|
2016-10-14 13:19:01 +00:00
|
|
|
static bool dwc3_core_is_valid(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
2016-10-14 13:19:01 +00:00
|
|
|
u32 reg;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2011-08-29 11:56:36 +00:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
|
2016-10-14 13:19:01 +00:00
|
|
|
|
2011-08-29 11:56:36 +00:00
|
|
|
/* This should read as U3 followed by revision number */
|
2015-09-05 02:15:10 +00:00
|
|
|
if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
|
|
|
|
/* Detected DWC_usb3 IP */
|
|
|
|
dwc->revision = reg;
|
|
|
|
} else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
|
|
|
|
/* Detected DWC_usb31 IP */
|
|
|
|
dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
|
|
|
|
dwc->revision |= DWC3_REVISION_IS_DWC31;
|
2018-11-08 20:06:48 +00:00
|
|
|
dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
|
2015-09-05 02:15:10 +00:00
|
|
|
} else {
|
2016-10-14 13:19:01 +00:00
|
|
|
return false;
|
2011-08-29 11:56:36 +00:00
|
|
|
}
|
|
|
|
|
2016-10-14 13:19:01 +00:00
|
|
|
return true;
|
|
|
|
}
|
2012-06-21 12:14:29 +00:00
|
|
|
|
2016-10-14 13:23:24 +00:00
|
|
|
static void dwc3_core_setup_global_control(struct dwc3 *dwc)
|
2016-10-14 13:19:01 +00:00
|
|
|
{
|
2016-10-14 13:23:24 +00:00
|
|
|
u32 hwparams4 = dwc->hwparams.hwparams4;
|
|
|
|
u32 reg;
|
2016-05-16 07:49:01 +00:00
|
|
|
|
2011-10-31 21:25:41 +00:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
2012-02-25 01:32:13 +00:00
|
|
|
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
|
2011-10-31 21:25:41 +00:00
|
|
|
|
2011-11-24 10:22:05 +00:00
|
|
|
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
|
2011-10-31 21:25:41 +00:00
|
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
|
2014-02-25 20:00:13 +00:00
|
|
|
/**
|
|
|
|
* WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
|
|
|
|
* issue which would cause xHCI compliance tests to fail.
|
|
|
|
*
|
|
|
|
* Because of that we cannot enable clock gating on such
|
|
|
|
* configurations.
|
|
|
|
*
|
|
|
|
* Refers to:
|
|
|
|
*
|
|
|
|
* STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
|
|
|
|
* SOF/ITP Mode Used
|
|
|
|
*/
|
|
|
|
if ((dwc->dr_mode == USB_DR_MODE_HOST ||
|
|
|
|
dwc->dr_mode == USB_DR_MODE_OTG) &&
|
|
|
|
(dwc->revision >= DWC3_REVISION_210A &&
|
|
|
|
dwc->revision <= DWC3_REVISION_250A))
|
|
|
|
reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
|
|
|
|
else
|
|
|
|
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
|
2011-10-31 21:25:41 +00:00
|
|
|
break;
|
2013-12-19 19:04:28 +00:00
|
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
|
|
|
|
/* enable hibernation here */
|
|
|
|
dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
|
2014-10-28 11:54:22 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT Enabling this bit so that host-mode hibernation
|
|
|
|
* will work. Device-mode hibernation is not yet implemented.
|
|
|
|
*/
|
|
|
|
reg |= DWC3_GCTL_GBLHIBERNATIONEN;
|
2013-12-19 19:04:28 +00:00
|
|
|
break;
|
2011-10-31 21:25:41 +00:00
|
|
|
default:
|
2016-11-03 12:07:51 +00:00
|
|
|
/* nothing */
|
|
|
|
break;
|
2011-10-31 21:25:41 +00:00
|
|
|
}
|
|
|
|
|
2014-10-28 11:54:23 +00:00
|
|
|
/* check if current dwc3 is on simulation board */
|
|
|
|
if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
|
2018-08-18 16:49:54 +00:00
|
|
|
dev_info(dwc->dev, "Running with FPGA optimizations\n");
|
2014-10-28 11:54:23 +00:00
|
|
|
dwc->is_fpga = true;
|
|
|
|
}
|
|
|
|
|
2014-10-28 11:54:25 +00:00
|
|
|
WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
|
|
|
|
"disable_scramble cannot be used on non-FPGA builds\n");
|
|
|
|
|
|
|
|
if (dwc->disable_scramble_quirk && dwc->is_fpga)
|
|
|
|
reg |= DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
else
|
|
|
|
reg &= ~DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
|
2014-10-28 11:54:27 +00:00
|
|
|
if (dwc->u2exit_lfps_quirk)
|
|
|
|
reg |= DWC3_GCTL_U2EXIT_LFPS;
|
|
|
|
|
2011-10-31 21:25:41 +00:00
|
|
|
/*
|
|
|
|
* WORKAROUND: DWC3 revisions <1.90a have a bug
|
2012-02-16 02:56:56 +00:00
|
|
|
* where the device can fail to connect at SuperSpeed
|
2011-10-31 21:25:41 +00:00
|
|
|
* and falls back to high-speed mode which causes
|
2012-02-16 02:56:56 +00:00
|
|
|
* the device to enter a Connect/Disconnect loop
|
2011-10-31 21:25:41 +00:00
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_190A)
|
|
|
|
reg |= DWC3_GCTL_U2RSTECN;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
2016-10-14 13:23:24 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 14:03:18 +00:00
|
|
|
static int dwc3_core_get_phy(struct dwc3 *dwc);
|
2018-02-12 13:30:08 +00:00
|
|
|
static int dwc3_core_ulpi_init(struct dwc3 *dwc);
|
2017-06-05 14:03:18 +00:00
|
|
|
|
2018-07-23 10:32:37 +00:00
|
|
|
/* set global incr burst type configuration registers */
|
|
|
|
static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct device *dev = dwc->dev;
|
|
|
|
/* incrx_mode : for INCR burst type. */
|
|
|
|
bool incrx_mode;
|
|
|
|
/* incrx_size : for size of INCRX burst. */
|
|
|
|
u32 incrx_size;
|
|
|
|
u32 *vals;
|
|
|
|
u32 cfg;
|
|
|
|
int ntype;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Handle property "snps,incr-burst-type-adjustment".
|
|
|
|
* Get the number of value from this property:
|
|
|
|
* result <= 0, means this property is not supported.
|
|
|
|
* result = 1, means INCRx burst mode supported.
|
|
|
|
* result > 1, means undefined length burst mode supported.
|
|
|
|
*/
|
2019-07-23 19:17:04 +00:00
|
|
|
ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
|
2018-07-23 10:32:37 +00:00
|
|
|
if (ntype <= 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
|
|
|
|
if (!vals) {
|
|
|
|
dev_err(dev, "Error to get memory\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get INCR burst type, and parse it */
|
|
|
|
ret = device_property_read_u32_array(dev,
|
|
|
|
"snps,incr-burst-type-adjustment", vals, ntype);
|
|
|
|
if (ret) {
|
2019-03-27 15:17:37 +00:00
|
|
|
kfree(vals);
|
2018-07-23 10:32:37 +00:00
|
|
|
dev_err(dev, "Error to get property\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
incrx_size = *vals;
|
|
|
|
|
|
|
|
if (ntype > 1) {
|
|
|
|
/* INCRX (undefined length) burst mode */
|
|
|
|
incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
|
|
|
|
for (i = 1; i < ntype; i++) {
|
|
|
|
if (vals[i] > incrx_size)
|
|
|
|
incrx_size = vals[i];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* INCRX burst mode */
|
|
|
|
incrx_mode = INCRX_BURST_MODE;
|
|
|
|
}
|
|
|
|
|
2019-03-27 15:17:37 +00:00
|
|
|
kfree(vals);
|
|
|
|
|
2018-07-23 10:32:37 +00:00
|
|
|
/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
|
|
|
|
cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
|
|
|
|
if (incrx_mode)
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
|
|
|
|
switch (incrx_size) {
|
|
|
|
case 256:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
|
|
|
|
break;
|
|
|
|
case 128:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev, "Invalid property\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
|
|
|
|
}
|
|
|
|
|
2016-10-14 13:23:24 +00:00
|
|
|
/**
|
|
|
|
* dwc3_core_init - Low-level initialization of DWC3 Core
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
|
|
|
static int dwc3_core_init(struct dwc3 *dwc)
|
|
|
|
{
|
2019-08-09 19:15:52 +00:00
|
|
|
unsigned int hw_mode;
|
2016-10-14 13:23:24 +00:00
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
2019-08-09 19:15:52 +00:00
|
|
|
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
|
|
|
|
|
2016-10-14 13:23:24 +00:00
|
|
|
/*
|
|
|
|
* Write Linux Version Code to our GUID register so it's easy to figure
|
|
|
|
* out which kernel version a bug was found.
|
|
|
|
*/
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
|
|
|
|
|
|
|
|
/* Handle USB2.0-only core configuration */
|
|
|
|
if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
|
|
|
|
DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
|
|
|
|
if (dwc->maximum_speed == USB_SPEED_SUPER)
|
|
|
|
dwc->maximum_speed = USB_SPEED_HIGH;
|
|
|
|
}
|
|
|
|
|
2018-02-12 13:30:08 +00:00
|
|
|
ret = dwc3_phy_setup(dwc);
|
2016-10-14 13:23:24 +00:00
|
|
|
if (ret)
|
|
|
|
goto err0;
|
2011-10-31 21:25:41 +00:00
|
|
|
|
2018-02-12 13:30:08 +00:00
|
|
|
if (!dwc->ulpi_ready) {
|
|
|
|
ret = dwc3_core_ulpi_init(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
|
|
|
dwc->ulpi_ready = true;
|
|
|
|
}
|
2011-10-31 21:25:41 +00:00
|
|
|
|
2018-02-12 13:30:08 +00:00
|
|
|
if (!dwc->phys_ready) {
|
|
|
|
ret = dwc3_core_get_phy(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto err0a;
|
|
|
|
dwc->phys_ready = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = dwc3_core_soft_reset(dwc);
|
2017-06-05 14:03:18 +00:00
|
|
|
if (ret)
|
2018-02-12 13:30:08 +00:00
|
|
|
goto err0a;
|
2017-06-05 14:03:18 +00:00
|
|
|
|
2019-08-09 19:15:52 +00:00
|
|
|
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
|
|
|
|
dwc->revision > DWC3_REVISION_194A) {
|
|
|
|
if (!dwc->dis_u3_susphy_quirk) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!dwc->dis_u2_susphy_quirk) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-14 13:23:24 +00:00
|
|
|
dwc3_core_setup_global_control(dwc);
|
2016-05-16 07:49:01 +00:00
|
|
|
dwc3_core_num_eps(dwc);
|
2013-12-19 19:04:28 +00:00
|
|
|
|
|
|
|
ret = dwc3_setup_scratch_buffers(dwc);
|
|
|
|
if (ret)
|
2016-05-16 07:49:01 +00:00
|
|
|
goto err1;
|
|
|
|
|
|
|
|
/* Adjust Frame Length */
|
|
|
|
dwc3_frame_length_adjustment(dwc);
|
|
|
|
|
2018-07-23 10:32:37 +00:00
|
|
|
dwc3_set_incr_burst_type(dwc);
|
|
|
|
|
2016-05-16 07:49:01 +00:00
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 0);
|
|
|
|
usb_phy_set_suspend(dwc->usb3_phy, 0);
|
|
|
|
ret = phy_power_on(dwc->usb2_generic_phy);
|
|
|
|
if (ret < 0)
|
2013-12-19 19:04:28 +00:00
|
|
|
goto err2;
|
|
|
|
|
2016-05-16 07:49:01 +00:00
|
|
|
ret = phy_power_on(dwc->usb3_generic_phy);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err3;
|
|
|
|
|
|
|
|
ret = dwc3_event_buffers_setup(dwc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to setup event buffers\n");
|
|
|
|
goto err4;
|
|
|
|
}
|
|
|
|
|
2016-08-22 22:39:13 +00:00
|
|
|
/*
|
|
|
|
* ENDXFER polling is available on version 3.10a and later of
|
|
|
|
* the DWC_usb3 controller. It is NOT available in the
|
|
|
|
* DWC_usb31 controller.
|
|
|
|
*/
|
|
|
|
if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
|
|
|
|
reg |= DWC3_GUCTL2_RST_ACTBITLATER;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
|
|
|
|
}
|
|
|
|
|
2017-04-19 12:11:38 +00:00
|
|
|
if (dwc->revision >= DWC3_REVISION_250A) {
|
2016-10-13 01:00:55 +00:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
|
2017-04-19 12:11:38 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable hardware control of sending remote wakeup
|
|
|
|
* in HS when the device is in the L1 state.
|
|
|
|
*/
|
|
|
|
if (dwc->revision >= DWC3_REVISION_290A)
|
|
|
|
reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
|
|
|
|
|
|
|
|
if (dwc->dis_tx_ipgap_linecheck_quirk)
|
|
|
|
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
|
|
|
|
|
2020-02-21 09:15:31 +00:00
|
|
|
if (dwc->parkmode_disable_ss_quirk)
|
|
|
|
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
|
|
|
|
2016-10-13 01:00:55 +00:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
|
|
|
}
|
|
|
|
|
2018-07-27 07:41:20 +00:00
|
|
|
if (dwc->dr_mode == USB_DR_MODE_HOST ||
|
|
|
|
dwc->dr_mode == USB_DR_MODE_OTG) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable Auto retry Feature to make the controller operating in
|
|
|
|
* Host mode on seeing transaction errors(CRC errors or internal
|
|
|
|
* overrun scenerios) on IN transfers to reply to the device
|
|
|
|
* with a non-terminating retry ACK (i.e, an ACK transcation
|
|
|
|
* packet with Retry=1 & Nump != 0)
|
|
|
|
*/
|
|
|
|
reg |= DWC3_GUCTL_HSTINAUTORETRY;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
|
|
|
|
}
|
|
|
|
|
2018-03-16 22:35:44 +00:00
|
|
|
/*
|
|
|
|
* Must config both number of packets and max burst settings to enable
|
|
|
|
* RX and/or TX threshold.
|
|
|
|
*/
|
|
|
|
if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
|
|
|
|
u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
|
|
|
|
u8 rx_maxburst = dwc->rx_max_burst_prd;
|
|
|
|
u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
|
|
|
|
u8 tx_maxburst = dwc->tx_max_burst_prd;
|
|
|
|
|
|
|
|
if (rx_thr_num && rx_maxburst) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
|
|
|
|
reg |= DWC31_RXTHRNUMPKTSEL_PRD;
|
|
|
|
|
|
|
|
reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
|
|
|
|
reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
|
|
|
|
|
|
|
|
reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
|
|
|
|
reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tx_thr_num && tx_maxburst) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
|
|
|
|
reg |= DWC31_TXTHRNUMPKTSEL_PRD;
|
|
|
|
|
|
|
|
reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
|
|
|
|
reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
|
|
|
|
|
|
|
|
reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
|
|
|
|
reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-05-16 07:49:01 +00:00
|
|
|
err4:
|
2016-10-21 10:51:07 +00:00
|
|
|
phy_power_off(dwc->usb3_generic_phy);
|
2016-05-16 07:49:01 +00:00
|
|
|
|
|
|
|
err3:
|
2016-10-21 10:51:07 +00:00
|
|
|
phy_power_off(dwc->usb2_generic_phy);
|
2016-05-16 07:49:01 +00:00
|
|
|
|
2013-12-19 19:04:28 +00:00
|
|
|
err2:
|
2016-05-16 07:49:01 +00:00
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
2013-12-19 19:04:28 +00:00
|
|
|
|
|
|
|
err1:
|
|
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
2014-03-03 11:38:11 +00:00
|
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
phy_exit(dwc->usb3_generic_phy);
|
2013-12-19 19:04:28 +00:00
|
|
|
|
2018-02-12 13:30:08 +00:00
|
|
|
err0a:
|
|
|
|
dwc3_ulpi_exit(dwc);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
err0:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-04-16 20:08:29 +00:00
|
|
|
static int dwc3_core_get_phy(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
2014-04-16 20:08:29 +00:00
|
|
|
struct device *dev = dwc->dev;
|
2013-07-31 06:21:25 +00:00
|
|
|
struct device_node *node = dev->of_node;
|
2014-04-16 20:08:29 +00:00
|
|
|
int ret;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2013-01-25 11:06:53 +00:00
|
|
|
if (node) {
|
|
|
|
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
|
|
|
|
dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
|
2013-08-14 18:21:23 +00:00
|
|
|
} else {
|
|
|
|
dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
|
|
|
|
dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
|
2013-01-25 11:06:53 +00:00
|
|
|
}
|
|
|
|
|
2013-03-15 08:52:08 +00:00
|
|
|
if (IS_ERR(dwc->usb2_phy)) {
|
|
|
|
ret = PTR_ERR(dwc->usb2_phy);
|
2014-03-03 11:38:10 +00:00
|
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
|
|
dwc->usb2_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
2013-03-15 08:52:08 +00:00
|
|
|
return ret;
|
2014-03-03 11:38:10 +00:00
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2012-07-19 11:09:48 +00:00
|
|
|
}
|
|
|
|
|
2013-03-15 08:52:08 +00:00
|
|
|
if (IS_ERR(dwc->usb3_phy)) {
|
2013-07-04 05:59:34 +00:00
|
|
|
ret = PTR_ERR(dwc->usb3_phy);
|
2014-03-03 11:38:10 +00:00
|
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
|
|
dwc->usb3_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
2013-03-15 08:52:08 +00:00
|
|
|
return ret;
|
2014-03-03 11:38:10 +00:00
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2012-07-19 11:09:48 +00:00
|
|
|
}
|
|
|
|
|
2014-03-03 11:38:11 +00:00
|
|
|
dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
|
|
|
|
if (IS_ERR(dwc->usb2_generic_phy)) {
|
|
|
|
ret = PTR_ERR(dwc->usb2_generic_phy);
|
|
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
|
|
dwc->usb2_generic_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
|
|
|
|
if (IS_ERR(dwc->usb3_generic_phy)) {
|
|
|
|
ret = PTR_ERR(dwc->usb3_generic_phy);
|
|
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
|
|
dwc->usb3_generic_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-16 20:08:29 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-16 20:13:45 +00:00
|
|
|
static int dwc3_core_init_mode(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct device *dev = dwc->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
2017-04-04 09:49:18 +00:00
|
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
2017-06-05 14:22:10 +00:00
|
|
|
|
|
|
|
if (dwc->usb2_phy)
|
|
|
|
otg_set_vbus(dwc->usb2_phy->otg, false);
|
2017-09-27 11:19:22 +00:00
|
|
|
phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
|
|
|
|
phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
|
2017-06-05 14:22:10 +00:00
|
|
|
|
2014-04-16 20:13:45 +00:00
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
|
|
if (ret) {
|
2016-06-10 11:48:38 +00:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize gadget\n");
|
2014-04-16 20:13:45 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
2017-04-04 09:49:18 +00:00
|
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
|
2017-06-05 14:22:10 +00:00
|
|
|
|
|
|
|
if (dwc->usb2_phy)
|
|
|
|
otg_set_vbus(dwc->usb2_phy->otg, true);
|
2017-09-27 11:19:22 +00:00
|
|
|
phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
|
|
|
|
phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
|
2017-06-05 14:22:10 +00:00
|
|
|
|
2014-04-16 20:13:45 +00:00
|
|
|
ret = dwc3_host_init(dwc);
|
|
|
|
if (ret) {
|
2016-06-10 11:48:38 +00:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize host\n");
|
2014-04-16 20:13:45 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_OTG:
|
2017-04-04 09:49:18 +00:00
|
|
|
INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
|
2017-04-05 10:39:31 +00:00
|
|
|
ret = dwc3_drd_init(dwc);
|
|
|
|
if (ret) {
|
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize dual-role\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2014-04-16 20:13:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_core_exit_mode(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
dwc3_gadget_exit(dwc);
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
|
|
|
dwc3_host_exit(dwc);
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_OTG:
|
2017-04-05 10:39:31 +00:00
|
|
|
dwc3_drd_exit(dwc);
|
2014-04-16 20:13:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
2019-12-11 16:10:03 +00:00
|
|
|
|
|
|
|
/* de-assert DRVVBUS for HOST and OTG mode */
|
|
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
2014-04-16 20:13:45 +00:00
|
|
|
}
|
|
|
|
|
2016-10-14 13:30:52 +00:00
|
|
|
static void dwc3_get_properties(struct dwc3 *dwc)
|
2014-04-16 20:08:29 +00:00
|
|
|
{
|
2016-10-14 13:30:52 +00:00
|
|
|
struct device *dev = dwc->dev;
|
2014-10-28 11:54:26 +00:00
|
|
|
u8 lpm_nyet_threshold;
|
2014-10-31 03:11:12 +00:00
|
|
|
u8 tx_de_emphasis;
|
2014-10-31 03:11:18 +00:00
|
|
|
u8 hird_threshold;
|
2018-03-16 22:35:44 +00:00
|
|
|
u8 rx_thr_num_pkt_prd;
|
|
|
|
u8 rx_max_burst_prd;
|
|
|
|
u8 tx_thr_num_pkt_prd;
|
|
|
|
u8 tx_max_burst_prd;
|
2014-04-16 20:08:29 +00:00
|
|
|
|
2014-10-28 11:54:26 +00:00
|
|
|
/* default to highest possible threshold */
|
2019-04-25 20:55:23 +00:00
|
|
|
lpm_nyet_threshold = 0xf;
|
2014-10-28 11:54:26 +00:00
|
|
|
|
2014-10-31 03:11:12 +00:00
|
|
|
/* default to -3.5dB de-emphasis */
|
|
|
|
tx_de_emphasis = 1;
|
|
|
|
|
2014-10-31 03:11:18 +00:00
|
|
|
/*
|
|
|
|
* default to assert utmi_sleep_n and use maximum allowed HIRD
|
|
|
|
* threshold value of 0b1100
|
|
|
|
*/
|
|
|
|
hird_threshold = 12;
|
|
|
|
|
2015-09-21 08:14:32 +00:00
|
|
|
dwc->maximum_speed = usb_get_maximum_speed(dev);
|
2015-09-21 08:14:34 +00:00
|
|
|
dwc->dr_mode = usb_get_dr_mode(dev);
|
2016-08-16 14:44:38 +00:00
|
|
|
dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
|
2015-09-21 08:14:32 +00:00
|
|
|
|
2016-11-17 11:43:47 +00:00
|
|
|
dwc->sysdev_is_parent = device_property_read_bool(dev,
|
|
|
|
"linux,sysdev_is_parent");
|
|
|
|
if (dwc->sysdev_is_parent)
|
|
|
|
dwc->sysdev = dwc->dev->parent;
|
|
|
|
else
|
|
|
|
dwc->sysdev = dwc->dev;
|
|
|
|
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->has_lpm_erratum = device_property_read_bool(dev,
|
2014-10-28 11:54:26 +00:00
|
|
|
"snps,has-lpm-erratum");
|
2015-09-21 08:14:35 +00:00
|
|
|
device_property_read_u8(dev, "snps,lpm-nyet-threshold",
|
2014-10-28 11:54:26 +00:00
|
|
|
&lpm_nyet_threshold);
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
|
2014-10-31 03:11:18 +00:00
|
|
|
"snps,is-utmi-l1-suspend");
|
2015-09-21 08:14:35 +00:00
|
|
|
device_property_read_u8(dev, "snps,hird-threshold",
|
2014-10-31 03:11:18 +00:00
|
|
|
&hird_threshold);
|
usb: dwc3: Add workaround for isoc start transfer failure
In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
isochronous IN, BIT[15:14] of the 16-bit microframe number reported by
the XferNotReady event are invalid. The driver uses this number to
schedule the isochronous transfer and passes it to the START TRANSFER
command. Because this number is invalid, the command may fail. If
BIT[15:14] matches the internal 16-bit microframe, the START TRANSFER
command will pass and the transfer will start at the scheduled time, if
it is off by 1, the command will still pass, but the transfer will start
2 seconds in the future. For all other conditions, the START TRANSFER
command will fail with bus-expiry.
In order to workaround this issue, we can test for the correct
combination of BIT[15:14] by sending START TRANSFER commands with
different values of BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each
combination is 2^14 uframe apart (or 2 seconds). 4 seconds into the
future will result in a bus-expiry status. As the result, within the 4
possible combinations for BIT[15:14], there will be 2 successful and 2
failure START COMMAND status. One of the 2 successful command status
will result in a 2-second delay start. The smaller BIT[15:14] value is
the correct combination.
Since there are only 4 outcomes and the results are ordered, we can
simply test 2 START TRANSFER commands with BIT[15:14] combinations 'b00
and 'b01 to deduce the smaller successful combination.
Let test0 = test status for combination 'b00 and test1 = test status for
'b01 of BIT[15:14]. The correct combination is as follow:
if test0 fails and test1 passes, BIT[15:14] is 'b01
if test0 fails and test1 fails, BIT[15:14] is 'b10
if test0 passes and test1 fails, BIT[15:14] is 'b11
if test0 passes and test1 passes, BIT[15:14] is 'b00
Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
endpoints.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-15 06:56:54 +00:00
|
|
|
dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-start-transfer-quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->usb3_lpm_capable = device_property_read_bool(dev,
|
2015-03-09 14:06:12 +00:00
|
|
|
"snps,usb3_lpm_capable");
|
2018-11-08 02:10:42 +00:00
|
|
|
dwc->usb2_lpm_disable = device_property_read_bool(dev,
|
|
|
|
"snps,usb2-lpm-disable");
|
2018-03-16 22:35:44 +00:00
|
|
|
device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
|
|
|
|
&rx_thr_num_pkt_prd);
|
|
|
|
device_property_read_u8(dev, "snps,rx-max-burst-prd",
|
|
|
|
&rx_max_burst_prd);
|
|
|
|
device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
|
|
|
|
&tx_thr_num_pkt_prd);
|
|
|
|
device_property_read_u8(dev, "snps,tx-max-burst-prd",
|
|
|
|
&tx_max_burst_prd);
|
2014-04-16 20:08:29 +00:00
|
|
|
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->disable_scramble_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:25 +00:00
|
|
|
"snps,disable_scramble_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:27 +00:00
|
|
|
"snps,u2exit_lfps_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:28 +00:00
|
|
|
"snps,u2ss_inp3_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:29 +00:00
|
|
|
"snps,req_p1p2p3_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:30 +00:00
|
|
|
"snps,del_p1p2p3_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:31 +00:00
|
|
|
"snps,del_phy_power_chg_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->lfps_filter_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:32 +00:00
|
|
|
"snps,lfps_filter_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
|
2014-10-28 11:54:33 +00:00
|
|
|
"snps,rx_detect_poll_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
|
2014-10-31 03:11:13 +00:00
|
|
|
"snps,dis_u3_susphy_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
|
2014-10-31 03:11:14 +00:00
|
|
|
"snps,dis_u2_susphy_quirk");
|
2015-10-03 03:30:57 +00:00
|
|
|
dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis_enblslpm_quirk");
|
2019-05-10 07:07:28 +00:00
|
|
|
dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-u1-entry-quirk");
|
|
|
|
dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-u2-entry-quirk");
|
2016-03-14 09:10:50 +00:00
|
|
|
dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis_rxdet_inp3_quirk");
|
2016-08-16 14:44:37 +00:00
|
|
|
dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-u2-freeclk-exists-quirk");
|
2016-08-16 14:44:39 +00:00
|
|
|
dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-del-phy-power-chg-quirk");
|
2017-04-19 12:11:38 +00:00
|
|
|
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-tx-ipgap-linecheck-quirk");
|
2020-02-21 09:15:31 +00:00
|
|
|
dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,parkmode-disable-ss-quirk");
|
2014-10-31 03:11:12 +00:00
|
|
|
|
2015-09-21 08:14:35 +00:00
|
|
|
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
|
2014-10-31 03:11:12 +00:00
|
|
|
"snps,tx_de_emphasis_quirk");
|
2015-09-21 08:14:35 +00:00
|
|
|
device_property_read_u8(dev, "snps,tx_de_emphasis",
|
2014-10-31 03:11:12 +00:00
|
|
|
&tx_de_emphasis);
|
2015-09-21 08:14:35 +00:00
|
|
|
device_property_read_string(dev, "snps,hsphy_interface",
|
|
|
|
&dwc->hsphy_interface);
|
|
|
|
device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
|
2016-05-16 07:42:23 +00:00
|
|
|
&dwc->fladj);
|
2015-09-21 08:14:35 +00:00
|
|
|
|
2017-10-31 13:11:55 +00:00
|
|
|
dwc->dis_metastability_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis_metastability_quirk");
|
|
|
|
|
2014-10-28 11:54:26 +00:00
|
|
|
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
|
2014-10-31 03:11:12 +00:00
|
|
|
dwc->tx_de_emphasis = tx_de_emphasis;
|
2014-10-28 11:54:26 +00:00
|
|
|
|
2019-08-20 01:35:58 +00:00
|
|
|
dwc->hird_threshold = hird_threshold;
|
2014-10-31 03:11:18 +00:00
|
|
|
|
2018-03-16 22:35:44 +00:00
|
|
|
dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
|
|
|
|
dwc->rx_max_burst_prd = rx_max_burst_prd;
|
|
|
|
|
|
|
|
dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
|
|
|
|
dwc->tx_max_burst_prd = tx_max_burst_prd;
|
|
|
|
|
2016-11-14 20:32:43 +00:00
|
|
|
dwc->imod_interval = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check whether the core supports IMOD */
|
|
|
|
bool dwc3_has_imod(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
return ((dwc3_is_usb3(dwc) &&
|
|
|
|
dwc->revision >= DWC3_REVISION_300A) ||
|
|
|
|
(dwc3_is_usb31(dwc) &&
|
|
|
|
dwc->revision >= DWC3_USB31_REVISION_120A));
|
2016-10-14 13:30:52 +00:00
|
|
|
}
|
|
|
|
|
2016-11-11 01:08:51 +00:00
|
|
|
static void dwc3_check_params(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct device *dev = dwc->dev;
|
|
|
|
|
2016-11-14 20:32:43 +00:00
|
|
|
/* Check for proper value of imod_interval */
|
|
|
|
if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
|
|
|
|
dev_warn(dwc->dev, "Interrupt moderation not supported\n");
|
|
|
|
dwc->imod_interval = 0;
|
|
|
|
}
|
|
|
|
|
2016-11-14 20:32:45 +00:00
|
|
|
/*
|
|
|
|
* Workaround for STAR 9000961433 which affects only version
|
|
|
|
* 3.00a of the DWC_usb3 core. This prevents the controller
|
|
|
|
* interrupt from being masked while handling events. IMOD
|
|
|
|
* allows us to work around this issue. Enable it for the
|
|
|
|
* affected version.
|
|
|
|
*/
|
|
|
|
if (!dwc->imod_interval &&
|
|
|
|
(dwc->revision == DWC3_REVISION_300A))
|
|
|
|
dwc->imod_interval = 1;
|
|
|
|
|
2016-11-11 01:08:51 +00:00
|
|
|
/* Check the maximum_speed parameter */
|
|
|
|
switch (dwc->maximum_speed) {
|
|
|
|
case USB_SPEED_LOW:
|
|
|
|
case USB_SPEED_FULL:
|
|
|
|
case USB_SPEED_HIGH:
|
|
|
|
case USB_SPEED_SUPER:
|
|
|
|
case USB_SPEED_SUPER_PLUS:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev, "invalid maximum_speed parameter %d\n",
|
|
|
|
dwc->maximum_speed);
|
|
|
|
/* fall through */
|
|
|
|
case USB_SPEED_UNKNOWN:
|
|
|
|
/* default to superspeed */
|
|
|
|
dwc->maximum_speed = USB_SPEED_SUPER;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* default to superspeed plus if we are capable.
|
|
|
|
*/
|
|
|
|
if (dwc3_is_usb31(dwc) &&
|
|
|
|
(DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
|
|
|
|
DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
|
|
|
|
dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-14 13:30:52 +00:00
|
|
|
static int dwc3_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
2018-04-19 11:03:37 +00:00
|
|
|
struct resource *res, dwc_res;
|
2016-10-14 13:30:52 +00:00
|
|
|
struct dwc3 *dwc;
|
|
|
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
void __iomem *regs;
|
|
|
|
|
|
|
|
dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
|
|
|
|
if (!dwc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dwc->dev = dev;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "missing memory resource\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->xhci_resources[0].start = res->start;
|
|
|
|
dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
|
|
|
|
DWC3_XHCI_REGS_END;
|
|
|
|
dwc->xhci_resources[0].flags = res->flags;
|
|
|
|
dwc->xhci_resources[0].name = res->name;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Request memory region but exclude xHCI regs,
|
|
|
|
* since it will be requested by the xhci-plat driver.
|
|
|
|
*/
|
2018-04-19 11:03:37 +00:00
|
|
|
dwc_res = *res;
|
|
|
|
dwc_res.start += DWC3_GLOBALS_REGS_START;
|
|
|
|
|
|
|
|
regs = devm_ioremap_resource(dev, &dwc_res);
|
|
|
|
if (IS_ERR(regs))
|
|
|
|
return PTR_ERR(regs);
|
2016-10-14 13:30:52 +00:00
|
|
|
|
|
|
|
dwc->regs = regs;
|
2018-04-19 11:03:37 +00:00
|
|
|
dwc->regs_size = resource_size(&dwc_res);
|
2016-10-14 13:30:52 +00:00
|
|
|
|
|
|
|
dwc3_get_properties(dwc);
|
|
|
|
|
2020-02-25 17:53:04 +00:00
|
|
|
dwc->reset = devm_reset_control_array_get(dev, true, true);
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
if (IS_ERR(dwc->reset))
|
|
|
|
return PTR_ERR(dwc->reset);
|
|
|
|
|
2018-06-12 08:24:48 +00:00
|
|
|
if (dev->of_node) {
|
2020-02-25 17:53:03 +00:00
|
|
|
ret = devm_clk_bulk_get_all(dev, &dwc->clks);
|
2018-06-12 08:24:48 +00:00
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
return ret;
|
|
|
|
/*
|
|
|
|
* Clocks are optional, but new DT platforms should support all
|
|
|
|
* clocks as required by the DT-binding.
|
|
|
|
*/
|
2020-02-25 17:53:03 +00:00
|
|
|
if (ret < 0)
|
2018-06-12 08:24:48 +00:00
|
|
|
dwc->num_clks = 0;
|
2020-02-25 17:53:03 +00:00
|
|
|
else
|
|
|
|
dwc->num_clks = ret;
|
|
|
|
|
2018-06-12 08:24:48 +00:00
|
|
|
}
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
|
|
|
|
ret = reset_control_deassert(dwc->reset);
|
|
|
|
if (ret)
|
2019-07-12 07:26:33 +00:00
|
|
|
return ret;
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
|
2019-07-12 07:26:34 +00:00
|
|
|
ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
if (ret)
|
|
|
|
goto assert_reset;
|
|
|
|
|
usb: dwc3: Fix core validation in probe, move after clocks are enabled
The required clocks needs to be enabled before the first register
access. After commit fe8abf332b8f ("usb: dwc3: support clocks and resets
for DWC3 core"), this happens when the dwc3_core_is_valid function is
called, but the mentioned commit adds that call in the wrong place,
before the clocks are enabled. So, move that call after the
clk_bulk_enable() to ensure the clocks are enabled and the reset
deasserted.
I detected this while, as experiment, I tried to move the clocks and resets
from the glue layer to the DWC3 core on a Samsung Chromebook Plus.
That was not detected before because, in most cases, the glue layer
initializes SoC-specific things and then populates the child "snps,dwc3"
with those clocks already enabled.
Fixes: b873e2d0ea1ef ("usb: dwc3: Do core validation early on probe")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2019-06-13 15:01:07 +00:00
|
|
|
if (!dwc3_core_is_valid(dwc)) {
|
|
|
|
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto disable_clks;
|
|
|
|
}
|
|
|
|
|
2015-05-13 12:26:45 +00:00
|
|
|
platform_set_drvdata(pdev, dwc);
|
2015-05-13 12:26:46 +00:00
|
|
|
dwc3_cache_hwparams(dwc);
|
2015-05-13 12:26:45 +00:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
spin_lock_init(&dwc->lock);
|
|
|
|
|
2016-05-16 10:14:48 +00:00
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
pm_runtime_use_autosuspend(dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
|
2012-02-15 09:27:55 +00:00
|
|
|
pm_runtime_enable(dev);
|
2016-06-10 11:38:02 +00:00
|
|
|
ret = pm_runtime_get_sync(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err1;
|
|
|
|
|
2012-02-15 09:27:55 +00:00
|
|
|
pm_runtime_forbid(dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2012-10-11 10:54:36 +00:00
|
|
|
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate event buffers\n");
|
|
|
|
ret = -ENOMEM;
|
2016-06-10 11:38:02 +00:00
|
|
|
goto err2;
|
2012-10-11 10:54:36 +00:00
|
|
|
}
|
|
|
|
|
2016-09-07 02:22:03 +00:00
|
|
|
ret = dwc3_get_dr_mode(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto err3;
|
2014-02-25 20:00:13 +00:00
|
|
|
|
2016-05-16 07:49:01 +00:00
|
|
|
ret = dwc3_alloc_scratch_buffers(dwc);
|
|
|
|
if (ret)
|
2016-06-10 11:38:02 +00:00
|
|
|
goto err3;
|
2016-05-16 07:49:01 +00:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
ret = dwc3_core_init(dwc);
|
|
|
|
if (ret) {
|
2018-11-07 20:40:29 +00:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize core: %d\n", ret);
|
2016-06-10 11:38:02 +00:00
|
|
|
goto err4;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
}
|
|
|
|
|
2016-11-11 01:08:51 +00:00
|
|
|
dwc3_check_params(dwc);
|
2016-02-06 01:08:59 +00:00
|
|
|
|
2014-04-16 20:13:45 +00:00
|
|
|
ret = dwc3_core_init_mode(dwc);
|
|
|
|
if (ret)
|
2016-06-10 11:38:02 +00:00
|
|
|
goto err5;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2016-04-12 11:10:18 +00:00
|
|
|
dwc3_debugfs_init(dwc);
|
2016-05-16 10:14:48 +00:00
|
|
|
pm_runtime_put(dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2016-06-10 11:38:02 +00:00
|
|
|
err5:
|
2016-05-16 07:49:01 +00:00
|
|
|
dwc3_event_buffers_cleanup(dwc);
|
2018-08-27 15:30:16 +00:00
|
|
|
dwc3_ulpi_exit(dwc);
|
2014-03-03 11:38:11 +00:00
|
|
|
|
2016-06-10 11:38:02 +00:00
|
|
|
err4:
|
2016-05-16 07:49:01 +00:00
|
|
|
dwc3_free_scratch_buffers(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2016-06-10 11:38:02 +00:00
|
|
|
err3:
|
2012-10-11 10:54:36 +00:00
|
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
|
2016-06-10 11:38:02 +00:00
|
|
|
err2:
|
|
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
|
|
|
|
err1:
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
usb: dwc3: Fix core validation in probe, move after clocks are enabled
The required clocks needs to be enabled before the first register
access. After commit fe8abf332b8f ("usb: dwc3: support clocks and resets
for DWC3 core"), this happens when the dwc3_core_is_valid function is
called, but the mentioned commit adds that call in the wrong place,
before the clocks are enabled. So, move that call after the
clk_bulk_enable() to ensure the clocks are enabled and the reset
deasserted.
I detected this while, as experiment, I tried to move the clocks and resets
from the glue layer to the DWC3 core on a Samsung Chromebook Plus.
That was not detected before because, in most cases, the glue layer
initializes SoC-specific things and then populates the child "snps,dwc3"
with those clocks already enabled.
Fixes: b873e2d0ea1ef ("usb: dwc3: Do core validation early on probe")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2019-06-13 15:01:07 +00:00
|
|
|
disable_clks:
|
2019-07-12 07:26:34 +00:00
|
|
|
clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
assert_reset:
|
|
|
|
reset_control_assert(dwc->reset);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-19 18:26:20 +00:00
|
|
|
static int dwc3_remove(struct platform_device *pdev)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
{
|
|
|
|
struct dwc3 *dwc = platform_get_drvdata(pdev);
|
2014-09-02 20:19:43 +00:00
|
|
|
|
2016-05-16 10:14:48 +00:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2014-09-03 21:13:37 +00:00
|
|
|
dwc3_debugfs_exit(dwc);
|
|
|
|
dwc3_core_exit_mode(dwc);
|
2013-01-25 03:00:54 +00:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
dwc3_core_exit(dwc);
|
2015-05-13 12:26:51 +00:00
|
|
|
dwc3_ulpi_exit(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
2013-10-11 13:34:28 +00:00
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
2016-05-16 10:14:48 +00:00
|
|
|
pm_runtime_allow(&pdev->dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2016-05-16 10:14:48 +00:00
|
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
dwc3_free_scratch_buffers(dwc);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-16 10:14:48 +00:00
|
|
|
#ifdef CONFIG_PM
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
static int dwc3_core_init_for_resume(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = reset_control_deassert(dwc->reset);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2019-07-12 07:26:34 +00:00
|
|
|
ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
if (ret)
|
|
|
|
goto assert_reset;
|
|
|
|
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto disable_clks;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
disable_clks:
|
2019-07-12 07:26:34 +00:00
|
|
|
clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
assert_reset:
|
|
|
|
reset_control_assert(dwc->reset);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
|
2012-04-30 11:56:33 +00:00
|
|
|
{
|
2016-05-16 10:14:48 +00:00
|
|
|
unsigned long flags;
|
2018-05-09 17:39:21 +00:00
|
|
|
u32 reg;
|
2012-04-30 11:56:33 +00:00
|
|
|
|
2017-09-27 11:19:20 +00:00
|
|
|
switch (dwc->current_dr_role) {
|
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
2020-02-19 16:20:04 +00:00
|
|
|
if (pm_runtime_suspended(dwc->dev))
|
|
|
|
break;
|
2016-05-16 10:14:48 +00:00
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2012-04-30 11:56:33 +00:00
|
|
|
dwc3_gadget_suspend(dwc);
|
2016-05-16 10:14:48 +00:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2019-03-27 09:56:08 +00:00
|
|
|
synchronize_irq(dwc->irq_gadget);
|
2017-09-27 11:19:20 +00:00
|
|
|
dwc3_core_exit(dwc);
|
2016-05-16 07:52:58 +00:00
|
|
|
break;
|
2017-09-27 11:19:20 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
2018-05-09 17:39:21 +00:00
|
|
|
if (!PMSG_IS_AUTO(msg)) {
|
2018-01-18 11:24:30 +00:00
|
|
|
dwc3_core_exit(dwc);
|
2018-05-09 17:39:21 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Let controller to suspend HSPHY before PHY driver suspends */
|
|
|
|
if (dwc->dis_u2_susphy_quirk ||
|
|
|
|
dwc->dis_enblslpm_quirk) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
|
|
|
|
DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
|
|
|
|
/* Give some time for USB2 PHY to suspend */
|
|
|
|
usleep_range(5000, 6000);
|
|
|
|
}
|
|
|
|
|
|
|
|
phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
|
|
|
|
phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
|
2018-01-18 11:24:30 +00:00
|
|
|
break;
|
2018-02-27 11:30:19 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
|
|
|
/* do nothing during runtime_suspend */
|
|
|
|
if (PMSG_IS_AUTO(msg))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
dwc3_gadget_suspend(dwc);
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2019-03-27 09:56:08 +00:00
|
|
|
synchronize_irq(dwc->irq_gadget);
|
2018-02-27 11:30:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
dwc3_otg_exit(dwc);
|
|
|
|
dwc3_core_exit(dwc);
|
|
|
|
break;
|
2012-04-30 11:56:33 +00:00
|
|
|
default:
|
2016-05-16 07:52:58 +00:00
|
|
|
/* do nothing */
|
2012-04-30 11:56:33 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
|
2012-04-30 11:56:33 +00:00
|
|
|
{
|
2016-05-16 10:14:48 +00:00
|
|
|
unsigned long flags;
|
2014-03-03 11:38:11 +00:00
|
|
|
int ret;
|
2018-05-09 17:39:21 +00:00
|
|
|
u32 reg;
|
2012-04-30 11:56:33 +00:00
|
|
|
|
2017-09-27 11:19:20 +00:00
|
|
|
switch (dwc->current_dr_role) {
|
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
ret = dwc3_core_init_for_resume(dwc);
|
2017-09-27 11:19:20 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-04-11 14:12:34 +00:00
|
|
|
|
2018-03-16 14:44:27 +00:00
|
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
2016-05-16 10:14:48 +00:00
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2012-04-30 11:56:33 +00:00
|
|
|
dwc3_gadget_resume(dwc);
|
2016-05-16 10:14:48 +00:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2017-09-27 11:19:20 +00:00
|
|
|
break;
|
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
2018-01-18 11:24:30 +00:00
|
|
|
if (!PMSG_IS_AUTO(msg)) {
|
usb: dwc3: support clocks and resets for DWC3 core
Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-16 02:41:07 +00:00
|
|
|
ret = dwc3_core_init_for_resume(dwc);
|
2018-01-18 11:24:30 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2018-03-16 14:44:27 +00:00
|
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
|
2018-05-09 17:39:21 +00:00
|
|
|
break;
|
2018-01-18 11:24:30 +00:00
|
|
|
}
|
2018-05-09 17:39:21 +00:00
|
|
|
/* Restore GUSB2PHYCFG bits that were modified in suspend */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
if (dwc->dis_u2_susphy_quirk)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
|
|
|
|
if (dwc->dis_enblslpm_quirk)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
|
|
|
|
phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
|
|
|
|
phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
|
2018-02-27 11:30:19 +00:00
|
|
|
break;
|
|
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
|
|
|
/* nothing to do on runtime_resume */
|
|
|
|
if (PMSG_IS_AUTO(msg))
|
|
|
|
break;
|
|
|
|
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
dwc3_set_prtcap(dwc, dwc->current_dr_role);
|
|
|
|
|
|
|
|
dwc3_otg_init(dwc);
|
|
|
|
if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
|
|
|
|
dwc3_otg_host_init(dwc);
|
|
|
|
} else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
dwc3_gadget_resume(dwc);
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2018-01-18 11:24:30 +00:00
|
|
|
}
|
2018-02-27 11:30:19 +00:00
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
break;
|
2012-04-30 11:56:33 +00:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-05-16 10:14:48 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_checks(struct dwc3 *dwc)
|
|
|
|
{
|
2017-09-27 11:19:20 +00:00
|
|
|
switch (dwc->current_dr_role) {
|
2018-01-18 11:24:30 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
2016-05-16 10:14:48 +00:00
|
|
|
if (dwc->connected)
|
|
|
|
return -EBUSY;
|
|
|
|
break;
|
2018-01-18 11:24:30 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
2016-05-16 10:14:48 +00:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (dwc3_runtime_checks(dwc))
|
|
|
|
return -EBUSY;
|
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
|
2016-05-16 10:14:48 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
device_init_wakeup(dev, true);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
device_init_wakeup(dev, false);
|
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
|
2016-05-16 10:14:48 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-09-27 11:19:20 +00:00
|
|
|
switch (dwc->current_dr_role) {
|
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
2016-05-16 10:14:48 +00:00
|
|
|
dwc3_gadget_process_pending_events(dwc);
|
|
|
|
break;
|
2017-09-27 11:19:20 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
2016-05-16 10:14:48 +00:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_idle(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
|
2017-09-27 11:19:20 +00:00
|
|
|
switch (dwc->current_dr_role) {
|
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
2016-05-16 10:14:48 +00:00
|
|
|
if (dwc3_runtime_checks(dwc))
|
|
|
|
return -EBUSY;
|
|
|
|
break;
|
2017-09-27 11:19:20 +00:00
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
2016-05-16 10:14:48 +00:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
pm_runtime_autosuspend(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int dwc3_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
|
2016-05-16 10:14:48 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
2018-01-18 11:24:30 +00:00
|
|
|
ret = dwc3_resume_common(dwc, PMSG_RESUME);
|
2016-05-16 10:14:48 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-30 11:56:33 +00:00
|
|
|
pm_runtime_disable(dev);
|
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-09 12:27:01 +00:00
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
2012-04-30 11:56:33 +00:00
|
|
|
|
|
|
|
static const struct dev_pm_ops dwc3_dev_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
|
2016-05-16 10:14:48 +00:00
|
|
|
SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
|
|
|
|
dwc3_runtime_idle)
|
2012-04-30 11:56:33 +00:00
|
|
|
};
|
|
|
|
|
2013-01-25 11:06:53 +00:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static const struct of_device_id of_dwc3_match[] = {
|
2013-07-02 18:20:24 +00:00
|
|
|
{
|
|
|
|
.compatible = "snps,dwc3"
|
|
|
|
},
|
2013-01-25 11:06:53 +00:00
|
|
|
{
|
|
|
|
.compatible = "synopsys,dwc3"
|
|
|
|
},
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, of_dwc3_match);
|
|
|
|
#endif
|
|
|
|
|
2014-09-25 07:57:02 +00:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
|
|
|
|
#define ACPI_ID_INTEL_BSW "808622B7"
|
|
|
|
|
|
|
|
static const struct acpi_device_id dwc3_acpi_match[] = {
|
|
|
|
{ ACPI_ID_INTEL_BSW, 0 },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
|
|
|
|
#endif
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
static struct platform_driver dwc3_driver = {
|
|
|
|
.probe = dwc3_probe,
|
2012-11-19 18:21:08 +00:00
|
|
|
.remove = dwc3_remove,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "dwc3",
|
2013-01-25 11:06:53 +00:00
|
|
|
.of_match_table = of_match_ptr(of_dwc3_match),
|
2014-09-25 07:57:02 +00:00
|
|
|
.acpi_match_table = ACPI_PTR(dwc3_acpi_match),
|
2016-05-09 12:27:01 +00:00
|
|
|
.pm = &dwc3_dev_pm_ops,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-02-28 11:57:20 +00:00
|
|
|
module_platform_driver(dwc3_driver);
|
|
|
|
|
2011-10-19 17:39:50 +00:00
|
|
|
MODULE_ALIAS("platform:dwc3");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
2013-06-30 11:15:11 +00:00
|
|
|
MODULE_LICENSE("GPL v2");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
|