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usb: dwc3: set SUSPHY bit for all cores
It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core initialization is completed above the dwc3 revision 1.94a. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -374,6 +374,15 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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/*
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* Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
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* to '0' during coreConsultant configuration. So default value
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* will be '0' when the core is reset. Application needs to set it
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* to '1' after the core initialization is completed.
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*/
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if (dwc->revision > DWC3_REVISION_194A)
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reg |= DWC3_GUSB3PIPECTL_SUSPHY;
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if (dwc->u2ss_inp3_quirk)
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reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
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@ -395,6 +404,21 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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mdelay(100);
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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/*
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* Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
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* '0' during coreConsultant configuration. So default value will
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* be '0' when the core is reset. Application needs to set it to
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* '1' after the core initialization is completed.
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*/
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if (dwc->revision > DWC3_REVISION_194A)
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reg |= DWC3_GUSB2PHYCFG_SUSPHY;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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mdelay(100);
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}
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/**
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