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usb: dwc3: core: improve reset sequence
According to Synopsys Databook, we shouldn't be relying on GCTL.CORESOFTRESET bit as that's only for debugging purposes. Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode. Host side block will be reset by XHCI driver if necessary. Note that this reduces amount of time spent on dwc3_probe() by a long margin. We're still gonna wait for reset to finish for a long time (default to 1ms max), but tests show that the reset polling loop executed at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000 times in a row). Suggested-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -67,23 +67,9 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
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static int dwc3_core_soft_reset(struct dwc3 *dwc)
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{
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u32 reg;
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int retries = 1000;
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int ret;
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/* Before Resetting PHY, put Core in Reset */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg |= DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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/* Assert USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Assert USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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usb_phy_init(dwc->usb2_phy);
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usb_phy_init(dwc->usb3_phy);
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ret = phy_init(dwc->usb2_generic_phy);
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@ -95,26 +81,28 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
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phy_exit(dwc->usb2_generic_phy);
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return ret;
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}
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mdelay(100);
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/* Clear USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/*
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* We're resetting only the device side because, if we're in host mode,
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* XHCI driver will reset the host block. If dwc3 was configured for
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* host-only mode, then we can return early.
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*/
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if (dwc->dr_mode == USB_DR_MODE_HOST)
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return 0;
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/* Clear USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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reg |= DWC3_DCTL_CSFTRST;
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dwc3_writel(dwc->regs, DWC3_DCTL, reg);
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mdelay(100);
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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if (!(reg & DWC3_DCTL_CSFTRST))
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return 0;
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/* After PHYs are stable we can take Core out of reset state */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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udelay(1);
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} while (--retries);
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return 0;
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return -ETIMEDOUT;
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}
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/**
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