Prepare v2016.05-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>

Kconfig

@@ -1,6 +1,7 @@
 #
 # For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
+# see the file Documentation/kbuild/kconfig-language.txt in the
+# Linux kernel source tree.
 #
 mainmenu "U-Boot $UBOOTVERSION Configuration"
 
@@ -17,7 +18,7 @@ config LOCALVERSION
 	string "Local version - append to U-Boot release"
 	help
 	  Append an extra string to the end of your U-Boot version.
-	  This will show up on your boot log, for example.
+	  This will show up in your boot log, for example.
 	  The string you set here will be appended after the contents of
 	  any files with a filename matching localversion* in your
 	  object and source tree, in that order.  Your total string can
@@ -28,11 +29,11 @@ config LOCALVERSION_AUTO
 	default y
 	help
 	  This will try to automatically determine if the current tree is a
-	  release tree by looking for git tags that belong to the current
+	  release tree by looking for Git tags that belong to the current
 	  top of tree revision.
 
 	  A string of the format -gxxxxxxxx will be added to the localversion
-	  if a git-based tree is found.  The string generated by this will be
+	  if a Git-based tree is found.  The string generated by this will be
 	  appended after any matching localversion* files, and after the value
 	  set in CONFIG_LOCALVERSION.
 
@@ -56,7 +57,7 @@ config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
 	default y if DM
 	help
-	  Before relocation memory is very limited on many platforms. Still,
+	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
@@ -66,7 +67,7 @@ config SYS_MALLOC_F_LEN
 	depends on SYS_MALLOC_F
 	default 0x400
 	help
-	  Before relocation memory is very limited on many platforms. Still,
+	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
@@ -78,7 +79,7 @@ menuconfig EXPERT
 	  This option allows certain base U-Boot options and settings
 	  to be disabled or tweaked. This is for specialized
 	  environments which can tolerate a "non-standard" U-Boot.
-	  Only use this if you really know what you are doing.
+	  Use this only if you really know what you are doing.
 
 if EXPERT
 	config SYS_MALLOC_CLEAR_ON_INIT
@@ -95,7 +96,7 @@ if EXPERT
 	  Then the boot time can be significantly reduced.
 	  Warning:
 	  When disabling this, please check if malloc calls, maybe
-	  should be replaced by calloc - if expects zeroed memory.
+	  should be replaced by calloc - if one expects zeroed memory.
 endif
 endmenu		# General setup
 
@@ -117,10 +118,10 @@ config SPL
 config SPL_SYS_MALLOC_SIMPLE
 	bool
 	depends on SPL
-	prompt "Only use malloc_simple functions in the spl"
+	prompt "Only use malloc_simple functions in the SPL"
 	help
 	  Say Y here to only use the *_simple malloc functions from
-	  malloc_simple.c, rather then using the versions from dlmalloc.c
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
 	  this will make the SPL binary smaller at the cost of more heap
 	  usage as the *_simple malloc functions do not re-use free-ed mem.
 

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 NAME =
 
 # *DOCUMENTATION*

arch/arm/Kconfig

@@ -538,6 +538,7 @@ config TARGET_CM_T43
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
+	select CMD_GPIO
 	select CMD_USB
 	select DM
 	select DM_ETH
@@ -579,6 +580,7 @@ config ARCH_ZYNQ
 	select SPL_OF_CONTROL if SPL
 	select DM
 	select DM_ETH
+	select DM_GPIO
 	select SPL_DM if SPL
 	select DM_MMC
 	select DM_SPI
@@ -591,8 +593,6 @@ config ARCH_ZYNQMP
 	select ARM64
 	select DM
 	select OF_CONTROL
-	select DM_ETH
-	select DM_MMC
 	select DM_SERIAL
 
 config TEGRA

arch/arm/cpu/arm926ejs/mx27/reset.c

@@ -27,14 +27,14 @@ void reset_cpu(ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
-	writel(0x00000000, &regs->wcr);
+	writew(0x0000, &regs->wcr);
 
 	/* Write Service Sequence */
-	writel(0x00005555, &regs->wsr);
-	writel(0x0000AAAA, &regs->wsr);
+	writew(0x5555, &regs->wsr);
+	writew(0xAAAA, &regs->wsr);
 
 	/* Enable watchdog */
-	writel(WCR_WDE, &regs->wcr);
+	writew(WCR_WDE, &regs->wcr);
 
 	while (1);
 	/*NOTREACHED*/

arch/arm/cpu/armv7/mx6/Kconfig

@@ -60,6 +60,18 @@ config TARGET_CM_FX6
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 
+config TARGET_GE_B450V3
+	bool "General Electric B450v3"
+	select MX6Q
+
+config TARGET_GE_B650V3
+	bool "General Electric B650v3"
+	select MX6Q
+
+config TARGET_GE_B850V3
+	bool "General Electric B850v3"
+	select MX6Q
+
 config TARGET_GW_VENTANA
 	bool "gw_ventana"
 	select SUPPORT_SPL
@@ -92,12 +104,14 @@ config TARGET_MX6SLEVK
 
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
+	select MX6SX
 	select SUPPORT_SPL
 	select DM
 	select DM_THERMAL
 
 config TARGET_MX6SXSABREAUTO
         bool "mx6sxsabreauto"
+	select MX6SX
         select DM
         select DM_THERMAL
 
@@ -153,16 +167,25 @@ config TARGET_WANDBOARD
 config TARGET_WARP
 	bool "WaRP"
 
+config TARGET_XPRESS
+	bool "CCV xPress"
+	select MX6UL
+	select DM
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 endchoice
 
 config SYS_SOC
 	default "mx6"
 
+source "board/ge/bx50v3/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
+source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/embest/mx6boards/Kconfig"

arch/arm/cpu/armv7/mx6/clock.c

@@ -1183,6 +1183,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("PLL_NET    %8d MHz\n", freq / 1000000);
 
 	printf("\n");
+	printf("ARM        %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 #ifdef CONFIG_MXC_SPI

arch/arm/cpu/armv7/mx6/ddr.c

@@ -12,40 +12,20 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/types.h>
+#include <wait_bit.h>
 
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
-	unsigned int timeout = 1000;
-	u32 val;
-
-	while (--timeout) {
-		val = readl(reg);
-		if (!set)
-			val = ~val;
-
-		if ((val & mask) == mask)
-			return 0;
-
-		udelay(1);
-	}
-
-	printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
-	      __func__, reg, mask, set);
-	hang();	/* DRAM couldn't be calibrated, game over :-( */
-}
-
 static void reset_read_data_fifos(void)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 
 	/* Reset data FIFOs twice. */
 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-	wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 
 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-	wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 }
 
 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
@@ -60,12 +40,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable)
 	 */
 	if (cs0_enable) { /* CS0 */
 		writel(0x04008050, &mmdc0->mdscr);
-		wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+		wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
 	}
 
 	if (cs1_enable) { /* CS1 */
 		writel(0x04008058, &mmdc0->mdscr);
-		wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+		wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
 	}
 }
 
@@ -164,7 +144,7 @@ int mmdc_do_write_level_calibration(void)
 	 * 7. Upon completion of this process the MMDC de-asserts
 	 * the MPWLGCR[HW_WL_EN]
 	 */
-	wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0);
+	wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
 
 	/*
 	 * 8. check for any errors: check both PHYs for x64 configuration,
@@ -289,7 +269,7 @@ int mmdc_do_dqs_calibration(void)
 		writel(0x00008028, &mmdc0->mdscr);
 
 	/* poll to make sure the con_ack bit was asserted */
-	wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+	wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
 
 	/*
 	 * Check MDMISC register CALIB_PER_CS to see which CS calibration
@@ -327,7 +307,7 @@ int mmdc_do_dqs_calibration(void)
 	 * this bit until it clears to indicate completion of the write access.
 	 */
 	setbits_le32(&mmdc0->mpswdar0, 1);
-	wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0);
+	wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
 
 	/* Set the RD_DL_ABS# bits to their default values
 	 * (will be calibrated later in the read delay-line calibration).
@@ -372,7 +352,7 @@ int mmdc_do_dqs_calibration(void)
 	setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
 
 	/* Poll for completion.  MPDGCTRL0[HW_DG_EN] should be 0 */
-	wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0);
+	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
 
 	/*
 	 * Check to see if any errors were encountered during calibration
@@ -431,7 +411,7 @@ int mmdc_do_dqs_calibration(void)
 	 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0.   Also, ensure that
 	 * no error bits were set.
 	 */
-	wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0);
+	wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
 
 	/* check both PHYs for x64 configuration, if x32, check only PHY0 */
 	if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
@@ -484,7 +464,7 @@ int mmdc_do_dqs_calibration(void)
 	 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
 	 * Also, ensure that no error bits were set.
 	 */
-	wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0);
+	wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
 
 	/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
 	if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
@@ -532,7 +512,7 @@ int mmdc_do_dqs_calibration(void)
 	writel(0x0, &mmdc0->mdscr);	/* CS0 */
 
 	/* Poll to make sure the con_ack bit is clear */
-	wait_for_bit(&mmdc0->mdscr, 1 << 14, 0);
+	wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
 
 	/*
 	 * Print out the registers that were updated as a result

arch/arm/cpu/armv7/mx6/soc.c

@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }
 
@@ -325,15 +328,30 @@ int arch_cpu_init(void)
 	 */
 	init_bandgap();
 
-	/*
-	 * When low freq boot is enabled, ROM will not set AHB
-	 * freq, so we need to ensure AHB freq is 132MHz in such
-	 * scenario.
-	 */
-	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
-		set_ahb_rate(132000000);
+	if (!IS_ENABLED(CONFIG_MX6UL)) {
+		/*
+		 * When low freq boot is enabled, ROM will not set AHB
+		 * freq, so we need to ensure AHB freq is 132MHz in such
+		 * scenario.
+		 *
+		 * To i.MX6UL, when power up, default ARM core and
+		 * AHB rate is 396M and 132M.
+		 */
+		if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+			set_ahb_rate(132000000);
+	}
 
-		/* Set perclk to source from OSC 24MHz */
+	if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
+		/*
+		 * According to the design team's requirement on i.MX6UL,
+		 * the PMIC_STBY_REQ PAD should be configured as open
+		 * drain 100K (0x0000b8a0).
+		 * Only exists on TO1.0
+		 */
+		writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+	}
+
+	/* Set perclk to source from OSC 24MHz */
 #if defined(CONFIG_MX6SL)
 	set_preclk_from_osc();
 #endif

arch/arm/cpu/armv7/mx7/Kconfig

@@ -15,6 +15,13 @@ choice
 
 config TARGET_MX7DSABRESD
 	bool "mx7dsabresd"
+	select MX7D
+	select DM
+	select DM_THERMAL
+
+config TARGET_WARP7
+	bool "warp7"
+	select MX7D
 	select DM
 	select DM_THERMAL
 
@@ -24,5 +31,6 @@ config SYS_SOC
 	default "mx7"
 
 source "board/freescale/mx7dsabresd/Kconfig"
+source "board/warp7/Kconfig"
 
 endif

arch/arm/cpu/armv7/mx7/soc.c

@@ -165,6 +165,21 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 	return val;
 }
 
+static bool is_mx7d(void)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+	int val;
+
+	val = readl(&fuse->tester4);
+	if (val & 1)
+		return false;
+	else
+		return true;
+}
+
 u32 get_cpu_rev(void)
 {
 	struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
@@ -172,6 +187,9 @@ u32 get_cpu_rev(void)
 	u32 reg = readl(&ccm_anatop->digprog);
 	u32 type = (reg >> 16) & 0xff;
 
+	if (!is_mx7d())
+		type = MXC_CPU_MX7S;
+
 	reg &= 0xff;
 	return (type << 12) | reg;
 }

arch/arm/cpu/armv8/start.S

@@ -201,15 +201,6 @@ ENDPROC(apply_core_errata)
 WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
-#ifndef CONFIG_ARMV8_MULTIENTRY
-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-	/*
-	 * For single-entry systems the lowlevel init is very simple.
-	 */
-	ldr	x0, =GICD_BASE
-	bl	gic_init_secure
-#endif
-#else /* CONFIG_ARMV8_MULTIENTRY is set */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	branch_if_slave x0, 1f
 	ldr	x0, =GICD_BASE
@@ -222,7 +213,6 @@ WEAK(lowlevel_init)
 	ldr	x0, =GICD_BASE
 	ldr	x1, =GICC_BASE
 	bl	gic_init_secure_percpu
-#endif
 #endif
 
 	branch_if_master x0, x1, 2f

arch/arm/dts/Makefile

@@ -81,7 +81,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
-	zynqmp-ep108.dtb
+	zynqmp-ep108.dtb			\
+	zynqmp-zcu102.dtb			\
+	zynqmp-zcu102-revB.dtb			\
+	zynqmp-zc1751-xm015-dc1.dtb		\
+	zynqmp-zc1751-xm016-dc2.dtb		\
+	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
@@ -207,6 +212,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-sinovoip-bpi-m3.dtb
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-2.dtb \
+	sun8i-h3-orangepi-one.dtb \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \

arch/arm/dts/am437x-gp-evm.dts

@@ -573,7 +573,7 @@
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &mmc3 {

arch/arm/dts/am437x-sk-evm.dts

@@ -536,7 +536,7 @@
 
 	vmmc-supply = <&dcdc4>;
 	bus-width = <4>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &usb2_phy1 {

arch/arm/dts/am57xx-beagle-x15.dts

@@ -586,7 +586,7 @@
 	vmmc_aux-supply = <&vdd_3v3>;
 	pbias-supply = <&pbias_mmc_reg>;
 	bus-width = <4>;
-	cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
 };
 
 &mmc2 {

arch/arm/dts/dra7-evm.dts

@@ -469,6 +469,11 @@
 	status = "okay";
 	vmmc-supply = <&ldo1_reg>;
 	bus-width = <4>;
+	/*
+	 * SDCD signal is not being used here - using the fact that GPIO mode
+	 * is always hardwired.
+	 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 };
 
 &mmc2 {

arch/arm/dts/dra72-evm.dts

@@ -503,7 +503,7 @@
 	 * SDCD signal is not being used here - using the fact that GPIO mode
 	 * is a viable alternative
 	 */
-	cd-gpios = <&gpio6 27 0>;
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 };
 
 &mmc2 {

arch/arm/dts/socfpga_arria5_socdk.dts

@@ -21,7 +21,7 @@
 	};
 
 	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
+		/* this allow the ethaddr uboot environment variable contents
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;

arch/arm/dts/socfpga_cyclone5_socdk.dts

@@ -21,7 +21,7 @@
 	};
 
 	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
+		/* this allow the ethaddr uboot environment variable contents
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;

arch/arm/dts/socfpga_cyclone5_socrates.dts

@@ -15,6 +15,11 @@
 	};
 
 	aliases {
+		/*
+		 * This allows the ethaddr uboot environment variable
+		 * contents to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
 		udc0 = &usb1;
 	};
 

arch/arm/dts/socfpga_cyclone5_sr1500.dts

@@ -16,7 +16,7 @@
 
 	aliases {
 		/*
-		 * This allows the ethaddr uboot environmnet variable
+		 * This allows the ethaddr uboot environment variable
 		 * contents to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;

arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts

@@ -57,8 +57,16 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_b>;
 	status = "okay";
 };
+
+&usb_otg {
+	status = "okay";
+};

arch/arm/dts/sun8i-h3-orangepi-one.dts

@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi One";
+	compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+		pwr_led {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		status_led {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	r_gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sw_r_opc>;
+
+		sw4 {
+			label = "sw4";
+			linux,code = <BTN_0>;
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pio {
+	leds_opc: led_pins@0 {
+		allwinner,pins = "PA15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	leds_r_opc: led_pins@0 {
+		allwinner,pins = "PL10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	sw_r_opc: key_pins@0 {
+		allwinner,pins = "PL3";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	/* USB VBUS is always on */
+	status = "okay";
+};

arch/arm/dts/zynq-7000.dtsi

@@ -96,8 +96,10 @@
 		gpio0: gpio@e000a000 {
 			compatible = "xlnx,zynq-gpio-1.0";
 			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
 			clocks = <&clkc 42>;
 			gpio-controller;
+			interrupt-controller;
 			interrupt-parent = <&intc>;
 			interrupts = <0 20 4>;
 			reg = <0xe000a000 0x1000>;
@@ -270,6 +272,13 @@
 				reg = <0x100 0x100>;
 			};
 
+			rstc: rstc@200 {
+				compatible = "xlnx,zynq-reset";
+				reg = <0x200 0x48>;
+				#reset-cells = <1>;
+				syscon = <&slcr>;
+			};
+
 			pinctrl0: pinctrl@700 {
 				compatible = "xlnx,pinctrl-zynq";
 				reg = <0x700 0x200>;
@@ -297,7 +306,12 @@
 
 		devcfg: devcfg@f8007000 {
 			compatible = "xlnx,zynq-devcfg-1.0";
+			interrupt-parent = <&intc>;
+			interrupts = <0 8 4>;
 			reg = <0xf8007000 0x100>;
+			clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
+			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
+			syscon = <&slcr>;
 		};
 
 		global_timer: timer@f8f00200 {

arch/arm/dts/zynq-microzed.dts

@@ -1,7 +1,7 @@
 /*
  * Xilinx MicroZED board DTS
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2016 Xilinx, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -15,12 +15,27 @@
 	aliases {
 		serial0 = &uart1;
 		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
 		device_type = "memory";
 		reg = <0 0x40000000>;
 	};
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
 };
 
 &qspi {
@@ -32,3 +47,24 @@
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};

arch/arm/dts/zynq-zc702.dts

@@ -27,7 +27,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -91,6 +91,8 @@
 	phy-handle = <&ethernet_phy>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem0_default>;
+	phy-reset-gpio = <&gpio0 11 0>;
+	phy-reset-active-low;
 
 	ethernet_phy: ethernet-phy@7 {
 		reg = <7>;
@@ -128,6 +130,21 @@
 			};
 		};
 
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			adv7511: hdmi-tx@39 {
+				compatible = "adi,adv7511";
+				reg = <0x39>;
+				adi,input-depth = <8>;
+				adi,input-colorspace = "yuv422";
+				adi,input-clock = "1x";
+				adi,input-style = <3>;
+				adi,input-justification = "right";
+			};
+		};
+
 		i2c@2 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -370,6 +387,11 @@
 	};
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
@@ -384,11 +406,6 @@
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

arch/arm/dts/zynq-zc706.dts

@@ -27,7 +27,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -84,6 +84,21 @@
 			};
 		};
 
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			adv7511: hdmi-tx@39 {
+				compatible = "adi,adv7511";
+				reg = <0x39>;
+				adi,input-depth = <8>;
+				adi,input-colorspace = "yuv422";
+				adi,input-clock = "1x";
+				adi,input-style = <3>;
+				adi,input-justification = "evenly";
+			};
+		};
+
 		i2c@2 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -291,6 +306,11 @@
 	};
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
@@ -305,11 +325,6 @@
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

arch/arm/dts/zynq-zc770-xm010.dts

@@ -21,7 +21,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -36,27 +36,6 @@
 	};
 };
 
-&spi1 {
-	status = "okay";
-	num-cs = <4>;
-	is-decoded-cs = <0>;
-	flash@0 {
-		compatible = "sst25wf080";
-		reg = <1>;
-		spi-max-frequency = <1000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@test {
-			label = "spi-flash";
-			reg = <0x0 0x100000>;
-		};
-	};
-};
-
-&qspi {
-	status = "okay";
-};
-
 &can0 {
 	status = "okay";
 };
@@ -82,10 +61,31 @@
 
 };
 
+&qspi {
+	status = "okay";
+};
+
 &sdhci0 {
 	status = "okay";
 };
 
+&spi1 {
+	status = "okay";
+	num-cs = <4>;
+	is-decoded-cs = <0>;
+	flash@0 {
+		compatible = "sst25wf080";
+		reg = <1>;
+		spi-max-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@test {
+			label = "spi-flash";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
 &uart1 {
 	u-boot,dm-pre-reloc;
 	status = "okay";

arch/arm/dts/zynq-zc770-xm011.dts

@@ -7,6 +7,7 @@
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
+
 / {
 	compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
 	model = "Xilinx Zynq";
@@ -18,7 +19,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 

arch/arm/dts/zynq-zc770-xm012.dts

@@ -20,7 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 

arch/arm/dts/zynq-zc770-xm013.dts

@@ -16,11 +16,12 @@
 		ethernet0 = &gem1;
 		i2c0 = &i2c1;
 		serial0 = &uart0;
-		spi0 = &spi0;
+		spi0 = &qspi;
+		spi1 = &spi0;
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -58,6 +59,10 @@
 	};
 };
 
+&qspi {
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	num-cs = <4>;

arch/arm/dts/zynq-zed.dts

@@ -26,7 +26,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -50,6 +50,11 @@
 	};
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
@@ -60,11 +65,6 @@
 	status = "okay";
 };
 
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

arch/arm/dts/zynq-zybo.dts

@@ -26,13 +26,13 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
 	usb_phy0: phy0 {
-		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 		reset-gpios = <&gpio0 46 1>;
 	};
 };
@@ -51,6 +51,11 @@
 	};
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
@@ -61,11 +66,6 @@
 	status = "okay";
 };
 
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

arch/arm/dts/zynqmp-clk.dtsi

@@ -0,0 +1,202 @@
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+&amba {
+	clk100: clk100 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk125: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clk200: clk200 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	clk250: clk250 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
+
+	clk300: clk300 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <300000000>;
+	};
+
+	clk600: clk600 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <600000000>;
+	};
+
+	dp_aclk: clock0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-accuracy = <100>;
+	};
+
+	dp_aud_clk: clock1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+		clock-accuracy = <100>;
+	};
+
+	dpdma_clk: dpdma_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <533000000>;
+	};
+
+	drm_clock: drm_clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <262750000>;
+		clock-accuracy = <0x64>;
+	};
+};
+
+&can0 {
+	clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+	clocks = <&clk100 &clk100>;
+};
+
+&fpd_dma_chan1 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&nand0 {
+	clocks = <&clk100 &clk100>;
+};
+
+&gem0 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem1 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem2 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem3 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gpio {
+	clocks = <&clk100>;
+};
+
+&i2c0 {
+	clocks = <&clk100>;
+};
+
+&i2c1 {
+	clocks = <&clk100>;
+};
+
+&qspi {
+	clocks = <&clk300 &clk300>;
+};
+
+&sata {
+	clocks = <&clk250>;
+};
+
+&sdhci0 {
+	clocks = <&clk200 &clk200>;
+};
+
+&sdhci1 {
+	clocks = <&clk200 &clk200>;
+};
+
+&spi0 {
+	clocks = <&clk200 &clk200>;
+};
+
+&spi1 {
+	clocks = <&clk200 &clk200>;
+};
+
+&uart0 {
+	clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+	clocks = <&clk100 &clk100>;
+};
+
+&usb0 {
+	clocks = <&clk250>, <&clk250>;
+};
+
+&usb1 {
+	clocks = <&clk250>, <&clk250>;
+};
+
+&xilinx_drm {
+	clocks = <&drm_clock>;
+};
+
+&xlnx_dp {
+	clocks = <&dp_aclk>, <&dp_aud_clk>;
+};
+
+&xlnx_dpdma {
+	clocks = <&dpdma_clk>;
+};
+
+&xlnx_dp_snd_codec0 {
+	clocks = <&dp_aud_clk>;
+};

arch/arm/dts/zynqmp-ep108-clk.dtsi

@@ -62,6 +62,10 @@
 	clocks = <&i2c_clk>;
 };
 
+&nand0 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
 &qspi {
 	clocks = <&misc_clk &misc_clk>;
 };

arch/arm/dts/zynqmp-ep108.dts

@@ -10,17 +10,21 @@
 
 /dts-v1/;
 
-/include/ "zynqmp.dtsi"
-/include/ "zynqmp-ep108-clk.dtsi"
+#include "zynqmp.dtsi"
+#include "zynqmp-ep108-clk.dtsi"
 
 / {
 	model = "ZynqMP EP108";
 
 	aliases {
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
 		serial0 = &uart0;
 		spi0 = &qspi;
 		spi1 = &spi0;
 		spi2 = &spi1;
+		usb0 = &usb0;
+		usb1 = &usb1;
 	};
 
 	chosen {
@@ -29,7 +33,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x0 0x0 0x40000000>;
+		reg = <0x0 0x0 0x0 0x40000000>;
 	};
 };
 
@@ -69,10 +73,41 @@
 	};
 };
 
+&nand0 {
+	status = "okay";
+	arasan,has-mdma;
+	num-cs = <1>;
+
+	partition@0 {	/* for testing purpose */
+		label = "nand-fsbl-uboot";
+		reg = <0x0 0x0 0x400000>;
+	};
+	partition@1 {	/* for testing purpose */
+		label = "nand-linux";
+		reg = <0x0 0x400000 0x1400000>;
+	};
+	partition@2 {	/* for testing purpose */
+		label = "nand-device-tree";
+		reg = <0x0 0x1800000 0x400000>;
+	};
+	partition@3 {	/* for testing purpose */
+		label = "nand-rootfs";
+		reg = <0x0 0x1C00000 0x1400000>;
+	};
+	partition@4 {	/* for testing purpose */
+		label = "nand-bitstream";
+		reg = <0x0 0x3000000 0x400000>;
+	};
+	partition@5 {	/* for testing purpose */
+		label = "nand-misc";
+		reg = <0x0 0x3400000 0xFCC00000>;
+	};
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
-		compatible = "n25q512a11";
+		compatible = "m25p80";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
@@ -101,10 +136,20 @@
 &sata {
 	status = "okay";
 	ceva,broken-gen2;
+	/* SATA Phy OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+	ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+	ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+	ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+	ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+	ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 };
 
 &sdhci0 {
 	status = "okay";
+	bus-width = <8>;
 };
 
 &sdhci1 {
@@ -151,12 +196,20 @@
 
 &usb0 {
 	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
 	dr_mode = "peripheral";
 	maximum-speed = "high-speed";
 };
 
 &usb1 {
 	status = "okay";
+};
+
+&dwc3_1 {
+	status = "okay";
 	dr_mode = "host";
 	maximum-speed = "high-speed";
 };

arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts

@@ -0,0 +1,211 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP zc1751-xm015-dc1 RevA";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c1;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem3 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@0 {
+		reg = <0>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+	eeprom@55 {
+		compatible = "at,24c64"; /* 24AA64 */
+		reg = <0x55>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>; /* Based on DC1 spec */
+		partition@qspi-fsbl-uboot { /* for testing purpose */
+			label = "qspi-fsbl-uboot";
+			reg = <0x0 0x100000>;
+		};
+		partition@qspi-linux { /* for testing purpose */
+			label = "qspi-linux";
+			reg = <0x100000 0x500000>;
+		};
+		partition@qspi-device-tree { /* for testing purpose */
+			label = "qspi-device-tree";
+			reg = <0x600000 0x20000>;
+		};
+		partition@qspi-rootfs { /* for testing purpose */
+			label = "qspi-rootfs";
+			reg = <0x620000 0x5E0000>;
+		};
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+	/* SATA phy OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+	status = "okay";
+	bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+	status = "okay";
+	no-1-8-v;       /* for 1.0 silicon */
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&xilinx_drm {
+	status = "okay";
+};
+
+&xlnx_dp {
+	status = "okay";
+};
+
+&xlnx_dp_sub {
+	status = "okay";
+	xlnx,vid-clk-pl;
+};
+
+&xlnx_dp_snd_pcm0 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_pcm1 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_card {
+	status = "okay";
+};
+
+&xlnx_dp_snd_codec0 {
+	status = "okay";
+};
+
+&xlnx_dpdma {
+	status = "okay";
+};

arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts

@@ -0,0 +1,236 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP zc1751-xm016-dc2 RevA";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		can0 = &can0;
+		can1 = &can1;
+		ethernet0 = &gem2;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		usb0 = &usb1;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem2 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@5 {
+		reg = <5>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tca6416_u26: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/* IRQ not connected */
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&nand0 {
+	status = "okay";
+	arasan,has-mdma;
+	num-cs = <2>;
+
+	partition@0 {	/* for testing purpose */
+		label = "nand-fsbl-uboot";
+		reg = <0x0 0x0 0x400000>;
+	};
+	partition@1 {	/* for testing purpose */
+		label = "nand-linux";
+		reg = <0x0 0x400000 0x1400000>;
+	};
+	partition@2 {	/* for testing purpose */
+		label = "nand-device-tree";
+		reg = <0x0 0x1800000 0x400000>;
+	};
+	partition@3 {	/* for testing purpose */
+		label = "nand-rootfs";
+		reg = <0x0 0x1C00000 0x1400000>;
+	};
+	partition@4 {	/* for testing purpose */
+		label = "nand-bitstream";
+		reg = <0x0 0x3000000 0x400000>;
+	};
+	partition@5 {	/* for testing purpose */
+		label = "nand-misc";
+		reg = <0x0 0x3400000 0xFCC00000>;
+	};
+
+	partition@6 {	/* for testing purpose */
+		label = "nand1-fsbl-uboot";
+		reg = <0x1 0x0 0x400000>;
+	};
+	partition@7 {	/* for testing purpose */
+		label = "nand1-linux";
+		reg = <0x1 0x400000 0x1400000>;
+	};
+	partition@8 {	/* for testing purpose */
+		label = "nand1-device-tree";
+		reg = <0x1 0x1800000 0x400000>;
+	};
+	partition@9 {	/* for testing purpose */
+		label = "nand1-rootfs";
+		reg = <0x1 0x1C00000 0x1400000>;
+	};
+	partition@10 {	/* for testing purpose */
+		label = "nand1-bitstream";
+		reg = <0x1 0x3000000 0x400000>;
+	};
+	partition@11 {	/* for testing purpose */
+		label = "nand1-misc";
+		reg = <0x1 0x3400000 0xFCC00000>;
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	num-cs = <1>;
+	spi0_flash0: spi0_flash0@0 {
+		compatible = "m25p80";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+
+		spi0_flash0@00000000 {
+			label = "spi0_flash0";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
+&spi1 {
+	status = "okay";
+	num-cs = <1>;
+	spi1_flash0: spi1_flash0@0 {
+		compatible = "mtd_dataflash";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+
+		spi1_flash0@00000000 {
+			label = "spi1_flash0";
+			reg = <0x0 0x84000>;
+		};
+	};
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};

arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts

@@ -0,0 +1,121 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+/ {
+	model = "ZynqMP zc1751-xm019-dc5 RevA";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem1;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem1 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@0 {
+		reg = <0>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+/* FIXME: Add device */
+&i2c0 {
+	status = "okay";
+};
+
+/* FIXME: Add device */
+&i2c1 {
+	status = "okay";
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};

arch/arm/dts/zynqmp-zcu102-revB.dts

@@ -0,0 +1,42 @@
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevB
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "zynqmp-zcu102.dts"
+
+/ {
+	model = "ZynqMP ZCU102 RevB";
+};
+
+&gem3 {
+	phy-handle = <&phyc>;
+	phyc: phy@c {
+		reg = <0xc>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+	};
+	/* Cleanup from RevA */
+	/delete-node/ phy@21;
+};
+
+/* Different qspi 512Mbit version */
+
+/* Fix collision with u61 */
+&i2c0 {
+	i2cswitch@75 {
+		i2c@2 {
+			max15303@1b { /* u8 */
+				compatible = "max15303";
+				reg = <0x1b>;
+			};
+			/delete-node/ max15303@20;
+		};
+	};
+};

arch/arm/dts/zynqmp-zcu102.dts

@@ -0,0 +1,631 @@
+/*
+ * dts file for Xilinx ZynqMP ZCU102
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP ZCU102 RevA";
+	compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&can1 {
+	status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem3 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@21 {
+		reg = <21>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tca6416_u97: gpio@20 {
+		/*
+		 * Enable all GTs to out from U-Boot
+		 * i2c mw 20 6 0  - setup IO to output
+		 * i2c mw 20 2 ef - setup output values on pins 0-7
+		 * i2c mw 20 3 ff - setup output values on pins 10-17
+		 */
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * IRQ not connected
+		 * Lines:
+		 * 0 - PS_GTR_LAN_SEL0
+		 * 1 - PS_GTR_LAN_SEL1
+		 * 2 - PS_GTR_LAN_SEL2
+		 * 3 - PS_GTR_LAN_SEL3
+		 * 4 - PCI_CLK_DIR_SEL
+		 * 5 - IIC_MUX_RESET_B
+		 * 6 - GEM3_EXP_RESET_B
+		 * 7, 10 - 17 - not connected
+		 */
+
+		gtr_sel0 {
+			gpio-hog;
+			gpios = <0 0>;
+			output-high; /* PCIE = 0, DP = 1 */
+			line-name = "sel0";
+		};
+		gtr_sel1 {
+			gpio-hog;
+			gpios = <1 0>;
+			output-high; /* PCIE = 0, DP = 1 */
+			line-name = "sel1";
+		};
+		gtr_sel2 {
+			gpio-hog;
+			gpios = <2 0>;
+			output-high; /* PCIE = 0, USB0 = 1 */
+			line-name = "sel2";
+		};
+		gtr_sel3 {
+			gpio-hog;
+			gpios = <3 0>;
+			output-high; /* PCIE = 0, SATA = 1 */
+			line-name = "sel3";
+		};
+	};
+
+	tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * IRQ not connected
+		 * Lines:
+		 * 0 - VCCPSPLL_EN
+		 * 1 - MGTRAVCC_EN
+		 * 2 - MGTRAVTT_EN
+		 * 3 - VCCPSDDRPLL_EN
+		 * 4 - MIO26_PMU_INPUT_LS
+		 * 5 - PL_PMBUS_ALERT
+		 * 6 - PS_PMBUS_ALERT
+		 * 7 - MAXIM_PMBUS_ALERT
+		 * 10 - PL_DDR4_VTERM_EN
+		 * 11 - PL_DDR4_VPP_2V5_EN
+		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+		 * 13 - PS_DIMM_SUSPEND_EN
+		 * 14 - PS_DDR4_VTERM_EN
+		 * 15 - PS_DDR4_VPP_2V5_EN
+		 * 16 - 17 - not connected
+		 */
+	};
+
+	i2cswitch@75 { /* u60 */
+		compatible = "nxp,pca9544";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+		i2c@0 { /* i2c mw 75 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* PS_PMBUS */
+			ina226@40 { /* u76 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <5000>;
+			};
+			ina226@41 { /* u77 */
+				compatible = "ti,ina226";
+				reg = <0x41>;
+				shunt-resistor = <5000>;
+			};
+			ina226@42 { /* u78 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			ina226@43 { /* u87 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			ina226@44 { /* u85 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <5000>;
+			};
+			ina226@45 { /* u86 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			ina226@46 { /* u93 */
+				compatible = "ti,ina226";
+				reg = <0x46>;
+				shunt-resistor = <5000>;
+			};
+			ina226@47 { /* u88 */
+				compatible = "ti,ina226";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+			ina226@4a { /* u15 */
+				compatible = "ti,ina226";
+				reg = <0x4a>;
+				shunt-resistor = <5000>;
+			};
+			ina226@4b { /* u92 */
+				compatible = "ti,ina226";
+				reg = <0x4b>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@1 { /* i2c mw 75 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* PL_PMBUS */
+			ina226@40 { /* u79 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <2000>;
+			};
+			ina226@41 { /* u81 */
+				compatible = "ti,ina226";
+				reg = <0x41>;
+				shunt-resistor = <5000>;
+			};
+			ina226@42 { /* u80 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			ina226@43 { /* u84 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			ina226@44 { /* u16 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <5000>;
+			};
+			ina226@45 { /* u65 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			ina226@46 { /* u74 */
+				compatible = "ti,ina226";
+				reg = <0x46>;
+				shunt-resistor = <5000>;
+			};
+			ina226@47 { /* u75 */
+				compatible = "ti,ina226";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@2 { /* i2c mw 75 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* MAXIM_PMBUS - 00 */
+			max15301@a { /* u46 */
+				compatible = "max15301";
+				reg = <0xa>;
+			};
+			max15303@b { /* u4 */
+				compatible = "max15303";
+				reg = <0xb>;
+			};
+			max15303@10 { /* u13 */
+				compatible = "max15303";
+				reg = <0x10>;
+			};
+			max15301@13 { /* u47 */
+				compatible = "max15301";
+				reg = <0x13>;
+			};
+			max15303@14 { /* u7 */
+				compatible = "max15303";
+				reg = <0x14>;
+			};
+			max15303@15 { /* u6 */
+				compatible = "max15303";
+				reg = <0x15>;
+			};
+			max15303@16 { /* u10 */
+				compatible = "max15303";
+				reg = <0x16>;
+			};
+			max15303@17 { /* u9 */
+				compatible = "max15303";
+				reg = <0x17>;
+			};
+			max15301@18 { /* u63 */
+				compatible = "max15301";
+				reg = <0x18>;
+			};
+			max15303@1a { /* u49 */
+				compatible = "max15303";
+				reg = <0x1a>;
+			};
+			max15303@1d { /* u18 */
+				compatible = "max15303";
+				reg = <0x1d>;
+			};
+			max15303@20 { /* u8 */
+				compatible = "max15303";
+				status = "disabled"; /* unreachable */
+				reg = <0x20>;
+			};
+
+/*			drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
+drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
+*/
+			max20751@72 { /* u95 FIXME - not detected */
+				compatible = "max20751";
+				reg = <0x72>;
+			};
+			max20751@73 { /* u96 FIXME - not detected */
+				compatible = "max20751";
+				reg = <0x73>;
+			};
+		};
+		/* Bus 3 is not connected */
+	};
+
+	/* FIXME PL connection - u55 , PMOD - j160 */
+	/* FIXME MSP430F - u41 - not detected */
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+	/* FIXME PL i2c via PCA9306 - u45 */
+	/* FIXME MSP430 - u41 - not detected */
+	i2cswitch@74 { /* u34 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		i2c@0 { /* i2c mw 74 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/*
+			 * IIC_EEPROM 1kB memory which uses 256B blocks
+			 * where every block has different address.
+			 *    0 - 256B address 0x54
+			 * 256B - 512B address 0x55
+			 * 512B - 768B address 0x56
+			 * 768B - 1024B address 0x57
+			 */
+			eeprom@54 { /* u23 */
+				compatible = "at,24c08";
+				reg = <0x54>;
+			};
+		};
+		i2c@1 { /* i2c mw 74 0 2 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			si5341: clock-generator1@36 { /* SI5341 - u69 */
+				compatible = "si5341";
+				reg = <0x36>;
+			};
+
+		};
+		i2c@2 { /* i2c mw 74 0 4 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <300000000>;
+				clock-frequency = <300000000>;
+			};
+		};
+		i2c@3 { /* i2c mw 74 0 8 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>; /* copy from zc702 */
+				factory-fout = <156250000>;
+				clock-frequency = <148500000>;
+			};
+		};
+		i2c@4 { /* i2c mw 74 0 10 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			si5328: clock-generator4@69 {/* SI5328 - u20 */
+				compatible = "silabs,si5328";
+				reg = <0x69>;
+			};
+		};
+		/* 5 - 7 unconnected */
+	};
+
+	i2cswitch@75 {
+		compatible = "nxp,pca9548"; /* u135 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* HPC0_IIC */
+		};
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* HPC1_IIC */
+		};
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* SYSMON */
+		};
+		i2c@3 { /* i2c mw 75 0 8 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			/* DDR4 SODIMM */
+			dev@19 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x19>;
+			};
+			dev@30 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x30>;
+			};
+			dev@35 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x35>;
+			};
+			dev@36 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x36>;
+			};
+			dev@51 { /* u-boot detection - maybe SPD */
+				compatible = "xxx";
+				reg = <0x51>;
+			};
+		};
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* SEP 3 */
+		};
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			/* SEP 2 */
+		};
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			/* SEP 1 */
+		};
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+			/* SEP 0 */
+		};
+	};
+};
+
+&pcie {
+/*	status = "okay"; */
+};
+
+&qspi {
+	status = "okay";
+	is-dual = <1>;
+	flash@0 {
+		compatible = "m25p80"; /* 32MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+		spi-max-frequency = <108000000>; /* Based on DC1 spec */
+		partition@qspi-fsbl-uboot { /* for testing purpose */
+			label = "qspi-fsbl-uboot";
+			reg = <0x0 0x100000>;
+		};
+		partition@qspi-linux { /* for testing purpose */
+			label = "qspi-linux";
+			reg = <0x100000 0x500000>;
+		};
+		partition@qspi-device-tree { /* for testing purpose */
+			label = "qspi-device-tree";
+			reg = <0x600000 0x20000>;
+		};
+		partition@qspi-rootfs { /* for testing purpose */
+			label = "qspi-rootfs";
+			reg = <0x620000 0x5E0000>;
+		};
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+	/* SATA OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+	status = "okay";
+	no-1-8-v;	/* for 1.0 silicon */
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&xilinx_drm {
+	status = "okay";
+	clocks = <&si570_1>;
+};
+
+&xlnx_dp {
+	status = "okay";
+};
+
+&xlnx_dp_sub {
+	status = "okay";
+	xlnx,vid-clk-pl;
+};
+
+&xlnx_dp_snd_pcm0 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_pcm1 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_card {
+	status = "okay";
+};
+
+&xlnx_dp_snd_codec0 {
+	status = "okay";
+};
+
+&xlnx_dpdma {
+	status = "okay";
+};

arch/arm/dts/zynqmp.dtsi

@@ -10,7 +10,7 @@
 / {
 	compatible = "xlnx,zynqmp";
 	#address-cells = <2>;
-	#size-cells = <1>;
+	#size-cells = <2>;
 
 	cpus {
 		#address-cells = <1>;
@@ -45,8 +45,179 @@
 		};
 	};
 
+	power-domains {
+		compatible = "xlnx,zynqmp-genpd";
+
+		pd_usb0: pd-usb0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x16>;
+		};
+
+		pd_usb1: pd-usb1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x17>;
+		};
+
+		pd_sata: pd-sata {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1c>;
+		};
+
+		pd_spi0: pd-spi0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x23>;
+		};
+
+		pd_spi1: pd-spi1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x24>;
+		};
+
+		pd_uart0: pd-uart0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x21>;
+		};
+
+		pd_uart1: pd-uart1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x22>;
+		};
+
+		pd_eth0: pd-eth0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1d>;
+		};
+
+		pd_eth1: pd-eth1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1e>;
+		};
+
+		pd_eth2: pd-eth2 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1f>;
+		};
+
+		pd_eth3: pd-eth3 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x20>;
+		};
+
+		pd_i2c0: pd-i2c0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x25>;
+		};
+
+		pd_i2c1: pd-i2c1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x26>;
+		};
+
+		pd_dp: pd-dp {
+			/* fixme: what to attach to */
+			#power-domain-cells = <0x0>;
+			pd-id = <0x29>;
+		};
+
+		pd_gdma: pd-gdma {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2a>;
+		};
+
+		pd_adma: pd-adma {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2b>;
+		};
+
+		pd_ttc0: pd-ttc0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x18>;
+		};
+
+		pd_ttc1: pd-ttc1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x19>;
+		};
+
+		pd_ttc2: pd-ttc2 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1a>;
+		};
+
+		pd_ttc3: pd-ttc3 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1b>;
+		};
+
+		pd_sd0: pd-sd0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x27>;
+		};
+
+		pd_sd1: pd-sd1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x28>;
+		};
+
+		pd_nand: pd-nand {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2c>;
+		};
+
+		pd_qspi: pd-qspi {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2d>;
+		};
+
+		pd_gpio: pd-gpio {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2e>;
+		};
+
+		pd_can0: pd-can0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2f>;
+		};
+
+		pd_can1: pd-can1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x30>;
+		};
+
+		pd_ddr: pd-ddr {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x37>;
+		};
+
+		pd_apll: pd-apll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x32>;
+		};
+
+		pd_vpll: pd-vpll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x33>;
+		};
+
+		pd_dpll: pd-dpll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x34>;
+		};
+
+		pd_rpll: pd-rpll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x35>;
+		};
+
+		pd_iopll: pd-iopll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x36>;
+		};
+	};
+
 	pmu {
 		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <&gic>;
 		interrupts = <0 143 4>,
 			     <0 144 4>,
 			     <0 145 4>,
@@ -76,7 +247,7 @@
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		ranges;
+		ranges = <0 0 0 0 0xffffffff>;
 
 		gic: interrupt-controller@f9010000 {
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
@@ -95,7 +266,7 @@
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		ranges;
+		ranges = <0 0 0 0 0xffffffff>;
 
 		can0: can@ff060000 {
 			compatible = "xlnx,zynq-can-1.0";
@@ -106,6 +277,7 @@
 			interrupt-parent = <&gic>;
 			tx-fifo-depth = <0x40>;
 			rx-fifo-depth = <0x40>;
+			power-domains = <&pd_can0>;
 		};
 
 		can1: can@ff070000 {
@@ -117,6 +289,26 @@
 			interrupt-parent = <&gic>;
 			tx-fifo-depth = <0x40>;
 			rx-fifo-depth = <0x40>;
+			power-domains = <&pd_can1>;
+		};
+
+		cci: cci@fd6e0000 {
+			compatible = "arm,cci-400";
+			reg = <0x0 0xfd6e0000 0x9000>;
+			ranges = <0x0 0x0 0xfd6e0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 123 4>,
+					     <0 123 4>,
+					     <0 123 4>,
+					     <0 123 4>,
+					     <0 123 4>;
+			};
 		};
 
 		/* GDMA */
@@ -126,8 +318,10 @@
 			reg = <0x0 0xfd500000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 124 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <0>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan2: dma@fd510000 {
@@ -136,8 +330,10 @@
 			reg = <0x0 0xfd510000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 125 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <1>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan3: dma@fd520000 {
@@ -146,8 +342,10 @@
 			reg = <0x0 0xfd520000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 126 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <2>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan4: dma@fd530000 {
@@ -156,8 +354,10 @@
 			reg = <0x0 0xfd530000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 127 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <3>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan5: dma@fd540000 {
@@ -166,8 +366,10 @@
 			reg = <0x0 0xfd540000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 128 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <4>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan6: dma@fd550000 {
@@ -176,8 +378,10 @@
 			reg = <0x0 0xfd550000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 129 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <5>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan7: dma@fd560000 {
@@ -186,8 +390,10 @@
 			reg = <0x0 0xfd560000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 130 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <6>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan8: dma@fd570000 {
@@ -196,8 +402,10 @@
 			reg = <0x0 0xfd570000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 131 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <7>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		gpu: gpu@fd4b0000 {
@@ -218,6 +426,7 @@
 			interrupts = <0 77 4>;
 			xlnx,id = <0>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan2: dma@ffa90000 {
@@ -228,6 +437,7 @@
 			interrupts = <0 78 4>;
 			xlnx,id = <1>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan3: dma@ffaa0000 {
@@ -238,6 +448,7 @@
 			interrupts = <0 79 4>;
 			xlnx,id = <2>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan4: dma@ffab0000 {
@@ -248,6 +459,7 @@
 			interrupts = <0 80 4>;
 			xlnx,id = <3>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan5: dma@ffac0000 {
@@ -258,6 +470,7 @@
 			interrupts = <0 81 4>;
 			xlnx,id = <4>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan6: dma@ffad0000 {
@@ -268,6 +481,7 @@
 			interrupts = <0 82 4>;
 			xlnx,id = <5>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan7: dma@ffae0000 {
@@ -278,6 +492,7 @@
 			interrupts = <0 83 4>;
 			xlnx,id = <6>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan8: dma@ffaf0000 {
@@ -288,6 +503,14 @@
 			interrupts = <0 84 4>;
 			xlnx,id = <7>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
+		};
+
+		mc: memory-controller@fd070000 {
+			compatible = "xlnx,zynqmp-ddrc-2.40a";
+			reg = <0x0 0xfd070000 0x30000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 112 4>;
 		};
 
 		nand0: nand@ff100000 {
@@ -299,10 +522,11 @@
 			interrupts = <0 14 4>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			power-domains = <&pd_nand>;
 		};
 
 		gem0: ethernet@ff0b0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 57 4>, <0 57 4>;
@@ -310,12 +534,12 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
+			#stream-id-cells = <1>;
+			power-domains = <&pd_eth0>;
 		};
 
 		gem1: ethernet@ff0c0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 59 4>, <0 59 4>;
@@ -323,12 +547,12 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
+			#stream-id-cells = <1>;
+			power-domains = <&pd_eth1>;
 		};
 
 		gem2: ethernet@ff0d0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 61 4>, <0 61 4>;
@@ -336,12 +560,12 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
+			#stream-id-cells = <1>;
+			power-domains = <&pd_eth2>;
 		};
 
 		gem3: ethernet@ff0e0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 63 4>, <0 63 4>;
@@ -349,17 +573,20 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
+			#stream-id-cells = <1>;
+			power-domains = <&pd_eth3>;
 		};
 
 		gpio: gpio@ff0a0000 {
 			compatible = "xlnx,zynqmp-gpio-1.0";
 			status = "disabled";
 			#gpio-cells = <0x2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <0 16 4>;
 			reg = <0x0 0xff0a0000 0x1000>;
+			power-domains = <&pd_gpio>;
 		};
 
 		i2c0: i2c@ff020000 {
@@ -370,6 +597,7 @@
 			reg = <0x0 0xff020000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_i2c0>;
 		};
 
 		i2c1: i2c@ff030000 {
@@ -380,6 +608,7 @@
 			reg = <0x0 0xff030000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_i2c1>;
 		};
 
 		pcie: pcie@fd0e0000 {
@@ -390,16 +619,26 @@
 			#interrupt-cells = <1>;
 			device_type = "pci";
 			interrupt-parent = <&gic>;
-			interrupts = < 0 118 4>,
-				     < 0 116 4>,
-				     < 0 115 4>,	/* MSI_1 [63...32] */
-				     < 0 114 4 >;	/* MSI_0 [31...0] */
+			interrupts = <0 118 4>,
+				     <0 116 4>,
+				     <0 115 4>,	/* MSI_1 [63...32] */
+				     <0 114 4>;	/* MSI_0 [31...0] */
 			interrupt-names = "misc", "intx", "msi_1", "msi_0";
 			reg = <0x0 0xfd0e0000 0x1000>,
 			      <0x0 0xfd480000 0x1000>,
 			      <0x0 0xe0000000 0x1000000>;
 			reg-names = "breg", "pcireg", "cfg";
 			ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+			pcie_intc: legacy-interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
 		};
 
 		qspi: spi@ff0f0000 {
@@ -409,9 +648,11 @@
 			interrupts = <0 15 4>;
 			interrupt-parent = <&gic>;
 			num-cs = <1>;
-			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+			reg = <0x0 0xff0f0000 0x1000>,
+			      <0x0 0xc0000000 0x8000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_qspi>;
 		};
 
 		rtc: rtc@ffa60000 {
@@ -429,6 +670,7 @@
 			reg = <0x0 0xfd0c0000 0x2000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
+			power-domains = <&pd_sata>;
 		};
 
 		sdhci0: sdhci@ff160000 {
@@ -438,6 +680,8 @@
 			interrupts = <0 48 4>;
 			reg = <0x0 0xff160000 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
+			broken-tuning;
+			power-domains = <&pd_sd0>;
 		};
 
 		sdhci1: sdhci@ff170000 {
@@ -447,6 +691,8 @@
 			interrupts = <0 49 4>;
 			reg = <0x0 0xff170000 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
+			broken-tuning;
+			power-domains = <&pd_sd1>;
 		};
 
 		smmu: smmu@fd800000 {
@@ -454,11 +700,15 @@
 			reg = <0x0 0xfd800000 0x20000>;
 			#global-interrupts = <1>;
 			interrupt-parent = <&gic>;
-			interrupts = <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
+			interrupts = <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
+			mmu-masters = < &gem0 0x874
+					&gem1 0x875
+					&gem2 0x876
+					&gem3 0x877 >;
 		};
 
 		spi0: spi@ff040000 {
@@ -470,6 +720,7 @@
 			clock-names = "ref_clk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_spi0>;
 		};
 
 		spi1: spi@ff050000 {
@@ -481,6 +732,7 @@
 			clock-names = "ref_clk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_spi1>;
 		};
 
 		ttc0: timer@ff110000 {
@@ -490,6 +742,7 @@
 			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 			reg = <0x0 0xff110000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc0>;
 		};
 
 		ttc1: timer@ff120000 {
@@ -499,6 +752,7 @@
 			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 			reg = <0x0 0xff120000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc1>;
 		};
 
 		ttc2: timer@ff130000 {
@@ -508,6 +762,7 @@
 			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 			reg = <0x0 0xff130000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc2>;
 		};
 
 		ttc3: timer@ff140000 {
@@ -517,42 +772,69 @@
 			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 			reg = <0x0 0xff140000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc3>;
 		};
 
 		uart0: serial@ff000000 {
-			compatible = "cdns,uart-r1p12";
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 21 4>;
 			reg = <0x0 0xff000000 0x1000>;
 			clock-names = "uart_clk", "pclk";
+			power-domains = <&pd_uart0>;
 		};
 
 		uart1: serial@ff010000 {
-			compatible = "cdns,uart-r1p12";
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 22 4>;
 			reg = <0x0 0xff010000 0x1000>;
 			clock-names = "uart_clk", "pclk";
+			power-domains = <&pd_uart1>;
 		};
 
 		usb0: usb@fe200000 {
-			compatible = "snps,dwc3";
+			#address-cells = <2>;
+			#size-cells = <1>;
 			status = "disabled";
-			interrupt-parent = <&gic>;
-			interrupts = <0 65 4>;
-			reg = <0x0 0xfe200000 0x40000>;
-			clock-names = "clk_xin", "clk_ahb";
+			compatible = "xlnx,zynqmp-dwc3";
+			clock-names = "bus_clk", "ref_clk";
+			clocks = <&clk125>, <&clk125>;
+			power-domains = <&pd_usb0>;
+			ranges;
+
+			dwc3_0: dwc3@fe200000 {
+				compatible = "snps,dwc3";
+				status = "disabled";
+				reg = <0x0 0xfe200000 0x40000>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 65 4>;
+				/* snps,quirk-frame-length-adjustment = <0x20>; */
+				snps,refclk_fladj;
+			};
 		};
 
 		usb1: usb@fe300000 {
-			compatible = "snps,dwc3";
+			#address-cells = <2>;
+			#size-cells = <1>;
 			status = "disabled";
-			interrupt-parent = <&gic>;
-			interrupts = <0 70 4>;
-			reg = <0x0 0xfe300000 0x40000>;
-			clock-names = "clk_xin", "clk_ahb";
+			compatible = "xlnx,zynqmp-dwc3";
+			clock-names = "bus_clk", "ref_clk";
+			clocks = <&clk125>, <&clk125>;
+			power-domains = <&pd_usb1>;
+			ranges;
+
+			dwc3_1: dwc3@fe300000 {
+				compatible = "snps,dwc3";
+				status = "disabled";
+				reg = <0x0 0xfe300000 0x40000>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 70 4>;
+				/* snps,quirk-frame-length-adjustment = <0x20>; */
+				snps,refclk_fladj;
+			};
 		};
 
 		watchdog0: watchdog@fd4d0000 {
@@ -583,10 +865,11 @@
 			};
 		};
 
-		xlnx_dp: dp@43c00000 {
+		xlnx_dp: dp@fd4a0000 {
 			compatible = "xlnx,v-dp";
 			status = "disabled";
-			reg = <0x0 0xfd4a0000 0x1000>;
+			reg = <0x0 0xfd4a0000 0x1000>,
+			      <0x0 0xfd400000 0x20000>;
 			interrupts = <0 119 4>;
 			interrupt-parent = <&gic>;
 			clock-names = "aclk", "aud_clk";
@@ -599,6 +882,7 @@
 			xlnx,bpc = <8>;
 			xlnx,audio-chan = <2>;
 			xlnx,dp-sub = <&xlnx_dp_sub>;
+			xlnx,max-pclock-frequency = <300000>;
 		};
 
 		xlnx_dp_snd_card: dp_snd_card {
@@ -628,12 +912,16 @@
 			dma-names = "tx";
 		};
 
-		xlnx_dp_sub: dp_sub@43c0a000 {
+		xlnx_dp_sub: dp_sub@fd4aa000 {
 			compatible = "xlnx,dp-sub";
 			status = "disabled";
-			reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
+			reg = <0x0 0xfd4aa000 0x1000>,
+			      <0x0 0xfd4ab000 0x1000>,
+			      <0x0 0xfd4ac000 0x1000>;
 			reg-names = "blend", "av_buf", "aud";
 			xlnx,output-fmt = "rgb";
+			xlnx,vid-fmt = "yuyv";
+			xlnx,gfx-fmt = "rgb565";
 		};
 
 		xlnx_dpdma: dma@fd4c0000 {
@@ -645,22 +933,22 @@
 			clock-names = "axi_clk";
 			dma-channels = <6>;
 			#dma-cells = <1>;
-			dma-video0channel@43c10000 {
+			dma-video0channel@fd4c0000 {
 				compatible = "xlnx,video0";
 			};
-			dma-video1channel@43c10000 {
+			dma-video1channel@fd4c0000 {
 				compatible = "xlnx,video1";
 			};
-			dma-video2channel@43c10000 {
+			dma-video2channel@fd4c0000 {
 				compatible = "xlnx,video2";
 			};
-			dma-graphicschannel@43c10000 {
+			dma-graphicschannel@fd4c0000 {
 				compatible = "xlnx,graphics";
 			};
-			dma-audio0channel@43c10000 {
+			dma-audio0channel@fd4c0000 {
 				compatible = "xlnx,audio0";
 			};
-			dma-audio1channel@43c10000 {
+			dma-audio1channel@fd4c0000 {
 				compatible = "xlnx,audio1";
 			};
 		};

arch/arm/imx-common/cpu.c

@@ -137,6 +137,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX7S:
+		return "7SOLO";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
 		return "7D";	/* Dual-core version of the mx7 */
 	case MXC_CPU_MX6QP:

arch/arm/include/asm/arch-am33xx/spl.h

@@ -56,8 +56,9 @@
 #define BOOT_DEVICE_MMC1	0x07
 #define BOOT_DEVICE_MMC2	0x08
 #define BOOT_DEVICE_SPI		0x0A
+#define BOOT_DEVICE_USB		0x0D
 #define BOOT_DEVICE_UART	0x41
-#define BOOT_DEVICE_USB		0x45
+#define BOOT_DEVICE_USBETH	0x45
 #define BOOT_DEVICE_CPGMAC	0x47
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1

arch/arm/include/asm/arch-imx/cpu.h

@@ -21,6 +21,7 @@
 #define MXC_CPU_MX6D		0x67
 #define MXC_CPU_MX6DP		0x68
 #define MXC_CPU_MX6QP		0x69
+#define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
 

arch/arm/include/asm/arch-mx27/imx-regs.h

@@ -106,9 +106,9 @@ struct esdramc_regs {
 
 /* Watchdog Registers*/
 struct wdog_regs {
-	u32 wcr;
-	u32 wsr;
-	u32 wstr;
+	u16 wcr;
+	u16 wsr;
+	u16 wstr;
 };
 
 /* PLL registers */

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -162,6 +162,7 @@
 #endif
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)

arch/arm/mach-mvebu/include/mach/soc.h

@@ -55,6 +55,7 @@
 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
 #define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))

arch/arm/mach-sunxi/usb_phy.c

@@ -85,6 +85,8 @@ static struct sunxi_usb_phy {
 #endif
 };
 
+static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
+
 static int get_vbus_gpio(int index)
 {
 	switch (index) {
@@ -269,6 +271,11 @@ void sunxi_usb_phy_power_on(int index)
 {
 	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
 
+	if (initial_usb_scan_delay) {
+		mdelay(initial_usb_scan_delay);
+		initial_usb_scan_delay = 0;
+	}
+
 	phy->power_on_count++;
 	if (phy->power_on_count != 1)
 		return;

arch/arm/mach-zynq/include/mach/gpio.h

@@ -8,67 +8,4 @@
 #ifndef _ZYNQ_GPIO_H
 #define _ZYNQ_GPIO_H
 
-#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
-
-/* Maximum banks */
-#define ZYNQ_GPIO_MAX_BANK	4
-
-#define ZYNQ_GPIO_BANK0_NGPIO	32
-#define ZYNQ_GPIO_BANK1_NGPIO	22
-#define ZYNQ_GPIO_BANK2_NGPIO	32
-#define ZYNQ_GPIO_BANK3_NGPIO	32
-
-#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
-				 ZYNQ_GPIO_BANK1_NGPIO + \
-				 ZYNQ_GPIO_BANK2_NGPIO + \
-				 ZYNQ_GPIO_BANK3_NGPIO)
-
-#define ZYNQ_GPIO_BANK0_PIN_MIN	0
-#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
-					ZYNQ_GPIO_BANK0_NGPIO - 1)
-#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
-					ZYNQ_GPIO_BANK1_NGPIO - 1)
-#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
-					ZYNQ_GPIO_BANK2_NGPIO - 1)
-#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
-					ZYNQ_GPIO_BANK3_NGPIO - 1)
-
-/* Register offsets for the GPIO device */
-/* LSW Mask & Data -WO */
-#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
-/* MSW Mask & Data -WO */
-#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
-/* Data Register-RW */
-#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
-/* Direction mode reg-RW */
-#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
-/* Output enable reg-RW */
-#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
-/* Interrupt mask reg-RO */
-#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
-/* Interrupt enable reg-WO */
-#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
-/* Interrupt disable reg-WO */
-#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
-/* Interrupt status reg-RO */
-#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
-/* Interrupt type reg-RW */
-#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
-/* Interrupt polarity reg-RW */
-#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
-/* Interrupt on any, reg-RW */
-#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
-
-/* Disable all interrupts mask */
-#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
-
-/* Mid pin number of a bank */
-#define ZYNQ_GPIO_MID_PIN_NUM 16
-
-/* GPIO upper 16 bit mask */
-#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-
 #endif /* _ZYNQ_GPIO_H */

arch/m68k/cpu/mcf523x/start.S

@@ -141,8 +141,12 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 

arch/m68k/cpu/mcf52x2/start.S

@@ -198,8 +198,12 @@ _after_flashbar_copy:
 
 	move.l #__got_start, %a5		/* put relocation table address to a5 */
 
-	bsr cpu_init_f				/* run low-level CPU init code (from flash) */
-	bsr board_init_f			/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 

arch/m68k/cpu/mcf532x/start.S

@@ -155,8 +155,12 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 

arch/m68k/cpu/mcf5445x/start.S

@@ -664,8 +664,12 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 

arch/mips/lib/bootm.c

@@ -9,6 +9,7 @@
 #include <image.h>
 #include <fdt_support.h>
 #include <asm/addrspace.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -252,10 +253,10 @@ static int boot_reloc_fdt(bootm_headers_t *images)
 #endif
 }
 
-int arch_fixup_memory_node(void *blob)
+int arch_fixup_fdt(void *blob)
 {
 #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
-	u64 mem_start = 0;
+	u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
 	u64 mem_size = gd->ram_size;
 
 	return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);

arch/sandbox/Kconfig

@@ -7,6 +7,9 @@ config SYS_ARCH
 config SYS_BOARD
 	default "sandbox"
 
+config SYS_CPU
+	default "sandbox"
+
 config SYS_CONFIG_NAME
 	default "sandbox"
 

arch/sandbox/include/asm/cache.h

@@ -20,5 +20,6 @@
 #else
 #define ARCH_DMA_MINALIGN	16
 #endif
+#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
 
 #endif /* __SANDBOX_CACHE_H__ */

arch/sandbox/include/asm/io.h

@@ -57,5 +57,6 @@ void outw(unsigned int value, unsigned int addr);
 void outb(unsigned int value, unsigned int addr);
 
 #include <iotrace.h>
+#include <asm/types.h>
 
 #endif

board/ccv/xpress/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XPRESS
+
+config SYS_BOARD
+	default "xpress"
+
+config SYS_VENDOR
+	default "ccv"
+
+config SYS_CONFIG_NAME
+	default "xpress"
+
+endif

board/ccv/xpress/MAINTAINERS

@@ -0,0 +1,7 @@
+CCV XPRESS BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/ccv/xpress/
+F:	include/configs/xpress.h
+F:	configs/xpress_defconfig
+F:	configs/xpress_spl_defconfig

board/ccv/xpress/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := xpress.o
+obj-$(CONFIG_SPL_BUILD) += spl.o

board/ccv/xpress/imximage.cfg

@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* ddr io type */
+DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+/* clock */
+DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+/* control and address */
+DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
+				configured using Group Control Register:
+				IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+/* data strobes */
+DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+/* data */
+DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer:  IM
+ * Device Part Number:  IME1G16D3EEBG-15EI
+ * Clock Freq.:   400MHz
+ * Density per CS in Gb: 1
+ * Chip Selects used: 1
+ * Number of Banks: 8
+ * Row address:     13
+ * Column address:  10
+ * Data bus width 16
+ */
+DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
+				during MMDC set up */
+
+/*
+ * Calibration setup
+ */
+DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
+				periodic HW ZQ calibration. */
+
+/*
+ * For target board, may need to run write leveling calibration to fine tune
+ * these settings.
+ */
+DATA 4 0x021b080c 0x00000000
+
+/* Read DQS Gating calibration */
+DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
+
+/* Read calibration */
+DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
+
+/* Write calibration */
+DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
+
+/*
+ * read data bit delay: (3 is the reccommended default value, although out of
+ * reset value is 0)
+ */
+DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
+DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
+DATA 4 0x021b082c 0xF3333333
+DATA 4 0x021b0830 0xF3333333
+
+DATA 4 0x021b08c0 0x00921012
+
+/* Clock Fine Tuning */
+DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
+
+/* Complete calibration by forced measurement: */
+DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
+/*
+ * Calibration setup end
+ */
+
+/* MMDC init: */
+DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
+DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
+DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
+DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
+DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
+
+/*
+ * MDMISC: RALAT kept to the high level of 5.
+ * MDMISC: consider reducing RALAT if your 528MHz board design allow that.
+ * Lower RALAT benefits:
+ * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
+ *    to 3
+ * b. Small performence improvment
+ */
+DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
+
+DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
+				during MMDC set up */
+
+DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
+DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
+DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
+DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
+
+/* Mode register writes */
+DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
+DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
+DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
+DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
+DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
+				device on CS0 */
+
+DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
+DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
+DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
+DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
+				enter automatically to self-refresh while the
+				number of idle cycle reached. */
+DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
+				the configuration bit as initialization is
+				complete) */

board/ccv/xpress/spl.c

@@ -0,0 +1,116 @@
+/*
+ * SPL specific code for CCV xPress
+ *
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/crm_regs.h>
+
+/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x4164015C,
+	.p0_mprddlctl = 0x40404446,
+	.p0_mpwrdlctl = 0x40405A52,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* Setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* Setup iomux and i2c */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}

board/ccv/xpress/xpress.c

@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                  \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
+	PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+static struct i2c_pads_info i2c_pad_info4 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
+		.gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
+		.gp = IMX_GPIO_NR(1, 20),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
+		.gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
+		.gp = IMX_GPIO_NR(1, 21),
+	},
+};
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart8_pads[] = {
+	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+	imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
+}
+
+/* eMMC on USDHC2 */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*
+	 * RST_B
+	 */
+	MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC2_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(1, 9)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eMMC is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OTG1 */
+	MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* ENET1 reset */
+	MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* ENET1 interrupt */
+	MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	/* Reset LAN8742 PHY */
+	ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
+	if (!ret)
+		gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+	mdelay(10);
+	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+	mdelay(10);
+
+	return cpu_eth_init(bis);
+}
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+
+	setup_fec(CONFIG_FEC_ENET_DEV);
+
+	setup_usb();
+
+	return 0;
+}
+
+static const struct boot_mode board_boot_modes[] = {
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
+	{ NULL, 0 },
+};
+
+int board_late_init(void)
+{
+	add_board_boot_modes(board_boot_modes);
+	setenv("board_name", "xpress");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: CCV-EVA xPress\n");
+
+	return 0;
+}

board/dave/common/flash.c

@@ -1,691 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-	short n;
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
-		/* set sector offsets for bottom boot block type	*/
-		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
-			info->start[i] = base;
-			base += 8 << 10;
-		}
-		while (i < info->sector_count) {	/* 64k regular sectors	*/
-			info->start[i] = base;
-			base += 64 << 10;
-			++i;
-		}
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("ST  ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
-				break;
-	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
-				break;
-	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
-				break;
-	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_STMW320DT:	printf ("M29W320DT (32 M, top sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count-1))
-		  size = info->start[i+1] - info->start[i];
-		else
-		  size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++)
-		  {
-		    if (*flash++ != 0xffffffff)
-		      {
-			erased = 0;
-			break;
-		      }
-		  }
-
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		/* print empty and read-only info */
-		printf (" %08lX%s%s",
-			info->start[i],
-			erased ? " E" : "  ",
-			info->protect[i] ? "RO " : "   ");
-#else
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-#endif
-
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	short n;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
-
-	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
-
-	value = addr2[CONFIG_SYS_FLASH_READ0];
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
-		info->flash_id += FLASH_STMW320DT;
-		info->sector_count = 67;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
-		info->flash_id += FLASH_AMDL322T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
-		info->flash_id += FLASH_AMDL322B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
-		info->flash_id += FLASH_AMDL323T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
-		info->flash_id += FLASH_AMDL323B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
-		info->flash_id += FLASH_AM640U;
-		info->sector_count = 128;
-		info->size = 0x00800000;  break;	/* => 8 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 16;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
-		info->flash_id += FLASH_SST160A;
-		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
-		/* set sector offsets for bottom boot block type	*/
-		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
-			info->start[i] = base;
-			base += 8 << 10;
-		}
-		while (i < info->sector_count) {	/* 64k regular sectors	*/
-			info->start[i] = base;
-			base += 64 << 10;
-			++i;
-		}
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		/*  1 x 16k boot sector */
-		base -= 16 << 10;
-		--i;
-		info->start[i] = base;
-		/*  2 x 8k  boot sectors */
-		for (n=0; n<2; ++n) {
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		/*  1 x 32k boot sector */
-		base -= 32 << 10;
-		--i;
-		info->start[i] = base;
-
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-		  info->protect[i] = 0;
-		else
-		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
-		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
-			for (i=0; i<50; i++)
-			  udelay(1000);  /* wait 1 ms */
-		    } else {
-			if (sect == s_first) {
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			}
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-		    }
-		    l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-#ifdef CONFIG_B2
-			data = data | ((*(uchar *)cp)<<(8*i));
-#else
-			data = (data << 8) | (*(uchar *)cp);
-#endif
-		}
-		for (; i<4 && cnt>0; ++i) {
-#ifdef CONFIG_B2
-			data = data  | ((*src++)<<(8*i));
-#else
-			data = (data << 8) | *src++;
-#endif
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-#ifdef CONFIG_B2
-			data = data | ((*(uchar *)cp)<<(8*i));
-#else
-			data = (data << 8) | (*(uchar *)cp);
-#endif
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-#ifdef CONFIG_B2
-		data = (*(ulong*)src);
-		src += 4;
-#else
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-#endif
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-#ifdef CONFIG_B2
-		data = data  | ((*src++)<<(8*i));
-#else
-		data = (data << 8) | *src++;
-#endif
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-#ifdef CONFIG_B2
-		data = data | ((*(uchar *)cp)<<(8*i));
-#else
-		data = (data << 8) | (*(uchar *)cp);
-#endif
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	ulong *data_ptr = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
-	ulong start;
-	int flag;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile ulong *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
-	  {
-	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
-
-	    dest2[i] = data2[i];
-
-	    /* re-enable interrupts if necessary */
-	    if (flag)
-	      enable_interrupts();
-
-	    /* data polling for D7 */
-	    start = get_timer (0);
-	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
-		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-		return (1);
-	      }
-	    }
-	  }
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */

board/freescale/mx6qarm2/imximage_mx6dl.cfg

@@ -234,7 +234,7 @@ DATA 4 0x021b0018 0x0000174C
 /* MMDC0_MDRWD;*/
 DATA 4 0x021b002c 0x0f9f26d2
 /* MMDC0_MDOR */
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 /* MMDC0_MDCFG3LP */
 DATA 4 0x021b0038 0x00190778
 /* MMDC0_MDOTC */
@@ -263,7 +263,7 @@ DATA 4 0x021b4018 0x0000174C
 /* MMDC1_MDRWD;*/
 DATA 4 0x021b402c 0x0f9f26d2
 /* MMDC1_MDOR */
-DATA 4 0x021b4030 0x0000020e
+DATA 4 0x021b4030 0x009f0e10
 /* MMDC1_MDCFG3LP */
 DATA 4 0x021b4038 0x00190778
 /* MMDC1_MDOTC */

board/freescale/mx6sabresd/mx6sabresd.c

@@ -365,34 +365,24 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 	imx_enable_hdmi_phy();
 }
 
-static void enable_lvds(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)
-				IOMUXC_BASE_ADDR;
-	u32 reg = readl(&iomux->gpr[2]);
-	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
-	writel(reg, &iomux->gpr[2]);
-}
-
 struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB666,
 	.detect	= NULL,
-	.enable	= enable_lvds,
+	.enable	= NULL,
 	.mode	= {
 		.name           = "Hannstar-XGA",
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
@@ -406,13 +396,13 @@ struct display_info_t const displays[] = {{
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {

board/freescale/mx6slevk/imximage.cfg

@@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b085c 0x1b4700c7
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
@@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82
 DATA 4 0x021b0014 0x00000093
 DATA 4 0x021b0018 0x00001688
 DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f

board/ge/bx50v3/Kconfig

@@ -0,0 +1,18 @@
+if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+
+config IMX_CONFIG
+	default "board/ge/bx50v3/bx50v3.cfg"
+
+config SYS_BOARD
+	default "bx50v3"
+
+config SYS_VENDOR
+	default "ge"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "ge_bx50v3"
+
+endif

board/ge/bx50v3/MAINTAINERS

@@ -0,0 +1,8 @@
+GE_BX50V3 BOARD
+M:	Martin Donnelly <martin.donnelly@ge.com>
+S:	Maintained
+F:	board/ge/bx50v3/
+F:	include/configs/ge_bx50v3.h
+F:	configs/ge_b450v3_defconfig
+F:	configs/ge_b650v3_defconfig
+F:	configs/ge_b850v3_defconfig

board/ge/bx50v3/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright 2015 Timesys Corporation
+# Copyright 2015 General Electric Company
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := bx50v3.o

board/ge/bx50v3/bx50v3.c

@@ -0,0 +1,533 @@
+/*
+ * Copyright 2015 Timesys Corporation
+ * Copyright 2015 General Electric Company
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	/* AR8033 PHY Reset */
+	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset AR8033 PHY */
+	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
+		.gp = IMX_GPIO_NR(5, 26)
+	}
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info i2c_pad_info3 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+static iomux_v3_cfg_t const pcie_pads[] = {
+	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
+#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = 1; /* eMMC is always present */
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = !gpio_get_value(USDHC4_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_direction_input(USDHC2_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 2:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			gpio_direction_input(USDHC4_CD_GPIO);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers\n"
+			       "(%d) then supported by the board (%d)\n",
+			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
+	/* set device address 0x7 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	/* offset 0x8016: CLK_25M Clock Select */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	/* enable register write, no post increment, address 0x7 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+	/* set to 125 MHz from local PLL source */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
+
+	/* rgmii tx clock delay enable */
+	/* set debug port address: SerDes Test and System Mode Control */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	/* enable rgmii tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Power for LVDS Display */
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
+	/* Backlight enable for LVDS display */
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+int board_cfb_skip(void)
+{
+	gpio_direction_output(LVDS_POWER_GP, 1);
+
+	return 0;
+}
+
+static int detect_baseboard(struct display_info_t const *dev)
+{
+	if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
+	    IS_ENABLED(CONFIG_TARGET_GE_B650V3))
+		return 1;
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= -1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_baseboard,
+	.enable	= NULL,
+	.mode	= {
+		.name           = "G121X1-L03",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 20,
+		.right_margin   = 300,
+		.upper_margin   = 30,
+		.lower_margin   = 8,
+		.hsync_len      = 1,
+		.vsync_len      = 1,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 3,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+	     | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		       IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+		       IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlights off until needed */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	gpio_direction_input(LVDS_POWER_GP);
+	gpio_direction_input(LVDS_BACKLIGHT_GP);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+	setup_pcie();
+
+	return cpu_eth_init(bis);
+}
+
+static iomux_v3_cfg_t const misc_pads[] = {
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
+#define WIFI_EN	IMX_GPIO_NR(6, 14)
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(misc_pads,
+					 ARRAY_SIZE(misc_pads));
+
+	setup_iomux_uart();
+
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gpio_direction_output(SUS_S3_OUT, 1);
+	gpio_direction_output(WIFI_EN, 1);
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	/* We need at least 200ms between power on and backlight on
+	 * as per specifications from CHI MEI */
+	mdelay(250);
+
+	/* Backlight Power */
+	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}

board/ge/bx50v3/bx50v3.cfg

@@ -0,0 +1,151 @@
+/*
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* DDR IO */
+DATA 4, MX6_IOM_GRP_DDR_TYPE,	0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE,	0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1,	0x00000030
+DATA 4, MX6_IOM_DRAM_CAS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RAS,	0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RESET,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2,	0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1,	0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS,	0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL,	0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7,	0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE,	0x00020000
+DATA 4, MX6_IOM_GRP_B0DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B1DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B2DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B3DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B4DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B5DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B6DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B7DS,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7,	0x00000030
+
+/* Calibrations */
+/* ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/* Read DQS Gating calibration */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0,	0x45380544
+DATA 4, MX6_MMDC_P0_MPDGCTRL1,	0x05280530
+DATA 4, MX6_MMDC_P1_MPDGCTRL0,	0x4530053C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1,	0x0530050C
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL,	0x36303032
+DATA 4, MX6_MMDC_P1_MPRDDLCTL,	0x38363042
+/* Write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL,	0x3A3A423E
+DATA 4, MX6_MMDC_P1_MPWRDLCTL,	0x4A38483E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800
+
+/* MMDC init */
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC,	0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0,	0x8A8F79A4
+DATA 4, MX6_MMDC_P0_MDCFG1,	0xDB538E64
+DATA 4, MX6_MMDC_P0_MDCFG2,	0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC,	0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD,	0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR,	0x008F1023
+DATA 4, MX6_MMDC_P0_MDASP,	0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL,	0x841a0000
+
+/* Initialize Micron MT41J128M */
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR,	0x0408803a
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR,	0x0000803b
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00408031
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00408039
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04008048
+DATA 4, MX6_MMDC_P0_MDREF,	0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL,	0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL,	0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR,	0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  1	   --> CKO1 enabled
+ * cko1_div 111  --> divide by 8
+ * cko1_sel 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb

board/sandbox/README.sandbox

@@ -349,7 +349,8 @@ directory. These include:
      - Unit tests for U-Boot's compression algorithms, useful for
        security checking. It supports gzip, bzip2, lzma and lzo.
   driver model
-     - test/dm/test-dm.sh to run these.
+     - Run this pytest
+	  ./test/py/test.py --bd sandbox --build -k ut_dm -v
   image
      - Unit tests for images:
           test/image/test-imagetools.sh - multi-file images

board/sunxi/Kconfig

@@ -312,6 +312,15 @@ config MMC_SUNXI_SLOT_EXTRA
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
 
+config INITIAL_USB_SCAN_DELAY
+	int "delay initial usb scan by x ms to allow builtin devices to init"
+	default 0
+	---help---
+	Some boards have on board usb devices which need longer than the
+	USB spec's 1 second to connect from board powerup. Set this config
+	option to a non 0 value to add an extra delay before the first usb
+	bus scan.
+
 config USB0_VBUS_PIN
 	string "Vbus enable pin for usb0 (otg)"
 	default ""

board/sunxi/MAINTAINERS

@@ -55,6 +55,7 @@ F:	include/configs/sun8i.h
 F:	configs/ga10h_v1_1_defconfig
 F:	configs/gt90h_v4_defconfig
 F:	configs/orangepi_2_defconfig
+F:	configs/orangepi_one_defconfig
 F:	configs/orangepi_pc_defconfig
 F:	configs/orangepi_plus_defconfig
 F:	configs/polaroid_mid2809pxe04_defconfig

board/theadorable/theadorable.c

@@ -5,9 +5,13 @@
  */
 
 #include <common.h>
+#include <i2c.h>
+#include <pci.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <linux/crc8.h>
 #include <linux/mbus.h>
 #ifdef CONFIG_NET
 #include <netdev.h>
@@ -19,6 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
+#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
+	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
+
 #define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
 #define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
 #define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))
@@ -27,6 +35,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
 #define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000
 
+#define GPIO_USB0_PWR_ON		18
+#define GPIO_USB1_PWR_ON		19
+
+#define PEX_SWITCH_NOT_FOUNT_LIMIT	3
+
+#define STM_I2C_BUS	1
+#define STM_I2C_ADDR	0x27
+#define REBOOT_DELAY	1000		/* reboot-delay in ms */
+
 /* DDR3 static configuration */
 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
 	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
@@ -135,6 +152,8 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	int ret;
+
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
@@ -147,13 +166,33 @@ int board_init(void)
 	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
 			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
 
+	/*
+	 * Set RX Channel Control 0 Register:
+	 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
+	 * to 3 (1/1) results in a more stable USB connection.
+	 */
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
+
+	/* Toggle USB power */
+	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
+	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
+	mdelay(1);
+	gpio_set_value(GPIO_USB0_PWR_ON, 1);
+	gpio_set_value(GPIO_USB1_PWR_ON, 1);
+
 	return 0;
 }
 
 int checkboard(void)
 {
-	puts("Board: theadorable\n");
-
 	board_fpga_add();
 
 	return 0;
@@ -182,3 +221,63 @@ int board_video_init(void)
 
 	return mvebu_lcd_register_init(&lcd_info);
 }
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	pci_dev_t bdf;
+	ulong bootcount;
+
+	/*
+	 * Check if the PEX switch is detected (somtimes its not available
+	 * on the PCIe bus). In this case, try to recover by issuing a
+	 * soft-reset or even a power-cycle, depending on the bootcounter
+	 * value.
+	 */
+	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
+	if (bdf == -1) {
+		u8 i2c_buf[8];
+		int ret;
+
+		/* PEX switch not found! */
+		bootcount = bootcount_load();
+		printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
+		       bootcount);
+		if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
+			printf("Issuing power-switch via uC!\n");
+
+			printf("Issuing power-switch via uC!\n");
+			i2c_set_bus_num(STM_I2C_BUS);
+			i2c_buf[0] = STM_I2C_ADDR << 1;
+			i2c_buf[1] = 0xc5;	/* cmd */
+			i2c_buf[2] = 0x01;	/* enable */
+			/* Delay before reboot */
+			i2c_buf[3] = REBOOT_DELAY & 0x00ff;
+			i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
+			/* Delay before shutdown */
+			i2c_buf[5] = 0x00;
+			i2c_buf[6] = 0x00;
+			i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
+
+			ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
+			if (ret) {
+				printf("I2C write error (ret=%d)\n", ret);
+				printf("Issuing soft-reset...\n");
+				/* default handling: SOFT reset */
+				do_reset(NULL, 0, 0, NULL);
+			}
+
+			/* Wait for power-cycle to occur... */
+			printf("Waiting for power-cycle via uC...\n");
+			while (1)
+				;
+		} else {
+			printf("Issuing soft-reset...\n");
+			/* default handling: SOFT reset */
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+
+	return 0;
+}
+#endif

board/ti/am57xx/Kconfig

@@ -9,6 +9,15 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "am57xx_evm"
 
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 3
+        help
+          The AM57x (and DRA7xx) SoC has a total of 6 UARTs available to it.
+          Depending on your specific board you may want something other than UART3
+          here.
+
 source "board/ti/common/Kconfig"
 
 endif

board/ti/am57xx/board.c

@@ -35,6 +35,7 @@
 
 #define board_is_x15()		board_ti_is("BBRDX15_")
 #define board_is_am572x_evm()	board_ti_is("AM572PM_")
+#define board_is_am572x_idk()	board_ti_is("AM572IDK")
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
@@ -131,9 +132,9 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36ab,
+	.sdram_tim1		= 0xcccf36b3,
 	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x409f88a8,
+	.sdram_tim3		= 0x407f88a8,
 	.read_idle_ctrl		= 0x00050000,
 	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
@@ -278,6 +279,8 @@ void do_board_detect(void)
 		bname = "BeagleBoard X15";
 	else if (board_is_am572x_evm())
 		bname = "AM572x EVM";
+	else if (board_is_am572x_idk())
+		bname = "AM572x IDK";
 
 	if (bname)
 		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
@@ -296,6 +299,8 @@ static void setup_board_eeprom_env(void)
 
 	if (board_is_am572x_evm())
 		name = "am57xx_evm";
+	else if (board_is_am572x_idk())
+		name = "am572x_idk";
 	else
 		printf("Unidentified board claims %s in eeprom header\n",
 		       board_ti_get_name());
@@ -343,9 +348,24 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_IODELAY_RECALIBRATION
 void recalibrate_iodelay(void)
 {
-	__recalibrate_iodelay(core_padconf_array_essential,
-			      ARRAY_SIZE(core_padconf_array_essential),
-			      iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
+	const struct pad_conf_entry *pconf;
+	const struct iodelay_cfg_entry *iod;
+	int pconf_sz, iod_sz;
+
+	if (board_is_am572x_idk()) {
+		pconf = core_padconf_array_essential_am572x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
+		iod = iodelay_cfg_array_am572x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+	} else {
+		/* Common for X15/GPEVM */
+		pconf = core_padconf_array_essential_x15;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
+		iod = iodelay_cfg_array_x15;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
+	}
+
+	__recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 }
 #endif
 
@@ -605,6 +625,12 @@ int board_eth_init(bd_t *bis)
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
 
+	/* The phy address for the AM572x IDK are different than x15 */
+	if (board_is_am572x_idk()) {
+		cpsw_data.slave_data[0].phy_addr = 0;
+		cpsw_data.slave_data[1].phy_addr = 1;
+	}
+
 	ret = cpsw_register(&cpsw_data);
 	if (ret < 0)
 		printf("Error %d registering CPSW switch\n", ret);

board/ti/am57xx/mux_data.h

@@ -12,7 +12,7 @@
 
 #include <asm/arch/mux_dra7xx.h>
 
-const struct pad_conf_entry core_padconf_array_essential[] = {
+const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
 	{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
 	{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
@@ -264,6 +264,222 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RTCK, (M0 | PIN_INPUT_PULLDOWN)},	/* rtck.rtck */
 };
 
+const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
+	{GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin4b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a1.vin4b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin4b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin4b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin4b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a5.vin4b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin4b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin4b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a8.vin4b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin4b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin4b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin4b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a12.vin4b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d8.gpio3_12 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
+	{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d13.gpio3_17 */
+	{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d15.gpio3_19 */
+	{VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d17.gpio3_21 */
+	{VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d18.gpio3_22 */
+	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
+	{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.ecap1 */
+	{VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.gpio4_4 */
+	{VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.gpio4_5 */
+	{VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.pr1_pru1_gpo2 */
+	{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.pr1_mii_mt1_clk */
+	{VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.pr1_mii_mii1_txen */
+	{VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.pr1_mii_mii1_txd3 */
+	{VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.pr1_mii_mii1_txd2 */
+	{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT)},		/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT)},		/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_INPUT)},		/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT)},		/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT)},		/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT)},		/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT)},		/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT)},		/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT)},		/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT)},		/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT)},		/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT)},		/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT)},		/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT)},		/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT)},		/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT)},		/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT)},		/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT)},		/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT)},		/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT)},		/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT)},		/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT)},		/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT)},		/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT)},		/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT)},		/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT)},		/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT)},		/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP)},	/* mdio_d.mdio_d */
+	{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)},	/* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
+	{UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.pr1_mii0_rxdv */
+	{UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.rp1_mii_mr0_clk */
+	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)},  /* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0  | PIN_OUTPUT_PULLUP)},  /* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)},	/* gpio6_16.gpio6)_16 */
+	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.i6_19 */
+	{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.gpio5_1 */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
+	{MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.pr2_pru1_gpo1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.pr2_pru1_gpo3 */
+	{MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr1.pr2_pru1_gpo4 */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
+	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},		/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs1.gpio7_11 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_OUTPUT)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
+	{UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart1_rxd.gpio7_22 */
+	{UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.gpio7_23 */
+	{I2C2_SDA, (M1 | PIN_INPUT)},		/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},		/* i2c2_scl.hdmi1_ddc_sda */
+	{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_INPUT_PULLUP)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT_PULLDOWN)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_INPUT)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT_PULLUP)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT_PULLUP)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_OUTPUT_PULLUP)},	/* resetn.resetn */
+	{RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rstoutn.rstoutn */
+};
+
 const struct pad_conf_entry early_padconf[] = {
 	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
 	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
@@ -272,7 +488,7 @@ const struct pad_conf_entry early_padconf[] = {
 };
 
 #ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
 	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
 	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
 	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
@@ -326,5 +542,53 @@ const struct iodelay_cfg_entry iodelay_cfg_array[] = {
 	{0x0AEC, 232, 1278},	/* CFG_VIN2A_D22_IN */
 	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
 };
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
+	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
+	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
+	{0x0138, 2605, 45},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},		/* CFG_GPMC_A13_IN */
+	{0x0150, 1976, 1389},	/* CFG_GPMC_A14_IN */
+	{0x015C, 1872, 1408},	/* CFG_GPMC_A15_IN */
+	{0x0168, 1914, 1506},	/* CFG_GPMC_A16_IN */
+	{0x0170, 57, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 1904, 1471},	/* CFG_GPMC_A17_IN */
+	{0x0188, 1690, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 2917, 0},	/* CFG_GPMC_A1_IN */
+	{0x0204, 3156, 178},	/* CFG_GPMC_A2_IN */
+	{0x0210, 3109, 246},	/* CFG_GPMC_A3_IN */
+	{0x021C, 3142, 100},	/* CFG_GPMC_A4_IN */
+	{0x0228, 3084, 33},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2778, 0},	/* CFG_GPMC_A6_IN */
+	{0x0240, 3110, 0},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2874, 0},	/* CFG_GPMC_A8_IN */
+	{0x0258, 3072, 0},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},		/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 201, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 229, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 141, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 495, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 660, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 65, 70},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 125, 70},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 0, 70},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 70},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 65, 70},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},		/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 612, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 4, 927},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 136, 1340},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 130, 1450},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 144, 1269},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1330},	/* CFG_VIN2A_D23_IN */
+};
 #endif
 #endif /* _MUX_DATA_BEAGLE_X15_H_ */

board/ti/ks2_evm/board.c

@@ -20,6 +20,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TI_AEMIF)
 static struct aemif_config aemif_configs[] = {
 	{			/* CS0 */
 		.mode		= AEMIF_MODE_NAND,
@@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = {
 		.width		= AEMIF_WIDTH_8,
 	},
 };
+#endif
 
 int dram_init(void)
 {
@@ -42,7 +44,10 @@ int dram_init(void)
 
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
 	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
 	if (ddr3_size)
 		ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
 	return 0;

board/warp7/Kconfig

@@ -0,0 +1,9 @@
+if TARGET_WARP7
+
+config SYS_BOARD
+	default "warp7"
+
+config SYS_CONFIG_NAME
+	default "warp7"
+
+endif

board/warp7/MAINTAINERS

@@ -0,0 +1,6 @@
+WARP7 BOARD
+M:	Fabio Estevam <fabio.estevam@nxp.com>
+S:	Maintained
+F:	board/warp7/
+F:	include/configs/warp7.h
+F:	configs/warp7_defconfig

board/warp7/Makefile

@@ -0,0 +1,6 @@
+# (C) Copyright 2016 NXP Semiconductors
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := warp7.o

board/warp7/imximage.cfg

@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION	2
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000015
+DATA 4 0x307a0204 0x00161616
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f0f0404
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x00000d6e
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+DATA 4 0x307900c0 0x0e4c7304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1

board/warp7/warp7.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ * Author: Fabio Estevam <fabio.estevam@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/crm_regs.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
+			PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |	\
+			PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+		/* Assume uSDHC3 emmc is always present */
+		return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: WARP7\n");
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_DEVICE;
+}

board/xilinx/zynq/board.c

@@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 	return 0;
 }
 
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+			       const u32 *cell, int n)
+{
+	int i = 0, b, banks;
+	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+	int address_cells = fdt_address_cells(fdt, parent_offset);
+	int size_cells = fdt_size_cells(fdt, parent_offset);
+	char *p = buf;
+	u64 val;
+	u64 vals;
+
+	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+	      __func__, address_cells, size_cells, buf, cell);
+
+	/* Check memory bank setup */
+	banks = n % (address_cells + size_cells);
+	if (banks)
+		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+		      n, address_cells, size_cells);
+
+	banks = n / (address_cells + size_cells);
+
+	for (b = 0; b < banks; b++) {
+		debug("%s: Bank #%d:\n", __func__, b);
+		if (address_cells == 2) {
+			val = cell[i + 1];
+			val <<= 32;
+			val |= cell[i];
+			val = fdt64_to_cpu(val);
+			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+			      __func__, val, p, &cell[i]);
+			*(phys_addr_t *)p = val;
+		} else {
+			debug("%s: addr32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_addr_t);
+		i += address_cells;
+
+		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+		      sizeof(phys_addr_t));
+
+		if (size_cells == 2) {
+			vals = cell[i + 1];
+			vals <<= 32;
+			vals |= cell[i];
+			vals = fdt64_to_cpu(vals);
+
+			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+			      __func__, vals, p, &cell[i]);
+			*(phys_size_t *)p = vals;
+		} else {
+			debug("%s: size32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_size_t);
+		i += size_cells;
+
+		debug("%s: ps=%p, i=%x, size=%zu\n",
+		      __func__, p, i, sizeof(phys_size_t));
+	}
+
+	/* Return the first address size */
+	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+	int bank;
+
+	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		debug("Bank #%d: start %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].start);
+		debug("Bank #%d: size %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].size);
+	}
+}
+
 int dram_init(void)
 {
-	int node;
-	fdt_addr_t addr;
-	fdt_size_t size;
+	int node, len;
 	const void *blob = gd->fdt_blob;
+	const u32 *cell;
 
-	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
-					     "memory", 7);
-	if (node == -FDT_ERR_NOTFOUND) {
-		debug("ZYNQ DRAM: Can't get memory node\n");
+	memset(&tmp, 0, sizeof(tmp));
+
+	/* find or create "/memory" node. */
+	node = fdt_subnode_offset(blob, 0, "memory");
+	if (node < 0) {
+		printf("%s: Can't get memory node\n", __func__);
+		return node;
+	}
+
+	/* Get pointer to cells and lenght of it */
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell) {
+		printf("%s: Can't get reg property\n", __func__);
 		return -1;
 	}
-	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
-	if (addr == FDT_ADDR_T_NONE || size == 0) {
-		debug("ZYNQ DRAM: Can't get base address or size\n");
-		return -1;
-	}
-	gd->ram_size = size;
+
+	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
 	zynq_ddrc_init();
 
 	return 0;
 }
+#else
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#endif

board/xilinx/zynqmp/zynqmp.c

@@ -6,7 +6,6 @@
  */
 
 #include <common.h>
-#include <netdev.h>
 #include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
@@ -63,8 +62,8 @@ static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
 	int address_cells = fdt_address_cells(fdt, parent_offset);
 	int size_cells = fdt_size_cells(fdt, parent_offset);
 	char *p = buf;
-	phys_addr_t val;
-	phys_size_t vals;
+	u64 val;
+	u64 vals;
 
 	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
 	      __func__, address_cells, size_cells, buf, cell);
@@ -166,7 +165,7 @@ int dram_init(void)
 
 	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
 
-	debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
 
 	return 0;
 }

cmd/Kconfig

@@ -173,6 +173,13 @@ config CMD_ELF
 	help
 	  Boot an ELF/vxWorks image from the memory.
 
+config CMD_FDT
+	bool "Flattened Device Tree utility commands"
+	default y
+	depends on OF_LIBFDT
+	help
+	  Do FDT related setup before booting into the Operating System.
+
 config CMD_GO
 	bool "go"
 	default y

cmd/Makefile

@@ -54,7 +54,7 @@ obj-$(CONFIG_CMD_EXT4) += ext4.o
 obj-$(CONFIG_CMD_EXT2) += ext2.o
 obj-$(CONFIG_CMD_FAT) += fat.o
 obj-$(CONFIG_CMD_FDC) += fdc.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_CMD_FDT) += fdt.o
 obj-$(CONFIG_CMD_FITUPD) += fitupd.o
 obj-$(CONFIG_CMD_FLASH) += flash.o
 ifdef CONFIG_FPGA

cmd/bootefi.c

@@ -12,6 +12,10 @@
 #include <errno.h>
 #include <libfdt.h>
 #include <libfdt_env.h>
+#include <memalign.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * When booting using the "bootefi" command, we don't know which
@@ -34,17 +38,30 @@ static struct efi_device_path_file_path bootefi_image_path[] = {
 	}
 };
 
+static struct efi_device_path_file_path bootefi_device_path[] = {
+	{
+		.dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+		.dp.length = sizeof(bootefi_image_path[0]),
+		.str = { 'b','o','o','t','e','f','i' },
+	}, {
+		.dp.type = DEVICE_PATH_TYPE_END,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+		.dp.length = sizeof(bootefi_image_path[0]),
+	}
+};
+
 static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
 			void **protocol_interface, void *agent_handle,
 			void *controller_handle, uint32_t attributes)
 {
-	*protocol_interface = bootefi_image_path;
+	*protocol_interface = bootefi_device_path;
 	return EFI_SUCCESS;
 }
 
 /* The EFI loaded_image interface for the image executed via "bootefi" */
 static struct efi_loaded_image loaded_image_info = {
-	.device_handle = bootefi_image_path,
+	.device_handle = bootefi_device_path,
 	.file_path = bootefi_image_path,
 };
 
@@ -63,7 +80,7 @@ static struct efi_object loaded_image_info_obj = {
 		{
 			/*
 			 * When asking for the device path interface, return
-			 * bootefi_image_path
+			 * bootefi_device_path
 			 */
 			.guid = &efi_guid_device_path,
 			.open = &bootefi_open_dp,
@@ -73,22 +90,59 @@ static struct efi_object loaded_image_info_obj = {
 
 /* The EFI object struct for the device the "bootefi" image was loaded from */
 static struct efi_object bootefi_device_obj = {
-	.handle = bootefi_image_path,
+	.handle = bootefi_device_path,
 	.protocols = {
 		{
 			/* When asking for the device path interface, return
-			 * bootefi_image_path */
+			 * bootefi_device_path */
 			.guid = &efi_guid_device_path,
 			.open = &bootefi_open_dp,
 		}
 	},
 };
 
+static void *copy_fdt(void *fdt)
+{
+	u64 fdt_size = fdt_totalsize(fdt);
+	unsigned long fdt_ram_start = -1L, fdt_pages;
+	u64 new_fdt_addr;
+	void *new_fdt;
+	int i;
+
+        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+                u64 ram_start = gd->bd->bi_dram[i].start;
+                u64 ram_size = gd->bd->bi_dram[i].size;
+
+		if (!ram_size)
+			continue;
+
+		if (ram_start < fdt_ram_start)
+			fdt_ram_start = ram_start;
+	}
+
+	/* Give us at least 4kb breathing room */
+	fdt_size = ALIGN(fdt_size + 4096, 4096);
+	fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
+
+	/* Safe fdt location is at 128MB */
+	new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size;
+	if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+			       &new_fdt_addr) != EFI_SUCCESS) {
+		/* If we can't put it there, put it somewhere */
+		new_fdt_addr = (ulong)memalign(4096, fdt_size);
+	}
+	new_fdt = (void*)(ulong)new_fdt_addr;
+	memcpy(new_fdt, fdt, fdt_totalsize(fdt));
+	fdt_set_totalsize(new_fdt, fdt_size);
+
+	return new_fdt;
+}
+
 /*
  * Load an EFI payload into a newly allocated piece of memory, register all
  * EFI objects it would want to access and jump to it.
  */
-static unsigned long do_bootefi_exec(void *efi)
+static unsigned long do_bootefi_exec(void *efi, void *fdt)
 {
 	ulong (*entry)(void *image_handle, struct efi_system_table *st);
 	ulong fdt_pages, fdt_size, fdt_start, fdt_end;
@@ -100,32 +154,31 @@ static unsigned long do_bootefi_exec(void *efi)
 	 */
 	efi_save_gd();
 
-	/* Update system table to point to our currently loaded FDT */
-
-	if (working_fdt) {
+	if (fdt && !fdt_check_header(fdt)) {
 		/* Prepare fdt for payload */
-		if (image_setup_libfdt(&img, working_fdt, 0, NULL)) {
+		fdt = copy_fdt(fdt);
+
+		if (image_setup_libfdt(&img, fdt, 0, NULL)) {
 			printf("ERROR: Failed to process device tree\n");
 			return -EINVAL;
 		}
 
 		/* Link to it in the efi tables */
 		systab.tables[0].guid = EFI_FDT_GUID;
-		systab.tables[0].table = working_fdt;
+		systab.tables[0].table = fdt;
 		systab.nr_tables = 1;
 
 		/* And reserve the space in the memory map */
-		fdt_start = ((ulong)working_fdt) & ~EFI_PAGE_MASK;
-		fdt_end = ((ulong)working_fdt) + fdt_totalsize(working_fdt);
+		fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
+		fdt_end = ((ulong)fdt) + fdt_totalsize(fdt);
 		fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
 		fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
 		/* Give a bootloader the chance to modify the device tree */
 		fdt_pages += 2;
 		efi_add_memory_map(fdt_start, fdt_pages,
 				   EFI_BOOT_SERVICES_DATA, true);
-
 	} else {
-		printf("WARNING: No device tree loaded, expect boot to fail\n");
+		printf("WARNING: Invalid device tree, expect boot to fail\n");
 		systab.nr_tables = 0;
 	}
 
@@ -156,8 +209,8 @@ static unsigned long do_bootefi_exec(void *efi)
 /* Interpreter command to boot an arbitrary EFI image from memory */
 static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	char *saddr;
-	unsigned long addr;
+	char *saddr, *sfdt;
+	unsigned long addr, fdt_addr = 0;
 	int r = 0;
 
 	if (argc < 2)
@@ -166,8 +219,13 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	addr = simple_strtoul(saddr, NULL, 16);
 
+	if (argc > 2) {
+		sfdt = argv[2];
+		fdt_addr = simple_strtoul(sfdt, NULL, 16);
+	}
+
 	printf("## Starting EFI application at 0x%08lx ...\n", addr);
-	r = do_bootefi_exec((void *)addr);
+	r = do_bootefi_exec((void *)addr, (void*)fdt_addr);
 	printf("## Application terminated, r = %d\n", r);
 
 	if (r != 0)
@@ -178,32 +236,49 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #ifdef CONFIG_SYS_LONGHELP
 static char bootefi_help_text[] =
-	"<image address>\n"
-	"  - boot EFI payload stored at address <image address>\n"
-	"\n"
-	"Since most EFI payloads want to have a device tree provided, please\n"
-	"make sure you load a device tree using the fdt addr command before\n"
-	"executing bootefi.\n";
+	"<image address> [fdt address]\n"
+	"  - boot EFI payload stored at address <image address>.\n"
+	"    If specified, the device tree located at <fdt address> gets\n"
+	"    exposed as EFI configuration table.\n";
 #endif
 
 U_BOOT_CMD(
-	bootefi, 2, 0, do_bootefi,
+	bootefi, 3, 0, do_bootefi,
 	"Boots an EFI payload from memory\n",
 	bootefi_help_text
 );
 
-void efi_set_bootdev(const char *dev, const char *devnr)
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
 {
-	char devname[16] = { 0 }; /* dp->str is u16[16] long */
+	__maybe_unused struct blk_desc *desc;
+	char devname[32] = { 0 }; /* dp->str is u16[32] long */
 	char *colon;
 
 	/* Assemble the condensed device name we use in efi_disk.c */
 	snprintf(devname, sizeof(devname), "%s%s", dev, devnr);
 	colon = strchr(devname, ':');
+
+#ifdef CONFIG_ISO_PARTITION
+	/* For ISOs we create partition block devices */
+	desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
+	if (desc && (desc->type != DEV_TYPE_UNKNOWN) &&
+	    (desc->part_type == PART_TYPE_ISO)) {
+		if (!colon)
+			snprintf(devname, sizeof(devname), "%s%s:1", dev,
+				 devnr);
+		colon = NULL;
+	}
+#endif
+
 	if (colon)
 		*colon = '\0';
 
-	/* Patch the bootefi_image_path to the target device */
+	/* Patch bootefi_device_path to the target device */
+	memset(bootefi_device_path[0].str, 0, sizeof(bootefi_device_path[0].str));
+	ascii2unicode(bootefi_device_path[0].str, devname);
+
+	/* Patch bootefi_image_path to the target file path */
 	memset(bootefi_image_path[0].str, 0, sizeof(bootefi_image_path[0].str));
+	snprintf(devname, sizeof(devname), "%s", path);
 	ascii2unicode(bootefi_image_path[0].str, devname);
 }

cmd/fs.c

@@ -27,7 +27,8 @@ U_BOOT_CMD(
 static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
 				char * const argv[])
 {
-	efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "");
+	efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
+			(argc > 4) ? argv[4] : "");
 	return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
 }
 

cmd/nvedit.c

@@ -49,12 +49,13 @@ DECLARE_GLOBAL_DATA_PTR;
 	!defined(CONFIG_ENV_IS_IN_NAND)		&& \
 	!defined(CONFIG_ENV_IS_IN_NVRAM)	&& \
 	!defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
+	!defined(CONFIG_ENV_IS_IN_SATA)		&& \
 	!defined(CONFIG_ENV_IS_IN_SPI_FLASH)	&& \
 	!defined(CONFIG_ENV_IS_IN_REMOTE)	&& \
 	!defined(CONFIG_ENV_IS_IN_UBI)		&& \
 	!defined(CONFIG_ENV_IS_NOWHERE)
 # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
 #endif
 
 /*

cmd/usb_mass_storage.c

@@ -50,14 +50,16 @@ static void ums_fini(void)
 
 #define UMS_NAME_LEN 16
 
-static int ums_init(const char *devtype, const char *devnums)
+static int ums_init(const char *devtype, const char *devnums_part_str)
 {
-	char *s, *t, *devnum, *name;
+	char *s, *t, *devnum_part_str, *name;
 	struct blk_desc *block_dev;
-	int ret;
+	disk_partition_t info;
+	int partnum;
+	int ret = -1;
 	struct ums *ums_new;
 
-	s = strdup(devnums);
+	s = strdup(devnums_part_str);
 	if (!s)
 		return -1;
 
@@ -65,36 +67,47 @@ static int ums_init(const char *devtype, const char *devnums)
 	ums_count = 0;
 
 	for (;;) {
-		devnum = strsep(&t, ",");
-		if (!devnum)
+		devnum_part_str = strsep(&t, ",");
+		if (!devnum_part_str)
 			break;
 
-		ret = blk_get_device_by_str(devtype, devnum, &block_dev);
-		if (ret < 0)
+		partnum = blk_get_device_part_str(devtype, devnum_part_str,
+					&block_dev, &info, 1);
+
+		if (partnum < 0)
 			goto cleanup;
 
+		/* Check if the argument is in legacy format. If yes,
+		 * expose all partitions by setting the partnum = 0
+		 * e.g. ums 0 mmc 0
+		 */
+		if (!strchr(devnum_part_str, ':'))
+			partnum = 0;
+
 		/* f_mass_storage.c assumes SECTOR_SIZE sectors */
-		if (block_dev->blksz != SECTOR_SIZE) {
-			ret = -1;
+		if (block_dev->blksz != SECTOR_SIZE)
 			goto cleanup;
-		}
 
 		ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
-		if (!ums_new) {
-			ret = -1;
+		if (!ums_new)
 			goto cleanup;
-		}
 		ums = ums_new;
 
+		/* if partnum = 0, expose all partitions */
+		if (partnum == 0) {
+			ums[ums_count].start_sector = 0;
+			ums[ums_count].num_sectors = block_dev->lba;
+		} else {
+			ums[ums_count].start_sector = info.start;
+			ums[ums_count].num_sectors = info.size;
+		}
+
 		ums[ums_count].read_sector = ums_read_sector;
 		ums[ums_count].write_sector = ums_write_sector;
-		ums[ums_count].start_sector = 0;
-		ums[ums_count].num_sectors = block_dev->lba;
+
 		name = malloc(UMS_NAME_LEN);
-		if (!name) {
-			ret = -1;
+		if (!name)
 			goto cleanup;
-		}
 		snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
 		ums[ums_count].name = name;
 		ums[ums_count].block_dev = *block_dev;
@@ -108,9 +121,7 @@ static int ums_init(const char *devtype, const char *devnums)
 		ums_count++;
 	}
 
-	if (!ums_count)
-		ret = -1;
-	else
+	if (ums_count)
 		ret = 0;
 
 cleanup:
@@ -230,6 +241,6 @@ cleanup_ums_init:
 
 U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
 	"Use the UMS [USB Mass Storage]",
-	"<USB_controller> [<devtype>] <devnum>  e.g. ums 0 mmc 0\n"
+	"<USB_controller> [<devtype>] <dev[:part]>  e.g. ums 0 mmc 0\n"
 	"    devtype defaults to mmc"
 );

common/Makefile

@@ -50,6 +50,7 @@ obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
 obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
+obj-$(CONFIG_ENV_IS_IN_SATA) += env_sata.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
 obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o

common/env_sata.c

@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2010-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <errno.h>
+#include <memalign.h>
+#include <sata.h>
+#include <search.h>
+
+#if defined(CONFIG_ENV_SIZE_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+#error ENV REDUND not supported
+#endif
+
+#if !defined(CONFIG_ENV_OFFSET) || !defined(CONFIG_ENV_SIZE)
+#error CONFIG_ENV_OFFSET or CONFIG_ENV_SIZE not defined
+#endif
+
+char *env_name_spec = "SATA";
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int sata_get_env_dev(void)
+{
+	return CONFIG_SYS_SATA_ENV_DEV;
+}
+
+int env_init(void)
+{
+	/* use default */
+	gd->env_addr = (ulong)&default_environment[0];
+	gd->env_valid = 1;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+static inline int write_env(struct blk_desc *sata, unsigned long size,
+			    unsigned long offset, void *buffer)
+{
+	uint blk_start, blk_cnt, n;
+
+	blk_start = ALIGN(offset, sata->blksz) / sata->blksz;
+	blk_cnt   = ALIGN(size, sata->blksz) / sata->blksz;
+
+	n = blk_dwrite(sata, blk_start, blk_cnt, buffer);
+
+	return (n == blk_cnt) ? 0 : -1;
+}
+
+int saveenv(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
+	struct blk_desc *sata = NULL;
+	int env_sata, ret;
+
+	if (sata_initialize())
+		return 1;
+
+	env_sata = sata_get_env_dev();
+
+	sata = sata_get_dev(env_sata);
+	if (sata == NULL) {
+		printf("Unknown SATA(%d) device for environment!\n",
+		       env_sata);
+		return 1;
+	}
+
+	ret = env_export(env_new);
+	if (ret)
+		return 1;
+
+	printf("Writing to SATA(%d)...", env_sata);
+	if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, &env_new)) {
+		puts("failed\n");
+		return 1;
+	}
+
+	puts("done\n");
+	return 0;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+static inline int read_env(struct blk_desc *sata, unsigned long size,
+			   unsigned long offset, void *buffer)
+{
+	uint blk_start, blk_cnt, n;
+
+	blk_start = ALIGN(offset, sata->blksz) / sata->blksz;
+	blk_cnt   = ALIGN(size, sata->blksz) / sata->blksz;
+
+	n = blk_dread(sata, blk_start, blk_cnt, buffer);
+
+	return (n == blk_cnt) ? 0 : -1;
+}
+
+void env_relocate_spec(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+	struct blk_desc *sata = NULL;
+	int env_sata;
+
+	if (sata_initialize())
+		return;
+
+	env_sata = sata_get_env_dev();
+
+	sata = sata_get_dev(env_sata);
+	if (sata == NULL) {
+		printf("Unknown SATA(%d) device for environment!\n",
+		       env_sata);
+		return;
+	}
+
+	if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf))
+		return set_default_env(NULL);
+
+	env_import(buf, 1);
+}

configs/A10-OLinuXino-Lime_defconfig

@@ -12,7 +12,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y

configs/A10s-OLinuXino-M_defconfig

@@ -13,6 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y

configs/A13-OLinuXinoM_defconfig

@@ -17,6 +17,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y

configs/A13-OLinuXino_defconfig

@@ -19,7 +19,10 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010