Release v1.3.2

Update CHANGELOG for release.

Signed-off-by: Wolfgang Denk <wd@denx.de>

CREDITS

@@ -391,6 +391,10 @@ E: dan.poirot@windriver.com
 D: Support for the Wind River sbc405, sbc8240 board
 W: http://www.windriver.com
 
+N: Stelian Pop
+E: stelian.pop@leadtechdesign.com
+D: Atmel AT91CAP9ADK support
+
 N: Stefan Roese
 E: sr@denx.de
 D: AMCC PPC4xx Support
@@ -509,3 +513,18 @@ N: Nobuhiro Iwamatsu
 E: iwamatsu@nigauri.org
 D: Support for SuperH, MS7750SE01 and  MS7722SE01 boards.
 W: http://www.nigauri.org/~iwamatsu/
+
+N: Alan Lu
+E: alnalu001@gmail.com
+D: Support for Artila M-501 starter kit
+W: http://www.artila.com/
+
+N: Kimmo Leppala
+E: kimmo.leppala@sysart.fi
+D: Support for Artila M-501 starter kit
+W: http://www.sysart.fi/
+
+N: Timo Tuunainen
+E: timo.tuunainen@sysart.fi
+D: Support for Artila M-501 starter kit
+W: http://www.sysart.fi/

MAINTAINERS

@@ -351,7 +351,7 @@ Travis Sawyer (travis.sawyer@sandburst.com>
 
 Heiko Schocher <hs@denx.de>
 
-	ids8247			MPC8272
+	ids8247			MPC8247
 	jupiter			MPC5200
 	mgcoge			MPC8247
 	mgsuvd			MPC852

MAKEALL

@@ -446,6 +446,7 @@ LIST_ARM7="		\
 #########################################################################
 
 LIST_ARM9="			\
+	at91cap9adk		\
 	at91rm9200dk		\
 	cmc_pu2			\
 	ap920t			\
@@ -459,6 +460,7 @@ LIST_ARM9="			\
 	cp946es			\
 	cp966			\
 	lpd7a400		\
+	m501sk			\
 	mp2usb			\
 	mx1ads			\
 	mx1fs2			\

Makefile

@@ -24,7 +24,7 @@
 VERSION = 1
 PATCHLEVEL = 3
 SUBLEVEL = 2
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -118,6 +118,9 @@ src :=
 endif
 export obj src
 
+# Make sure CDPATH settings don't interfere
+unexport CDPATH
+
 #########################################################################
 
 ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
@@ -244,7 +247,7 @@ LIBS += libfdt/libfdt.a
 LIBS += api/libapi.a
 
 LIBS := $(addprefix $(obj),$(LIBS))
-.PHONY : $(LIBS)
+.PHONY : $(LIBS) $(VERSION_FILE)
 
 # Add GCC lib
 PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
@@ -326,6 +329,9 @@ $(LIBS):	depend $(obj)include/autoconf.mk
 $(SUBDIRS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $@ all
 
+$(LDSCRIPT):	depend $(obj)include/autoconf.mk
+		$(MAKE) -C $(dir $@) $(notdir $@)
+
 $(NAND_SPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
@@ -397,6 +403,10 @@ tags ctags:
 etags:
 		etags -a -o $(obj)etags `find $(SUBDIRS) $(TAG_SUBDIRS) \
 						-name '*.[ch]' -print`
+cscope:
+		find $(SUBDIRS) $(TAG_SUBDIRS) -name '*.[ch]' -print \
+						> cscope.files
+		cscope -b -q -k
 
 $(obj)System.map:	$(obj)u-boot
 		@$(NM) $< | \
@@ -411,6 +421,7 @@ $(obj)System.map:	$(obj)u-boot
 # to regenerate the autoconf.mk file.
 $(obj)include/autoconf.mk: $(obj)include/config.h $(VERSION_FILE)
 	@$(XECHO) Generating include/autoconf.mk ; \
+	set -e ; \
 	: Generate the dependancies ; \
 	$(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $@ include/common.h > $@.dep ; \
 	: Extract the config macros ; \
@@ -423,7 +434,7 @@ else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
 $(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \
-dep tags ctags etags $(obj)System.map:
+dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
 endif	# config.mk
@@ -485,7 +496,6 @@ icecube_5200_DDR_LOWBOOT08_config	\
 icecube_5100_config:			unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/icecube
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
 		{ if [ "$(findstring DDR,$@)" ] ; \
 			then echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \
@@ -526,7 +536,6 @@ lite5200b_PM_config	\
 lite5200b_LOWBOOT_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/icecube
-	@ >$(obj)include/config.h
 	@ echo "#define CONFIG_MPC5200_DDR"	>>$(obj)include/config.h
 	@ $(XECHO) "... DDR memory revision"
 	@ echo "#define CONFIG_MPC5200"		>>$(obj)include/config.h
@@ -556,7 +565,6 @@ prs200_highboot_config	\
 prs200_highboot_DDR_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/mcc200
-	@ >$(obj)include/config.h
 	@[ -n "$(findstring highboot,$@)" ] || \
 		{ $(XECHO) "... with lowboot configuration" ; \
 		}
@@ -597,7 +605,7 @@ mecp5200_config:  unconfig
 munices_config:	unconfig
 	@$(MKCONFIG) munices ppc mpc5xxx munices
 
-o2dnt_config:
+o2dnt_config:	unconfig
 	@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
 
 pf5200_config:	unconfig
@@ -608,7 +616,6 @@ PM520_DDR_config \
 PM520_ROMBOOT_config \
 PM520_ROMBOOT_DDR_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring DDR,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200_DDR"	>>$(obj)include/config.h ; \
 		  $(XECHO) "... DDR memory revision" ; \
@@ -623,7 +630,7 @@ smmaco4_config: unconfig
 	@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200
 
 cm5200_config:	unconfig
-	@./mkconfig -a cm5200 ppc mpc5xxx cm5200
+	@$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200
 
 spieval_config:	unconfig
 	@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200
@@ -651,7 +658,6 @@ Total5200_Rev2_config		\
 Total5200_Rev2_lowboot_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/total5200
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring 5100,$@)" ] || \
 		{ echo "#define CONFIG_MGT5100"		>>$(obj)include/config.h ; \
 		  $(XECHO) "... with MGT5100 processor" ; \
@@ -686,7 +692,6 @@ TQM5200_config	\
 TQM5200_STK100_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/tqm5200
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring cam5200,$@)" ] || \
 		{ echo "#define CONFIG_CAM5200"	>>$(obj)include/config.h ; \
 		  echo "#define CONFIG_TQM5200S"	>>$(obj)include/config.h ; \
@@ -729,8 +734,15 @@ motionpro_config:	unconfig
 #########################################################################
 ## MPC512x Systems
 #########################################################################
-ads5121_config: unconfig
-	@$(MKCONFIG) ads5121 ppc mpc512x ads5121
+ads5121_config \
+ads5121_PCI_config \
+	:		 unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _PCI_,$@)" ] ; then \
+		echo "#define CONFIG_PCI"  >>$(obj)include/config.h ; \
+		$(XECHO) "... with PCI enabled" ; \
+	fi
+	@$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
 
 
 #########################################################################
@@ -747,7 +759,7 @@ AdderII_config  \
 	@$(MKCONFIG) -a Adder ppc mpc8xx adder
 
 AdderUSB_config:	unconfig
-	@./mkconfig -a AdderUSB ppc mpc8xx adder
+	@$(MKCONFIG) -a AdderUSB ppc mpc8xx adder
 
 ADS860_config	  \
 FADS823_config	  \
@@ -789,7 +801,6 @@ xtract_GEN860T = $(subst _SC,,$(subst _config,,$1))
 GEN860T_SC_config	\
 GEN860T_config: unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _SC,$@)" ] || \
 		{ echo "#define CONFIG_SC" >>$(obj)include/config.h ; \
 		  $(XECHO) "With reduced H/W feature set (SC)..." ; \
@@ -816,7 +827,6 @@ xtract_ICU862 = $(subst _100MHz,,$(subst _config,,$1))
 ICU862_100MHz_config	\
 ICU862_config: unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _100MHz,$@)" ] || \
 		{ echo "#define CONFIG_100MHz"	>>$(obj)include/config.h ; \
 		  $(XECHO) "... with 100MHz system clock" ; \
@@ -830,7 +840,6 @@ IVML24_256_config \
 IVML24_128_config \
 IVML24_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring IVML24_config,$@)" ] || \
 		 { echo "#define CONFIG_IVML24_16M"	>>$(obj)include/config.h ; \
 		 }
@@ -846,7 +855,6 @@ IVMS8_256_config \
 IVMS8_128_config \
 IVMS8_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring IVMS8_config,$@)" ] || \
 		 { echo "#define CONFIG_IVMS8_16M"	>>$(obj)include/config.h ; \
 		 }
@@ -888,7 +896,6 @@ xtract_NETVIA = $(subst _V2,,$(subst _config,,$1))
 NETVIA_V2_config \
 NETVIA_config:		unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring NETVIA_config,$@)" ] || \
 		 { echo "#define CONFIG_NETVIA_VERSION 1" >>$(obj)include/config.h ; \
 		  $(XECHO) "... Version 1" ; \
@@ -904,7 +911,6 @@ xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
 NETPHONE_V2_config \
 NETPHONE_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring NETPHONE_config,$@)" ] || \
 		 { echo "#define CONFIG_NETPHONE_VERSION 1" >>$(obj)include/config.h ; \
 		 }
@@ -924,7 +930,6 @@ NETTA_ISDN_config \
 NETTA_6412_config \
 NETTA_config:		unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring ISDN_,$@)" ] || \
 		 { echo "#define CONFIG_NETTA_ISDN 1" >>$(obj)include/config.h ; \
 		 }
@@ -950,7 +955,6 @@ xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
 NETTA2_V2_config \
 NETTA2_config:		unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring NETTA2_config,$@)" ] || \
 		 { echo "#define CONFIG_NETTA2_VERSION 1" >>$(obj)include/config.h ; \
 		 }
@@ -963,7 +967,6 @@ NC650_Rev1_config \
 NC650_Rev2_config \
 CP850_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring CP850,$@)" ] || \
 		 { echo "#define CONFIG_CP850 1" >>$(obj)include/config.h ; \
 		   echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
@@ -1015,7 +1018,6 @@ RPXlite_DW_NVRAM_LCD_config	\
 RPXlite_DW_NVRAM_64_LCD_config	\
 RPXlite_DW_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _64,$@)" ] || \
 		{ echo "#define RPXlite_64MHz"		>>$(obj)include/config.h ; \
 		  $(XECHO) "... with 64MHz system clock ..."; \
@@ -1046,7 +1048,7 @@ RRvision_LCD_config:	unconfig
 SM850_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
 
-spc1920_config:
+spc1920_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920
 
 SPD823TS_config:	unconfig
@@ -1089,7 +1091,6 @@ TQM885D_config		\
 TK885D_config		\
 virtlab2_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>$(obj)include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>$(obj)include/config.h ; \
@@ -1334,7 +1335,6 @@ PPChameleonEVB_BA_33_config	\
 PPChameleonEVB_ME_33_config	\
 PPChameleonEVB_HI_33_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring EVB_BA,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>$(obj)include/config.h ; \
 		  $(XECHO) "... BASIC model" ; \
@@ -1656,8 +1656,6 @@ PM828_ROMBOOT_PCI_config:	unconfig
 	@if [ "$(findstring _PCI_,$@)" ] ; then \
 		echo "#define CONFIG_PCI"  >>$(obj)include/config.h ; \
 		$(XECHO) "... with PCI enabled" ; \
-	else \
-		>$(obj)include/config.h ; \
 	fi
 	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
 		$(XECHO) "... booting from 8-bit flash" ; \
@@ -1716,7 +1714,6 @@ TQM8265_AA_config:  unconfig
 	TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;	BMODE=60x;;  \
 	TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no;	BMODE=60x;;  \
 	esac; \
-	>$(obj)include/config.h ; \
 	if [ "$${CTYPE}" != "MPC8260" ] ; then \
 		echo "#define CONFIG_$${CTYPE}"	>>$(obj)include/config.h ; \
 	fi; \
@@ -1739,7 +1736,7 @@ TQM8265_AA_config:  unconfig
 	@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
 
 TQM8272_config: unconfig
-	@$(MKCONFIG) -a TQM8272 ppc mpc8260 tqm8272
+	@$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272
 
 VoVPN-GW_66MHz_config	\
 VoVPN-GW_100MHz_config:		unconfig
@@ -1765,7 +1762,6 @@ M5235EVB_Flash32_config:	unconfig
 	M5235EVB_Flash16_config)	FLASH=16;; \
 	M5235EVB_Flash32_config)	FLASH=32;; \
 	esac; \
-	>$(obj)include/config.h ; \
 	if [ "$${FLASH}" != "16" ] ; then \
 		echo "#define NORFLASH_PS32BIT	1" >> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
@@ -1788,14 +1784,12 @@ cobra5272_config :		unconfig
 EB+MCF-EV123_config :		unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/BuS/EB+MCF-EV123
-	@ >$(obj)include/config.h
 	@echo "TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
 	@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
 
 EB+MCF-EV123_internal_config :	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/BuS/EB+MCF-EV123
-	@ >$(obj)include/config.h
 	@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
 	@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
 
@@ -1823,7 +1817,6 @@ M5329BFEE_config :	unconfig
 	M5329AFEE_config)	NAND=0;; \
 	M5329BFEE_config)	NAND=16;; \
 	esac; \
-	>$(obj)include/config.h ; \
 	if [ "$${NAND}" != "0" ] ; then \
 		echo "#define NANDFLASH_SIZE	$${NAND}" > $(obj)include/config.h ; \
 	fi
@@ -1833,7 +1826,6 @@ M5373EVB_config :	unconfig
 	@case "$@" in \
 	M5373EVB_config)	NAND=16;; \
 	esac; \
-	>include/config.h ; \
 	if [ "$${NAND}" != "0" ] ; then \
 		echo "#define NANDFLASH_SIZE	$${NAND}" > $(obj)include/config.h ; \
 	fi
@@ -1855,7 +1847,6 @@ M54455EVB_i66_config :	unconfig
 	M54455EVB_i33_config)		FLASH=INTEL; FREQ=33333333;; \
 	M54455EVB_i66_config)		FLASH=INTEL; FREQ=66666666;; \
 	esac; \
-	>$(obj)include/config.h ; \
 	if [ "$${FLASH}" = "INTEL" ] ; then \
 		echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
@@ -1887,7 +1878,6 @@ M5475GFE_config :	unconfig
 	M5475FFE_config)	BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
 	M5475GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
 	esac; \
-	>include/config.h ; \
 	echo "#define CFG_BUSCLK	133333333" > $(obj)include/config.h ; \
 	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
 	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
@@ -1921,9 +1911,8 @@ M5485HFE_config :	unconfig
 	M5485EFE_config)	BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \
 	M5485FFE_config)	BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
 	M5485GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
-	M5485HFE_config)	BOOT=2;CODE=;VID=1;USB=0;RAM=64;RAM1=0;; \
+	M5485HFE_config)	BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
 	esac; \
-	>include/config.h ; \
 	echo "#define CFG_BUSCLK	100000000" > $(obj)include/config.h ; \
 	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
 	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
@@ -1948,8 +1937,7 @@ M5485HFE_config :	unconfig
 MPC8313ERDB_33_config \
 MPC8313ERDB_66_config: unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _33_,$@)" ] ; then \
+	@if [ "$(findstring _33_,$@)" ] ; then \
 		$(XECHO) -n "...33M ..." ; \
 		echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
 	fi ; \
@@ -1971,8 +1959,7 @@ MPC832XEMDS_HOST_66_config \
 MPC832XEMDS_SLAVE_config \
 MPC832XEMDS_ATM_config:	unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _HOST_,$@)" ] ; then \
+	@if [ "$(findstring _HOST_,$@)" ] ; then \
 		$(XECHO) -n "... PCI HOST " ; \
 		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
 	fi ; \
@@ -2021,8 +2008,7 @@ MPC8360EMDS_HOST_66_config \
 MPC8360EMDS_SLAVE_config \
 MPC8360EMDS_ATM_config: unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _HOST_,$@)" ] ; then \
+	@if [ "$(findstring _HOST_,$@)" ] ; then \
 		$(XECHO) -n "... PCI HOST " ; \
 		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
 	fi ; \
@@ -2050,10 +2036,9 @@ MPC8360EMDS_ATM_config: unconfig
 
 MPC8360ERDK_33_config \
 MPC8360ERDK_66_config \
-MPC8360ERDK_config:
+MPC8360ERDK_config:	unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _33_,$@)" ] ; then \
+	@if [ "$(findstring _33_,$@)" ] ; then \
 		$(XECHO) -n "... CLKIN 33MHz " ; \
 		echo "#define CONFIG_CLKIN_33MHZ" >>$(obj)include/config.h ;\
 	fi ;
@@ -2062,8 +2047,7 @@ MPC8360ERDK_config:
 MPC837XEMDS_config \
 MPC837XEMDS_HOST_config:	unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _HOST_,$@)" ] ; then \
+	@if [ "$(findstring _HOST_,$@)" ] ; then \
 		$(XECHO) -n "... PCI HOST " ; \
 		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
 	fi ;
@@ -2095,8 +2079,7 @@ MPC8540EVAL_66_config \
 MPC8540EVAL_33_slave_config \
 MPC8540EVAL_66_slave_config:	  unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _33_,$@)" ] ; then \
+	@if [ "$(findstring _33_,$@)" ] ; then \
 		$(XECHO) "... 33 MHz PCI" ; \
 	else \
 		echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \
@@ -2116,8 +2099,7 @@ MPC8560ADS_config:	unconfig
 MPC8541CDS_legacy_config \
 MPC8541CDS_config:	unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _legacy_,$@)" ] ; then \
+	@if [ "$(findstring _legacy_,$@)" ] ; then \
 		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
 		$(XECHO) "... legacy" ; \
 	fi
@@ -2129,8 +2111,7 @@ MPC8544DS_config:	unconfig
 MPC8548CDS_legacy_config \
 MPC8548CDS_config:	unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _legacy_,$@)" ] ; then \
+	@if [ "$(findstring _legacy_,$@)" ] ; then \
 		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
 		$(XECHO) "... legacy" ; \
 	fi
@@ -2139,8 +2120,7 @@ MPC8548CDS_config:	unconfig
 MPC8555CDS_legacy_config \
 MPC8555CDS_config:	unconfig
 	@mkdir -p $(obj)include
-	@echo "" >$(obj)include/config.h ; \
-	if [ "$(findstring _legacy_,$@)" ] ; then \
+	@if [ "$(findstring _legacy_,$@)" ] ; then \
 		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
 		$(XECHO) "... legacy" ; \
 	fi
@@ -2163,7 +2143,6 @@ sbc8540_66_config:	unconfig
 		echo "#define CONFIG_PCI_66"	>>$(obj)include/config.h ; \
 		$(XECHO) "... 66 MHz PCI" ; \
 	else \
-		>$(obj)include/config.h ; \
 		$(XECHO) "... 33 MHz PCI" ; \
 	fi
 	@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
@@ -2179,7 +2158,6 @@ sbc8560_66_config:      unconfig
 		echo "#define CONFIG_PCI_66"	>>$(obj)include/config.h ; \
 		$(XECHO) "... 66 MHz PCI" ; \
 	else \
-		>$(obj)include/config.h ; \
 		$(XECHO) "... 33 MHz PCI" ; \
 	fi
 	@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
@@ -2193,8 +2171,6 @@ stxssa_4M_config:	unconfig
 	@if [ "$(findstring _4M_,$@)" ] ; then \
 		echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
 		$(XECHO) "... with 4 MiB flash memory" ; \
-	else \
-		>$(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a stxssa ppc mpc85xx stxssa
 
@@ -2204,7 +2180,6 @@ TQM8555_config		\
 TQM8560_config:		unconfig
 	@mkdir -p $(obj)include
 	@CTYPE=$(subst TQM,,$(@:_config=)); \
-	>$(obj)include/config.h ; \
 	$(XECHO) "... TQM"$${CTYPE}; \
 	echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
@@ -2224,7 +2199,7 @@ MPC8641HPCN_config:    unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
 
 sbc8641d_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
+	@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
 
 #########################################################################
 ## 74xx/7xx Systems
@@ -2310,8 +2285,11 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
 
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
+at91cap9adk_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91cap9
+
 at91rm9200dk_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
 
 cmc_pu2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@@ -2322,6 +2300,8 @@ csb637_config	:	unconfig
 mp2usb_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
 
+m501sk_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm920t m501sk NULL at91rm9200
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2362,17 +2342,8 @@ mx1ads_config	:	unconfig
 mx1fs2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
 
-netstar_32_config	\
 netstar_config:		unconfig
-	@mkdir -p $(obj)include
-	@if [ "$(findstring _32_,$@)" ] ; then \
-		$(XECHO) "... 32MB SDRAM" ; \
-		echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>$(obj)include/config.h ; \
-	else \
-		$(XECHO) "... 64MB SDRAM" ; \
-		echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>$(obj)include/config.h ; \
-	fi
-	@$(MKCONFIG) -a netstar arm arm925t netstar
+	@$(MKCONFIG) $(@:_config=) arm arm925t netstar
 
 omap1510inn_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
@@ -2445,7 +2416,6 @@ trab_bigflash_config \
 trab_old_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/trab
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _bigram,$@)" ] || \
 		{ echo "#define CONFIG_FLASH_8MB"  >>$(obj)include/config.h ; \
 		  echo "#define CONFIG_RAM_32MB"   >>$(obj)include/config.h ; \
@@ -2487,8 +2457,7 @@ cm41xx_config	:	unconfig
 
 gth2_config		:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a gth2 mips mips gth2
 
 #########################################################################
@@ -2551,7 +2520,7 @@ cradle_config	:	unconfig
 csb226_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa csb226
 
-delta_config :
+delta_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa delta
 
 innokom_config	:	unconfig
@@ -2578,8 +2547,6 @@ scpu_config:    unconfig
 	@if [ "$(findstring scpu_,$@)" ] ; then \
 		echo "#define CONFIG_SCPU"	>>$(obj)include/config.h ; \
 		$(XECHO) "... on SCPU board variant" ; \
-	else \
-		>$(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive
 
@@ -2611,6 +2578,7 @@ omap2420h4_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
 
 apollon_config		: unconfig
+	@mkdir -p $(obj)include
 	@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
 	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
 	@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
@@ -2644,7 +2612,6 @@ incaip_133MHz_config	\
 incaip_150MHz_config	\
 incaip_config: unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _100MHz,$@)" ] || \
 		{ echo "#define CPU_CLOCK_RATE 100000000" >>$(obj)include/config.h ; \
 		  $(XECHO) "... with 100MHz system clock" ; \
@@ -2667,44 +2634,37 @@ tb0229_config: unconfig
 #########################################################################
 dbau1000_config		:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_DBAU1000 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
 dbau1100_config		:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_DBAU1100 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
 dbau1500_config		:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_DBAU1500 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
 dbau1550_config		:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
 dbau1550_el_config	:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
 pb1000_config		:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_PB1000 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a pb1x00 mips mips pb1x00
 
 qemu_mips_config: unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_QEMU_MIPS 1" >>$(obj)include/config.h
+	@echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
 
 #########################################################################
@@ -2725,7 +2685,6 @@ DK1C20_safe_32_config		\
 DK1C20_standard_32_config	\
 DK1C20_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _safe_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \
 		  $(XECHO) "... NIOS 'safe_32' configuration" ; \
@@ -2745,7 +2704,6 @@ DK1S10_standard_32_config	\
 DK1S10_mtx_ldk_20_config	\
 DK1S10_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _safe_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \
 		  $(XECHO) "... NIOS 'safe_32' configuration" ; \
@@ -2768,7 +2726,6 @@ ADNPESC1_DNPEVA2_base_32_config	\
 ADNPESC1_base_32_config		\
 ADNPESC1_config: unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
 	@[ -z "$(findstring _DNPEVA2,$@)" ] || \
 		{ echo "#define CONFIG_DNPEVA2 1" >>$(obj)include/config.h ; \
 		  $(XECHO) "... DNP/EVA2 configuration" ; \
@@ -2810,20 +2767,17 @@ PCI5441_config : unconfig
 #########################################################################
 suzaku_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_SUZAKU 1" >> $(obj)include/config.h
+	@echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 
 ml401_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_ML401 1" >> $(obj)include/config.h
+	@echo "#define CONFIG_ML401 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx
 
 xupv2p_config:	unconfig
 	@mkdir -p $(obj)include
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h
+	@echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
 
 #========================================================================
@@ -2867,66 +2821,60 @@ atngw100_config	:	unconfig
 ## sh3 (Renesas SuperH)
 #########################################################################
 ms7720se_config: unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_MS7720SE 1" >> include/config.h
-	@./mkconfig -a $(@:_config=) sh sh3 ms7720se
+	@echo "#define CONFIG_MS7720SE 1" > include/config.h
+	@$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se
 
 #########################################################################
 ## sh4 (Renesas SuperH)
 #########################################################################
 ms7750se_config: unconfig
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_MS7750SE 1" >> $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 ms7750se
+	@echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7750se
 
 ms7722se_config :	unconfig
-	@ >$(obj)include/config.h
-	@echo "#define CONFIG_MS7722SE 1" >> $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 ms7722se
+	@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se
 
 #########################################################################
 #########################################################################
 #########################################################################
 
 clean:
+	@rm -f $(obj)examples/82559_eeprom $(obj)examples/eepro100_eeprom \
+	       $(obj)examples/hello_world  $(obj)examples/interrupt	  \
+	       $(obj)examples/mem_to_mem_idma2intr			  \
+	       $(obj)examples/sched	   $(obj)examples/smc91111_eeprom \
+	       $(obj)examples/test_burst   $(obj)examples/timer
+	@rm -f $(obj)tools/bmp_logo	   $(obj)tools/easylogo/easylogo  \
+	       $(obj)tools/env/{fw_printenv,fw_setenv}			  \
+	       $(obj)tools/envcrc					  \
+	       $(obj)tools/gdb/{astest,gdbcont,gdbsend}			  \
+	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
+	       $(obj)tools/mkimage	   $(obj)tools/mpc86x_clk	  \
+	       $(obj)tools/ncb		   $(obj)tools/ubsha1
+	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
+	       $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin}	  \
+	       $(obj)board/trab/trab_fkt   $(obj)board/voiceblue/eeprom   \
+	       $(obj)board/{integratorap,integratorcp}/u-boot.lds	  \
+	       $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds
+	@rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map}
+	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl.map}
+	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
 		-o -name '*.o'	-o -name '*.a'	\) -print \
 		| xargs rm -f
-	@rm -f $(obj)examples/hello_world $(obj)examples/timer \
-	      $(obj)examples/eepro100_eeprom $(obj)examples/sched \
-	      $(obj)examples/mem_to_mem_idma2intr $(obj)examples/82559_eeprom \
-	      $(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
-	      $(obj)examples/test_burst
-	@rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
-		$(obj)tools/gen_eth_addr $(obj)tools/ubsha1
-	@rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
-	@rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
-	@rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
-	@rm -f $(obj)tools/env/fw_printenv $(obj)tools/env/fw_setenv
-	@rm -f $(obj)board/cray/L1/bootscript.c $(obj)board/cray/L1/bootscript.image
-	@rm -f $(obj)board/netstar/eeprom $(obj)board/netstar/crcek $(obj)board/netstar/crcit
-	@rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
-	@rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
-	@rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
-	@rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
-	@rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
-	@rm -f $(obj)include/bmp_logo.h
-	@rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
-	@rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
-		$(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
-	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
 
 clobber:	clean
 	@find $(OBJTREE) -type f \( -name .depend \
 		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
 		-print0 \
 		| xargs -0 rm -f
-	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS
-	@rm -fr $(obj)*.*~
+	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
+		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
-	@rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c $(obj)tools/sha1.c
-	@rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
+	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,sha1.c,inca-swap-bytes}
+	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f

board/actux1/actux1.c

@@ -89,7 +89,6 @@ int board_init (void)
  */
 int checkboard (void)
 {
-	char revision;
 	char *s = getenv ("serial#");
 
 	puts ("Board: AcTux-1 rev.");

board/actux2/actux2.c

@@ -96,11 +96,15 @@ int board_init (void)
  */
 int checkboard (void)
 {
-	char revision;
 	char *s = getenv ("serial#");
 
 	puts ("Board: AcTux-2 rev.");
 	putc (ACTUX2_BOARDREL + 'A' - 1);
+
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
 	putc ('\n');
 
 	return (0);
@@ -127,8 +131,6 @@ u32 get_board_rev (void)
 
 void reset_phy (void)
 {
-	int i;
-
 	/* init IcPlus IP175C ethernet switch to native IP175C mode */
 	miiphy_write ("NPE0", 29, 31, 0x175C);
 }

board/actux3/actux3.c

@@ -111,7 +111,6 @@ int board_init (void)
  */
 int checkboard (void)
 {
-	char revision;
 	char *s = getenv ("serial#");
 
 	puts ("Board: AcTux-3 rev.");

board/ads5121/Makefile

@@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))

board/ads5121/ads5121.c

@@ -34,6 +34,7 @@
 			 CLOCK_SCCR1_PSCFIFO_EN |			\
 			 CLOCK_SCCR1_DDR_EN |				\
 			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
 			 CLOCK_SCCR1_TPR_EN)
 
 #define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\

board/ads5121/pci.c

@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+
+static struct pci_controller pci_hose;
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile law512x_t *pci_law;
+	volatile pot512x_t *pci_pot;
+	volatile pcictrl512x_t *pci_ctrl;
+	volatile pciconf512x_t *pci_conf;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	struct pci_controller *hose;
+
+	/* Set PCI divider for 33MHz */
+	reg32 = immr->clk.scfr[0];
+	reg32 &= ~(SCFR1_PCI_DIV_MASK);
+	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
+	immr->clk.scfr[0] = reg32;
+
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = &immr->pci_ctrl;
+	pci_conf = &immr->pci_conf;
+
+	hose = &pci_hose;
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	pci_ctrl->gcr = 0;
+	udelay(2000);
+	pci_ctrl->gcr = 1;
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	{
+		int i;
+
+		for (i = 0; i < 1000; i++)
+			udelay(1000);
+	}
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
+
+	/* PCI IO space */
+	pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
+
+	/* PCI mmio - non-prefetch mem space */
+	pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI_MEM_BASE,
+		       CFG_PCI_MEM_PHYS,
+		       CFG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI_MMIO_BASE,
+		       CFG_PCI_MMIO_PHYS,
+		       CFG_PCI_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI_IO_BASE,
+		       CFG_PCI_IO_PHYS,
+		       CFG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR + 0x8300),
+			   (CFG_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose.first_busno);
+			tmp[1] = cpu_to_be32(pci_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+	}
+}
+#endif /* CONFIG_OF_LIBFDT */

board/amcc/acadia/memory.c

@@ -117,7 +117,9 @@ long int initdram(int board_type)
 	return (CFG_MBYTES_RAM << 20);
 }
 
+#ifndef CONFIG_NAND_SPL
 int testdram(void)
 {
 	return (0);
 }
+#endif

board/amcc/sequoia/sequoia.c

@@ -86,10 +86,13 @@ int board_early_init_f(void)
 	/* enable USB device */
 	out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
 
-	/* select Ethernet pins */
+	/* select Ethernet (and optionally IIC1) pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
 	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 		SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
 	mfsdr(SDR0_PFC2, sdr0_pfc2);
 	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 		SDR0_PFC2_SELECT_CONFIG_4;

board/amcc/taihu/taihu.c

@@ -162,7 +162,7 @@ void spi_sda(int bit)
 
 unsigned char spi_read(void)
 {
-	return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+	return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
 }
 
 void taihu_spi_chipsel(int cs)

board/apollon/mem.c

@@ -198,6 +198,8 @@ void gpmc_init(void)
 	sdelay(2000);
 
 	/* setup cs2 */
+	__raw_writel(0x0, GPMC_CONFIG7_2);	/* disable current map */
+	sdelay(1000);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
 		     GPMC_CONFIG1_2);
 	/* It's same as cs 0 */

board/atmel/at91cap9adk/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= at91cap9adk.o led.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/atmel/at91cap9adk/at91cap9adk.c

@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91CAP9.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+#define MP_BLOCK_3_BASE	0xFDF00000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void at91cap9_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
+#endif
+
+#ifdef CONFIG_USART1
+	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
+#endif
+
+#ifdef CONFIG_USART2
+	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+#endif
+
+
+}
+
+static void at91cap9_nor_hw_init(void)
+{
+	/* Ensure EBI supply is 3.3V */
+	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
+
+	/* Configure SMC CS0 for parallel flash */
+	AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
+				     AT91C_FLASH_NCS_WR_SETUP |
+				     AT91C_FLASH_NRD_SETUP |
+				     AT91C_FLASH_NCS_RD_SETUP;
+
+	AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
+				     AT91C_FLASH_NCS_WR_PULSE |
+				     AT91C_FLASH_NRD_PULSE |
+				     AT91C_FLASH_NCS_RD_PULSE;
+
+	AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
+				     AT91C_FLASH_NRD_CYCLE;
+
+	AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
+				     AT91C_SMC_WRITEMODE |
+				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
+				     AT91C_SMC_BAT_BYTE_WRITE |
+				     AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
+				     (AT91C_SMC_TDF & (1 << 16));
+}
+
+#ifdef CONFIG_CMD_NAND
+static void at91cap9_nand_hw_init(void)
+{
+	/* Enable CS3 */
+	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
+				     AT91C_SM_NCS_WR_SETUP |
+				     AT91C_SM_NRD_SETUP |
+				     AT91C_SM_NCS_RD_SETUP;
+
+	AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
+				     AT91C_SM_NCS_WR_PULSE |
+				     AT91C_SM_NRD_PULSE |
+				     AT91C_SM_NCS_RD_PULSE;
+
+	AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
+				     AT91C_SM_NRD_CYCLE;
+
+	AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
+				     AT91C_SMC_WRITEMODE |
+				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
+				     AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
+				     AT91C_SM_TDF;
+
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+
+	/* RDY/BSY is not connected */
+
+	/* Enable NandFlash */
+	AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
+	AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void at91cap9_spi_hw_init(void)
+{
+	AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
+				   AT91C_PD1_SPI0_NPCS3D;
+	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
+				   AT91C_PD1_SPI0_NPCS3D;
+
+	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
+	AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
+				   AT91C_PA1_SPI0_MOSI |
+				   AT91C_PA0_SPI0_MISO |
+				   AT91C_PA3_SPI0_NPCS1 |
+				   AT91C_PA5_SPI0_NPCS0 |
+				   AT91C_PA2_SPI0_SPCK;
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
+				   AT91C_PA4_SPI0_NPCS2A |
+				   AT91C_PA1_SPI0_MOSI |
+				   AT91C_PA0_SPI0_MISO |
+				   AT91C_PA3_SPI0_NPCS1 |
+				   AT91C_PA5_SPI0_NPCS0 |
+				   AT91C_PA2_SPI0_SPCK;
+
+	/* Enable Clock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91cap9_macb_hw_init(void)
+{
+	unsigned int gpio;
+
+	/* Enable clock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PB22) => PHY normal mode (not Test mode)
+	 *	ERX0 (PB25) => PHY ADDR0
+	 *	ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
+				     AT91C_PB25_E_RX0 |
+				     AT91C_PB26_E_RX1;
+
+	/* Need to reset PHY -> 500ms reset */
+	AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
+				    (AT91C_RSTC_ERSTL & (0x0D << 8)) |
+				    AT91C_RSTC_URSTEN;
+	AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
+				    AT91C_RSTC_EXTRST;
+
+	/* Wait for end hardware reset */
+	while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
+
+	/* Re-enable pull-up */
+	AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
+				     AT91C_PB25_E_RX0 |
+				     AT91C_PB26_E_RX1;
+
+#ifdef CONFIG_RMII
+	gpio =	AT91C_PB30_E_MDIO |
+		AT91C_PB29_E_MDC  |
+		AT91C_PB21_E_TXCK |
+		AT91C_PB27_E_RXER |
+		AT91C_PB25_E_RX0  |
+		AT91C_PB22_E_RXDV |
+		AT91C_PB26_E_RX1  |
+		AT91C_PB28_E_TXEN |
+		AT91C_PB23_E_TX0  |
+		AT91C_PB24_E_TX1;
+	AT91C_BASE_PIOB->PIO_ASR = gpio;
+	AT91C_BASE_PIOB->PIO_BSR = 0;
+	AT91C_BASE_PIOB->PIO_PDR = gpio;
+#else
+#error AT91CAP9A-DK works only in RMII mode
+#endif
+
+	/* Unlock EMAC, 3 0 2 1 sequence */
+#define MP_MAC_KEY0	0x5969cb2a
+#define MP_MAC_KEY1	0xb4a1872e
+#define MP_MAC_KEY2	0x05683fbc
+#define MP_MAC_KEY3	0x3634fba4
+#define UNLOCK_MAC	0x00000008
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_NEW
+static void at91cap9_uhp_hw_init(void)
+{
+	/* Unlock USB OHCI, 3 2 0 1 sequence */
+#define MP_OHCI_KEY0	0x896c11ca
+#define MP_OHCI_KEY1	0x68ebca21
+#define MP_OHCI_KEY2	0x4823efbc
+#define MP_OHCI_KEY3	0x8651aae4
+#define UNLOCK_OHCI	0x00000010
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91CAP9ADK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91cap9_serial_hw_init();
+	at91cap9_nor_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91cap9_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91cap9_spi_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91cap9_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91cap9_uhp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif

board/atmel/at91cap9adk/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x73000000

board/atmel/at91cap9adk/led.c

@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91CAP9.h>
+
+#define	RED_LED		AT91C_PIO_PC29	/* this is the power led */
+#define	GREEN_LED	AT91C_PIO_PA10	/* this is the user1 led */
+#define	YELLOW_LED	AT91C_PIO_PA11	/* this is the user1 led */
+
+void red_LED_on(void)
+{
+	AT91C_BASE_PIOC->PIO_SODR = RED_LED;
+}
+
+void red_LED_off(void)
+{
+	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+}
+
+void green_LED_on(void)
+{
+	AT91C_BASE_PIOA->PIO_CODR = GREEN_LED;
+}
+
+void green_LED_off(void)
+{
+	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED;
+}
+
+void yellow_LED_on(void)
+{
+	AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED;
+}
+
+void yellow_LED_off(void)
+{
+	AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED;
+}
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+
+	/* Disable peripherals on LEDs */
+	AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED;
+	/* Enable pins as outputs */
+	AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED;
+	/* Turn all LEDs OFF */
+	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED;
+
+	/* Disable peripherals on LEDs */
+	AT91C_BASE_PIOC->PIO_PER = RED_LED;
+	/* Enable pins as outputs */
+	AT91C_BASE_PIOC->PIO_OER = RED_LED;
+	/* Turn all LEDs OFF */
+	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+}

board/atmel/at91cap9adk/nand.c

@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_CMD_NAND
+
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+
+static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		IO_ADDR_W |= MASK_CLE;
+		break;
+	case NAND_CTL_SETALE:
+		IO_ADDR_W |= MASK_ALE;
+		break;
+	case NAND_CTL_CLRNCE:
+		AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
+		break;
+	case NAND_CTL_SETNCE:
+		AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
+		break;
+	}
+	this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = at91cap9adk_nand_hwcontrol;
+	nand->chip_delay = 20;
+
+	return 0;
+}
+#endif

board/atmel/at91cap9adk/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/atum8548/atum8548.c

@@ -30,7 +30,7 @@
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -39,7 +39,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
 long int fixed_sdram(void);
 
 int board_early_init_f (void)

board/cm5200/fwupdate.h

@@ -39,7 +39,7 @@
 #define FW_DIR		"nx-fw"
 #define RESCUE_IMAGE	"nxrs.img"
 #define LOAD_ADDR	0x400000
-#define RS_BOOTARGS	"ramdisk=8192K"
+#define RS_BOOTARGS	"ramdisk_size=8192K"
 
 /* Main function for fwupdate */
 void cm5200_fwupdate(void);

board/esd/common/fpga.c

@@ -37,7 +37,7 @@
 #define MAX_ONES               226
 
 #ifdef CFG_FPGA_PRG
-# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_PRG              CFG_FPGA_PRG	/* FPGA program pin (ppc output) */
 # define FPGA_CLK              CFG_FPGA_CLK	/* FPGA clk pin (ppc output)    */
 # define FPGA_DATA             CFG_FPGA_DATA	/* FPGA data pin (ppc output)  */
 # define FPGA_DONE             CFG_FPGA_DONE	/* FPGA done pin (ppc input)   */
@@ -92,129 +92,133 @@
 #endif
 
 
-static int fpga_boot(unsigned char *fpgadata, int size)
+static int fpga_boot (const unsigned char *fpgadata, int size)
 {
-  int i,index,len;
+	int i, index, len;
 	int count;
+	unsigned char b;
+
 #ifdef CFG_FPGA_SPARTAN2
 	int j;
 #else
-  unsigned char b;
 	int bit;
 #endif
 
 	/* display infos on fpgaimage */
 	index = 15;
-  for (i=0; i<4; i++)
-    {
+	for (i = 0; i < 4; i++) {
 		len = fpgadata[index];
-      DBG("FPGA: %s\n", &(fpgadata[index+1]));
-      index += len+3;
+		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+		index += len + 3;
 	}
 
 #ifdef CFG_FPGA_SPARTAN2
 	/* search for preamble 0xFFFFFFFF */
-  while (1)
-    {
-      if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
-	  (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
 			break;	/* preamble found */
 		else
 			index++;
 	}
 #else
 	/* search for preamble 0xFF2X */
-  for (index = 0; index < size-1 ; index++)
-    {
-      if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
 			break;
 	}
 	index += 2;
 #endif
 
-  DBG("FPGA: configdata starts at position 0x%x\n",index);
-  DBG("FPGA: length of fpga-data %d\n", size-index);
+	DBG ("FPGA: configdata starts at position 0x%x\n", index);
+	DBG ("FPGA: length of fpga-data %d\n", size - index);
 
 	/*
 	 * Setup port pins for fpga programming
 	 */
 #ifndef CONFIG_M5249
-  out32(GPIO0_ODR, 0x00000000);                                      /* no open drain pins */
-  out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
+	out32 (GPIO0_ODR, 0x00000000);	/* no open drain pins */
+	out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* setup for output */
 #endif
-  SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);            /* set pins to high */
+	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set pins to high */
 
-  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
 
 	/*
 	 * Init fpga by asserting and deasserting PROGRAM*
 	 */
-  SET_FPGA(FPGA_PRG_LOW  | FPGA_CLK_HIGH | FPGA_DATA_HIGH);             /* set prog active */
+	SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog active */
 
 	/* Wait for FPGA init line low */
 	count = 0;
-  while (FPGA_INIT_STATE)
-    {
-      udelay(1000); /* wait 1ms */
+	while (FPGA_INIT_STATE) {
+		udelay (1000);	/* wait 1ms */
 		/* Check for timeout - 100us max, so use 3ms */
-      if (count++ > 3)
-	{
-	  DBG("FPGA: Booting failed!\n");
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
 			return ERROR_FPGA_PRG_INIT_LOW;
 		}
 	}
 
-  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
 
 	/* deassert PROGRAM* */
-  SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);           /* set prog inactive */
+	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog inactive */
 
 	/* Wait for FPGA end of init period .  */
 	count = 0;
-  while (!(FPGA_INIT_STATE))
-    {
-      udelay(1000); /* wait 1ms */
+	while (!(FPGA_INIT_STATE)) {
+		udelay (1000);	/* wait 1ms */
 		/* Check for timeout */
-      if (count++ > 3)
-	{
-	  DBG("FPGA: Booting failed!\n");
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
 			return ERROR_FPGA_PRG_INIT_HIGH;
 		}
 	}
 
-  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
 
-  DBG("write configuration data into fpga\n");
+	DBG ("write configuration data into fpga\n");
 	/* write configuration-data into fpga... */
 
 #ifdef CFG_FPGA_SPARTAN2
 	/*
 	 * Load uncompressed image into fpga
 	 */
-  for (i=index; i<size; i++)
-    {
-      for (j=0; j<8; j++)
-	{
-	  if ((fpgadata[i] & 0x80) == 0x80)
-	    {
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			if ((b & 0x80) == 0x80) {
 				FPGA_WRITE_1;
-	    }
-	  else
-	    {
+			} else {
 				FPGA_WRITE_0;
 			}
-	  fpgadata[i] <<= 1;
+			b <<= 1;
 		}
 	}
 #else
 	/* send 0xff 0x20 */
-  FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
-  FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
-  FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
-  FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
 
 	/*
 	 ** Bit_DeCompression
@@ -224,41 +228,30 @@ static int fpga_boot(unsigned char *fpgadata, int size)
 	 **        255                        :                   '1'
 	 */
 
-  for (i=index; i<size; i++)
-    {
+	for (i = index; i < size; i++) {
 		b = fpgadata[i];
-      if ((b >= 1) && (b <= MAX_ONES))
-	{
-	  for(bit=0; bit<b; bit++)
-	    {
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
 				FPGA_WRITE_1;
 			}
 			FPGA_WRITE_0;
-	}
-      else if (b == (MAX_ONES+1))
-	{
-	  for(bit=1; bit<b; bit++)
-	    {
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
 				FPGA_WRITE_1;
 			}
-	}
-      else if ((b >= (MAX_ONES+2)) && (b <= 254))
-	{
-	  for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
-	    {
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
 				FPGA_WRITE_0;
 			}
 			FPGA_WRITE_1;
-	}
-      else if (b == 255)
-	{
+		} else if (b == 255) {
 			FPGA_WRITE_1;
 		}
 	}
 #endif
 
-  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
 
 	/*
 	 * Check if fpga's DONE signal - correctly booted ?
@@ -266,17 +259,15 @@ static int fpga_boot(unsigned char *fpgadata, int size)
 
 	/* Wait for FPGA end of programming period .  */
 	count = 0;
-  while (!(FPGA_DONE_STATE))
-    {
-      udelay(1000); /* wait 1ms */
+	while (!(FPGA_DONE_STATE)) {
+		udelay (1000);	/* wait 1ms */
 		/* Check for timeout */
-      if (count++ > 3)
-	{
-	  DBG("FPGA: Booting failed!\n");
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
 			return ERROR_FPGA_PRG_DONE;
 		}
 	}
 
-  DBG("FPGA: Booting successful!\n");
+	DBG ("FPGA: Booting successful!\n");
 	return 0;
 }

board/freescale/mpc8323erdb/mpc8323erdb.c

@@ -13,18 +13,13 @@
 #include <ioports.h>
 #include <mpc83xx.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 #include <command.h>
 #include <libfdt.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
-#if defined(CONFIG_SPD_EEPROM)
-#include <spd_sdram.h>
-#else
 #include <asm/mmu.h>
-#endif
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* UCC3 */

board/freescale/mpc832xemds/mpc832xemds.c

@@ -16,17 +16,12 @@
 #include <ioports.h>
 #include <mpc83xx.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 #include <command.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
-#if defined(CONFIG_SPD_EEPROM)
-#include <spd_sdram.h>
-#else
 #include <asm/mmu.h>
-#endif
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif

board/freescale/mpc8349emds/mpc8349emds.c

@@ -28,11 +28,9 @@
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
 #include <spi.h>
-#include <spd.h>
 #include <miiphy.h>
-#if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
-#endif
+
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif

board/freescale/mpc8349itx/mpc8349itx.c

@@ -24,19 +24,13 @@
 #include <ioports.h>
 #include <mpc83xx.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
-
 #ifdef CONFIG_PCI
 #include <asm/mpc8349_pci.h>
 #include <pci.h>
 #endif
-
-#ifdef CONFIG_SPD_EEPROM
 #include <spd_sdram.h>
-#else
 #include <asm/mmu.h>
-#endif
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif

board/freescale/mpc8360emds/mpc8360emds.c

@@ -15,16 +15,12 @@
 #include <ioports.h>
 #include <mpc83xx.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
-#if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
-#else
 #include <asm/mmu.h>
-#endif
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif

board/freescale/mpc8360erdk/mpc8360erdk.c

@@ -18,7 +18,6 @@
 #include <ioports.h>
 #include <mpc83xx.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 #include <asm/io.h>
 #include <asm/mmu.h>

board/freescale/mpc837xemds/mpc837xemds.c

@@ -12,10 +12,7 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <spd.h>
-#if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
-#endif
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif

board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -14,11 +14,8 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <spd.h>
 #include <asm/io.h>
-#if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
-#endif
 
 #if defined(CFG_DRAM_TEST)
 int

board/freescale/mpc8540ads/mpc8540ads.c

@@ -29,7 +29,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
@@ -37,8 +37,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 long int fixed_sdram(void);
@@ -73,7 +71,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 	puts("Initializing\n");
 

board/freescale/mpc8541cds/mpc8541cds.c

@@ -27,7 +27,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
@@ -39,8 +39,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 

board/freescale/mpc8544ds/mpc8544ds.c

@@ -27,7 +27,7 @@
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -38,8 +38,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void sdram_init(void);
 
 int board_early_init_f (void)

board/freescale/mpc8548cds/mpc8548cds.c

@@ -27,7 +27,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -42,8 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 

board/freescale/mpc8555cds/mpc8555cds.c

@@ -25,7 +25,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
@@ -37,8 +37,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 

board/freescale/mpc8560ads/mpc8560ads.c

@@ -30,7 +30,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -39,7 +39,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
 
 void local_bus_init(void);
 void sdram_init(void);
@@ -275,7 +274,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 	puts("Initializing\n");
 

board/freescale/mpc8568mds/mpc8568mds.c

@@ -27,7 +27,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <i2c.h>
 #include <ioports.h>
 #include <libfdt.h>
@@ -102,8 +102,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -27,10 +27,10 @@
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <i2c.h>
-#include <spd.h>
 #include <asm/io.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <spd_sdram.h>
 
 #include "../common/pixis.h"
 
@@ -38,10 +38,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
 void sdram_init(void);
 long int fixed_sdram(void);
 void mpc8610hpcd_diu_init(void);
@@ -280,13 +276,14 @@ void pci_init_board(void)
 	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+	uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
+		>> MPC8610_PORDEVSR_IO_SEL_SHIFT;
+	uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
+		>> MPC8610_PORBMSR_HA_SHIFT;
 
 	printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 		devdisr, io_sel, host_agent);
 
-
 #ifdef CONFIG_PCIE1
  {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -25,7 +25,7 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <asm/io.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -36,10 +36,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
 void sdram_init(void);
 long int fixed_sdram(void);
 
@@ -206,7 +202,8 @@ void pci_init_board(void)
 	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 
 #ifdef CONFIG_PCI1
 {
@@ -214,7 +211,8 @@ void pci_init_board(void)
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 #ifdef DEBUG
-	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
+		>> MPC8641_PORBMSR_HA_SHIFT;
 	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 #endif
 	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
@@ -321,28 +319,16 @@ void pci_init_board(void)
 
 }
 
+
 #if defined(CONFIG_OF_BOARD_SETUP)
+
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
 	int node, tmp[2];
 	const char *path;
 
-	fdt_fixup_ethernet(blob, bd);
-
-	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-			     "timebase-frequency", bd->bi_busfreq / 4, 1);
-	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-			     "bus-frequency", bd->bi_busfreq, 1);
-	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-			     "clock-frequency", bd->bi_intfreq, 1);
-	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
-			     "bus-frequency", bd->bi_busfreq, 1);
-
-	do_fixup_by_compat_u32(blob, "ns16550",
-			       "clock-frequency", bd->bi_busfreq, 1);
-
-	fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
+	ft_cpu_setup(blob, bd);
 
 	node = fdt_path_offset(blob, "/aliases");
 	tmp[0] = 0;

board/m501sk/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS  := m501sk.o eeprom.o
+
+SOBJS  := memsetup.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/m501sk/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000

board/m501sk/eeprom.c

@@ -0,0 +1,102 @@
+/*
+ * Add by Alan Lu, 07-29-2005
+ * For ATMEL AT24C16 EEPROM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#ifdef CFG_EEPROM_AT24C16
+#undef DEBUG
+
+void eeprom_init(void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+}
+
+int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer,
+			unsigned cnt)
+{
+	int page, count = 0, i = 0;
+	page = offset / 0x100;
+	i = offset % 0x100;
+
+	while (count < cnt) {
+		if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+			return 1;
+		if (i > 0xff) {
+			page++;
+			i = 0;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ *   0x00000nxx for EEPROM address selectors and page number at n.
+ */
+int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
+			unsigned cnt)
+{
+	int page, i = 0, count = 0;
+
+	page = offset / 0x100;
+	i = offset % 0x100;
+
+	while (count < cnt) {
+		if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+			return 1;
+		if (i > 0xff) {
+			page++;
+			i = 0;
+		}
+	}
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SPI
+int eeprom_probe(unsigned dev_addr, unsigned offset)
+{
+	unsigned char chip;
+
+	/* Probe the chip address */
+#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
+	chip = offset >> 8; /* block number */
+#else
+	chip = offset >> 16; /* block number */
+#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+
+	chip |= dev_addr; /* insert device address */
+	return (i2c_probe(chip));
+}
+#endif
+#endif

board/m501sk/m501sk.c

@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2008
+ * Based on modifications by Alan Lu / Artila
+ * Author : Timo Tuunainen / Sysart
+			Kimmo Leppala / Sysart
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#include "m501sk.h"
+#include "net.h"
+
+#ifdef CONFIG_M501SK
+
+void m501sk_gpio_init(void)
+{
+	AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) |
+		1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
+		1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
+
+	AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) |
+		1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
+		1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
+
+	AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96);
+	AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96);
+	AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32);
+	AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32);
+	AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8);
+
+	/* Power OFF all USART's LEDs */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+	AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+	AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+}
+
+uchar m501sk_gpio_set(M501SK_PIO io)
+{
+	uchar status = 0xff;
+	switch (io) {
+	case M501SK_DEBUG_LED1:
+	case M501SK_DEBUG_LED2:
+	case M501SK_DEBUG_LED3:
+	case M501SK_DEBUG_LED4:
+	case M501SK_READY_LED:
+		AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96);
+		status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
+		break;
+	case M501SK_BUZZER:
+		AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32);
+		status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
+		break;
+	}
+	return status;
+}
+
+uchar m501sk_gpio_clear(M501SK_PIO io)
+{
+	uchar status = 0xff;
+	switch (io) {
+	case M501SK_DEBUG_LED1:
+	case M501SK_DEBUG_LED2:
+	case M501SK_DEBUG_LED3:
+	case M501SK_DEBUG_LED4:
+	case M501SK_READY_LED:
+		AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96);
+		status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
+		break;
+	case M501SK_BUZZER:
+		AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32);
+		status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
+		break;
+	}
+	return status;
+}
+
+void load_sernum_ethaddr(void)
+{
+	return;
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+	gd->bd->bi_arch_number = MACH_TYPE_M501;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	m501sk_gpio_init();
+
+	/* Do interrupt init here, because flash needs timers */
+	interrupt_init();
+	flash_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i = 0;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	for (i = 0; i < 500; i++) {
+		m501sk_gpio_clear(M501SK_DEBUG_LED3);
+		m501sk_gpio_clear(M501SK_BUZZER);
+		udelay(250);
+		m501sk_gpio_set(M501SK_DEBUG_LED3);
+		m501sk_gpio_set(M501SK_BUZZER);
+		udelay(80);
+	}
+	m501sk_gpio_clear(M501SK_BUZZER);
+	m501sk_gpio_clear(M501SK_DEBUG_LED3);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_CMD_NET)
+	eth_init(gd->bd);
+	eth_halt();
+#endif
+
+	/* Protect U-Boot, kernel & ramdisk memory addresses */
+	run_command("protect on 10000000 1041ffff", 0);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+/*
+ * Name:
+ *     at91rm9200_GetPhyInterface
+ * Description:
+ *     Initialise the interface functions to the PHY
+ * Arguments:
+ *     None
+ * Return value:
+ *     None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
+#endif /* CONFIG_M501SK */

board/m501sk/m501sk.h

@@ -0,0 +1,167 @@
+/*
+ * linux/include/asm-arm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __M501SK_H
+#define __M501SK_H
+
+#ifndef __ASSEMBLY__
+#include <asm-arm/arch-at91rm9200/AT91RM9200.h>
+#else
+#include <asm-arm/arch-at91rm9200/AT91RM9200_inc.h>
+#endif
+
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */
+#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */
+#define AT91C_PA5_TXD3 ((unsigned int) 1 <<  5) /* USART 3 TxD */
+#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */
+
+/* ========== Register definition for PIOD peripheral ========== */
+#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */
+#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */
+#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */
+#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */
+#define AT91C_PIOD_IMR  ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */
+#define AT91C_PIOD_IER  ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */
+#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */
+#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */
+#define AT91C_PIOD_PER  ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */
+#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */
+#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */
+#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */
+#define AT91C_PIOD_ISR  ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */
+#define AT91C_PIOD_IDR  ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */
+#define AT91C_PIOD_PDR  ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */
+#define AT91C_PIOD_ODR  ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */
+#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */
+#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */
+#define AT91C_PIOD_ASR  ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */
+#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */
+#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */
+#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */
+#define AT91C_PIOD_PSR  ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */
+#define AT91C_PIOD_OER  ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */
+#define AT91C_PIOD_OSR  ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */
+#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */
+#define AT91C_PIOD_BSR  ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */
+#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */
+#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */
+
+#define AT91C_PIO_PD0   ((unsigned int) 1 <<  0) /* Pin Controlled by PD0 */
+#define AT91C_PD0_ETX0  ((unsigned int) AT91C_PIO_PD0) /*  Enet MAC Tx Data 0*/
+#define AT91C_PIO_PD1   ((unsigned int) 1 <<  1) /* Pin Controlled by PD1 */
+#define AT91C_PD1_ETX1  ((unsigned int) AT91C_PIO_PD1) /*  Enet MAC Tx Data 1*/
+#define AT91C_PIO_PD10  ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */
+#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/
+#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */
+#define AT91C_PIO_PD11  ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */
+#define AT91C_PD11_     ((unsigned int) AT91C_PIO_PD11) /*   */
+#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */
+#define AT91C_PIO_PD12  ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */
+#define AT91C_PD12_     ((unsigned int) AT91C_PIO_PD12) /*   */
+#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */
+#define AT91C_PIO_PD13  ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */
+#define AT91C_PD13_     ((unsigned int) AT91C_PIO_PD13) /*   */
+#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */
+#define AT91C_PIO_PD14  ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */
+#define AT91C_PD14_     ((unsigned int) AT91C_PIO_PD14) /*   */
+#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */
+#define AT91C_PIO_PD15  ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */
+#define AT91C_PD15_TD0  ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */
+#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */
+#define AT91C_PIO_PD16  ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */
+#define AT91C_PD16_TD1  ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */
+#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */
+#define AT91C_PIO_PD17  ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */
+#define AT91C_PD17_TD2  ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */
+#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */
+#define AT91C_PIO_PD18  ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */
+#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /*  SPI Perip CS 1 */
+#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */
+#define AT91C_PIO_PD19  ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */
+#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /*  SPI Perip CS 2 */
+#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */
+#define AT91C_PIO_PD2   ((unsigned int) 1 <<  2) /* Pin Controlled by PD2 */
+#define AT91C_PD2_ETX2  ((unsigned int) AT91C_PIO_PD2) /*  Ethernet MAC TxD 2 */
+#define AT91C_PIO_PD20  ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */
+#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */
+#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */
+#define AT91C_PIO_PD21  ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */
+#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */
+#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */
+#define AT91C_PIO_PD22  ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */
+#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /*  Usart 0 RTS */
+#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */
+#define AT91C_PIO_PD23  ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */
+#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */
+#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */
+#define AT91C_PIO_PD24  ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */
+#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /*  USART 3 RTS */
+#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */
+#define AT91C_PIO_PD25  ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */
+#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */
+#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */
+#define AT91C_PIO_PD26  ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */
+#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */
+#define AT91C_PIO_PD27  ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */
+#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */
+#define AT91C_PIO_PD3   ((unsigned int) 1 <<  3) /* Pin Controlled by PD3 */
+#define AT91C_PD3_ETX3  ((unsigned int) AT91C_PIO_PD3) /*  Enet MAC TxD 3 */
+#define AT91C_PIO_PD4   ((unsigned int) 1 <<  4) /* Pin Controlled by PD4 */
+#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */
+#define AT91C_PIO_PD5   ((unsigned int) 1 <<  5) /* Pin Controlled by PD5 */
+#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /*  Enet MAC TxCE */
+#define AT91C_PIO_PD6   ((unsigned int) 1 <<  6) /* Pin Controlled by PD6 */
+#define AT91C_PD6_DTXD  ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */
+#define AT91C_PIO_PD7   ((unsigned int) 1 <<  7) /* Pin Controlled by PD7 */
+#define AT91C_PD7_PCK0  ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/
+#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */
+#define AT91C_PIO_PD8   ((unsigned int) 1 <<  8) /* Pin Controlled by PD8 */
+#define AT91C_PD8_PCK1  ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/
+#define AT91C_PD8_TCLK  ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */
+#define AT91C_PIO_PD9   ((unsigned int) 1 <<  9) /* Pin Controlled by PD9 */
+#define AT91C_PD9_PCK2  ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */
+#define AT91C_PD9_TPS0  ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */
+#define AT91C_PIO_PB6   ((unsigned int) 1 <<  6) /* Pin Controlled by PB6 */
+#define AT91C_PIO_PC5   ((unsigned int) 1 <<  5)
+#define AT91C_PIO_PC14  ((unsigned int) 1 <<  14) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PC15  ((unsigned int) 1 <<  15) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PA19  ((unsigned int) 1 <<  19) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB2   ((unsigned int) 1 <<  2) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB8   ((unsigned int) 1 <<  8)
+#define AT91C_PIO_PB9   ((unsigned int) 1 <<  9)
+#define AT91C_PIO_PB10  ((unsigned int) 1 <<  10)
+#define AT91C_PIO_PB11  ((unsigned int) 1 <<  11)
+#define AT91C_PIO_PB17  ((unsigned int) 1 <<  17)
+#define AT91C_PIO_PB28  ((unsigned int) 1 <<  28)
+#define AT91C_PIO_PB29  ((unsigned int) 1 <<  29)
+
+typedef enum {
+	M501SK_BUZZER = 38,
+	M501SK_DEBUG_LED1 = 96,
+	M501SK_DEBUG_LED2,
+	M501SK_DEBUG_LED3,
+	M501SK_DEBUG_LED4,
+	M501SK_READY_LED = 102,
+} M501SK_PIO;
+
+void m501sk_gpio_init(void);
+uchar m501sk_gpio_set(M501SK_PIO io);
+uchar m501sk_gpio_clear(M501SK_PIO io);
+
+#endif

board/m501sk/memsetup.S

@@ -0,0 +1,200 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *	          Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_BOOTBINFUNC
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP 0xFFFFFF50
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER 0xFFFFFF54
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR 0xFFFFFF04
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR 0xFFFFFF08
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR 0xFFFFFF64
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR 0xFFFFFF70
+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR 0xFFFFFC2C
+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR 0xFFFFFC30
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define MCKR_VAL	0x00000202
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+_TEXT_BASE:
+	.word   TEXT_BASE
+
+.globl lowlevelinit
+lowlevelinit:
+	/* memory control configuration */
+	/* this isn't very elegant, but  what the heck */
+	ldr     r0, =SMRDATA
+	ldr     r1, _TEXT_BASE
+	sub     r0, r0, r1
+	add     r2, r0, #80
+0:
+	/* the address */
+	ldr     r1, [r0], #4
+	/* the value */
+	ldr     r3, [r0], #4
+	str     r3, [r1]
+	cmp     r2, r0
+	bne     0b
+	/* delay - this is all done by guess */
+	ldr     r0, =0x00010000
+1:
+	subs    r0, r0, #1
+	bhi     1b
+	ldr     r0, =SMRDATA1
+	ldr     r1, _TEXT_BASE
+	sub     r0, r0, r1
+	add     r2, r0, #176
+2:
+	/* the address */
+	ldr     r1, [r0], #4
+	/* the value */
+	ldr     r3, [r0], #4
+	str     r3, [r1]
+	cmp     r2, r0
+	bne     2b
+
+	/* everything is fine now */
+	mov     pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word MC_PUIA
+	.word MC_PUIA_VAL
+	.word MC_PUP
+	.word MC_PUP_VAL
+	.word MC_PUER
+	.word MC_PUER_VAL
+	.word MC_ASR
+	.word MC_ASR_VAL
+	.word MC_AASR
+	.word MC_AASR_VAL
+	.word EBI_CFGR
+	.word EBI_CFGR_VAL
+	.word SMC2_CSR
+	.word SMC2_CSR_VAL
+	.word PLLAR
+	.word PLLAR_VAL
+	.word PLLBR
+	.word PLLBR_VAL
+	.word MCKR
+	.word MCKR_VAL
+	/* SMRDATA is 80 bytes long */
+	/* here there's a delay of 100 */
+SMRDATA1:
+	.word PIOC_ASR
+	.word PIOC_ASR_VAL
+	.word PIOC_BSR
+	.word PIOC_BSR_VAL
+	.word PIOC_PDR
+	.word PIOC_PDR_VAL
+	.word EBI_CSA
+	.word EBI_CSA_VAL
+	.word SDRC_CR
+	.word SDRC_CR_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL1
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL2
+	.word SDRAM1
+	.word SDRAM_VAL
+	.word SDRC_TR
+	.word SDRC_TR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL3
+	.word SDRAM
+	.word SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */

board/m501sk/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	 cpu/arm920t/start.o   (.text)
+	 *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mgcoge/mgcoge.c

@@ -278,6 +278,17 @@ int checkboard(void)
 	return 0;
 }
 
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+	/* setup the UPIOx */
+	*(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
+	*(char *)(CFG_PIGGY_BASE + 0x03) = 0x15;
+	return 0;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 /*
  * update "memory" property in the blob
@@ -286,7 +297,7 @@ void ft_blob_update(void *blob, bd_t *bd)
 {
 	int ret, nodeoffset = 0;
 	ulong memory_data[2] = {0};
-	ulong flash_data[4] = {0};
+	ulong flash_data[8] = {0};
 
 	memory_data[0] = cpu_to_be32(bd->bi_memstart);
 	memory_data[1] = cpu_to_be32(bd->bi_memsize);
@@ -304,9 +315,13 @@ void ft_blob_update(void *blob, bd_t *bd)
 		printf("ft_blob_update(): cannot find /memory node "
 		"err:%s\n", fdt_strerror(nodeoffset));
 	}
-	/* update Flash size */
-	flash_data[2] = cpu_to_be32(bd->bi_flashstart);
-	flash_data[3] = cpu_to_be32(bd->bi_flashsize);
+	/* update Flash addr, size */
+	flash_data[2] = cpu_to_be32(CFG_FLASH_BASE);
+	flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE);
+	flash_data[4] = cpu_to_be32(1);
+	flash_data[5] = cpu_to_be32(0);
+	flash_data[6] = cpu_to_be32(CFG_FLASH_BASE_1);
+	flash_data[7] = cpu_to_be32(CFG_FLASH_SIZE_1);
 	nodeoffset = fdt_path_offset (blob, "/localbus");
 	if (nodeoffset >= 0) {
 		ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
@@ -331,7 +346,7 @@ void ft_blob_update(void *blob, bd_t *bd)
 	}
 	else {
 		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /localbus node "
+		printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
 		"err:%s\n", fdt_strerror(nodeoffset));
 	}
 

board/mgsuvd/mgsuvd.c

@@ -134,6 +134,17 @@ long int initdram (int board_type)
 	return (size);
 }
 
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+	/* setup the UPIOx */
+	*(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
+	*(char *)(CFG_PIGGY_BASE + 0x03) = 0x35;
+	return 0;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 /*
  * update "memory" property in the blob
@@ -179,31 +190,31 @@ void ft_blob_update(void *blob, bd_t *bd)
 	}
 	/* BRG */
 	brg_data[0] = cpu_to_be32(bd->bi_busfreq);
-	nodeoffset = fdt_path_offset (blob, "/soc866/cpm");
+	nodeoffset = fdt_path_offset (blob, "/soc/cpm");
 	if (nodeoffset >= 0) {
 		ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
 					sizeof(brg_data));
 	if (ret < 0)
-		printf("ft_blob_update): cannot set /soc866/cpm/brg-frequency "
+		printf("ft_blob_update): cannot set /soc/cpm/brg-frequency "
 			"property err:%s\n", fdt_strerror(ret));
 	}
 	else {
 		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /localbus node "
+		printf("ft_blob_update(): cannot find /soc/cpm node "
 		"err:%s\n", fdt_strerror(nodeoffset));
 	}
 	/* MAC Adresse */
-	nodeoffset = fdt_path_offset (blob, "/soc866/cpm/scc");
+	nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
 	if (nodeoffset >= 0) {
 		ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
 					sizeof(uchar) * 6);
 	if (ret < 0)
-		printf("ft_blob_update): cannot set /soc866/cpm/scc/mac-address "
+		printf("ft_blob_update): cannot set /soc/cpm/scc/mac-address "
 			"property err:%s\n", fdt_strerror(ret));
 	}
 	else {
 		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /localbus node "
+		printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
 		"err:%s\n", fdt_strerror(nodeoffset));
 	}
 }

board/mpc8540eval/mpc8540eval.c

@@ -26,9 +26,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
-#include <spd.h>
-
-extern long int spd_sdram (void);
+#include <spd_sdram.h>
 
 long int fixed_sdram (void);
 
@@ -66,7 +64,7 @@ int checkboard (void)
 long int initdram (int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
+
 #if !defined(CONFIG_RAM_AS_FLASH)
 	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;

board/mx1fs2/flash.c

@@ -173,7 +173,7 @@ flash_print_info(flash_info_t * info)
 	int i;
 	uchar *boottype;
 	uchar *bootletter;
-	uchar *fmt;
+	char *fmt;
 	uchar botbootletter[] = "B";
 	uchar topbootletter[] = "T";
 	uchar botboottype[] = "bottom boot sector";

board/mx1fs2/mx1fs2.c

@@ -48,7 +48,7 @@ static void logo_init(void)
 	imx_gpio_mode(PD14_PF_FLM_VSYNC);
 	imx_gpio_mode(PD13_PF_LP_HSYNC);
 	imx_gpio_mode(PD6_PF_LSCLK);
-	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
+	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR);
 	imx_gpio_mode(PD11_PF_CONTRAST);
 	imx_gpio_mode(PD10_PF_SPL_SPR);
 

board/netstal/common/fixed_sdram.c

@@ -44,7 +44,7 @@ void show_sdram_registers(void)
 }
 #endif
 
-long int fixed_hcu4_sdram (unsigned int dram_size)
+long int init_ppc405_sdram(unsigned int dram_size)
 {
 #ifdef DEBUG
 	printf(__FUNCTION__);

board/netstal/common/hcu_flash.c

@@ -21,18 +21,6 @@
  * MA 02111-1307 USA
  */
 
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- *
- * Modified 6/6/2007
- * Added isync
- * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com
- *
- */
-
 #include <common.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
@@ -387,7 +375,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
 
-#if 0
 	/*
 	 * We wait for the last triggered sector
 	 */
@@ -396,7 +383,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	wait_for_DQ7 (info, l_sect);
 
 DONE:
-#endif
 	/* reset to read mode */
 	addr = (FLASH_WORD_SIZE *) info->start[0];
 	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */

board/netstal/common/nm.h

@@ -27,8 +27,7 @@ extern void set_params_for_sw_install(int install_requested, char *board_name );
 extern void common_misc_init_r(void);
 
 enum {
-	/* HW_GENERATION_HCU1 is no longer supported */
-	HW_GENERATION_HCU2  = 0x10,
+	/* HW_GENERATION_HCU1/2 is no longer supported */
 	HW_GENERATION_HCU3  = 0x10,
 	HW_GENERATION_HCU4  = 0x20,
 	HW_GENERATION_HCU5  = 0x30,
@@ -36,3 +35,10 @@ enum {
 	HW_GENERATION_MCU20 = 0x0a,
 	HW_GENERATION_MCU25 = 0x09,
 };
+
+#ifdef CONFIG_405GP
+#if defined(DEBUG)
+void show_sdram_registers(void);
+#endif
+long int init_ppc405_sdram(unsigned int dram_size);
+#endif

board/netstal/common/nm_bsp.c

@@ -29,8 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 typedef struct {u8	id;	char *name;} generation_info;
 
-generation_info generations[7] = {
-	{HW_GENERATION_HCU2,	"HCU2"},
+generation_info generations[6] = {
 	{HW_GENERATION_HCU3,	"HCU3"},
 	{HW_GENERATION_HCU4,	"HCU4"},
 	{HW_GENERATION_HCU5,	"HCU5"},

board/netstal/hcu4/hcu4.c

@@ -1,5 +1,5 @@
 /*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
  *    Niklaus Giger (Niklaus.Giger@netstal.com)
  *
  *    This source code is free software; you can redistribute it
@@ -28,17 +28,10 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define HCU_MACH_VERSIONS_REGISTER	(0x7C000000 + 0xF00000)
-#define SYS_SLOT_ADDRESS		(0x7C000000 + 0x400000)
-#define HCU3_DIGITAL_IO_REGISTER	(0x7C000000 + 0x500000)
+#define HCU_SLOT_ADDRESS		(0x7C000000 + 0x400000)
+#define HCU_DIGITAL_IO_REGISTER		(0x7C000000 + 0x500000)
 #define HCU_SW_INSTALL_REQUESTED	0x10
 
-#undef DEBUG
-
-#if defined(DEBUG)
-void show_sdram_registers(void);
-#endif
-long int fixed_hcu4_sdram (unsigned int dram_size);
-
 /*
  * This function is run very early, out of flash, and before devices are
  * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
@@ -49,17 +42,12 @@ long int fixed_hcu4_sdram (unsigned int dram_size);
  * anything, not even stack. So be careful.
  */
 
-#define CPC0_CR0	0xb1	/* Chip control register 0 */
-#define CPC0_CR1        0xb2	/* Chip control register 1 */
 /* Attention: If you want 1 microsecs times from the external oscillator
- * use  0x00804051. But this causes problems with u-boot and linux!
+ * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
+ * 0x00804051 causes problems with u-boot and linux!
  */
 #define CPC0_CR0_VALUE	0x0030103c
 #define CPC0_CR1_VALUE	0x00004051
-#define CPC0_ECR	0xaa	/* Edge condition register */
-#define EBC0_CFG	0x23	/* External Peripheral Control Register */
-#define CPC0_EIRR	0xb6	/* External Interrupt Register */
-
 
 int board_early_init_f (void)
 {
@@ -70,16 +58,16 @@ int board_early_init_f (void)
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr (uicer, 0x00000000); /* disable all ints */
-	mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr (uictr, 0x00000000); /* set int trigger levels */
-	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(uicer, 0x00000000); /* disable all ints */
+	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
+	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
+	mtdcr(uictr, 0x00000000); /* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
 
 	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
 	mtdcr(CPC0_ECR, 0x60606000);
-	mtdcr(CPC0_EIRR, 0x7c000000);
+	mtdcr(CPC0_EIRR, 0x7C000000);
 
 	return 0;
 }
@@ -93,18 +81,19 @@ int board_pre_init (void)
 
 int sys_install_requested(void)
 {
-	u16 *ioValuePtr = (u16 *)HCU3_DIGITAL_IO_REGISTER;
-	return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
+	u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER);
+	return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0;
 }
 
 int checkboard (void)
 {
-	u16 *boardVersReg = (u16 *)HCU_MACH_VERSIONS_REGISTER;
-	u16 generation = in_be16(boardVersReg) & 0xf0;
-	u16 index      = in_be16(boardVersReg) & 0x0f;
+	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
+	u16 generation = boardVersReg & 0xf0;
+	u16 index      = boardVersReg & 0x0f;
+
+	/* Cannot be done in board_early_init */
+	mtdcr(cntrl0,  CPC0_CR0_VALUE);
 
-	/* Cannot be done, in board_early_init */
-	mtdcr(CPC0_CR0,  CPC0_CR0_VALUE);
 	/* Force /RTS to active. The board it not wired quite
 	 *  correctly to use cts/rtc flow control, so just force the
 	 *  /RST active and forget about it.
@@ -145,8 +134,8 @@ void sdram_init(void)
  */
 u32 hcu_get_slot(void)
 {
-	u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
-	return in_be16(slot) & 0x7f;
+	u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS);
+	return slot & 0x7f;
 }
 
 /*
@@ -154,12 +143,12 @@ u32 hcu_get_slot(void)
  */
 u32 get_serial_number(void)
 {
-	u32 *serial = (u32 *)CFG_FLASH_BASE;
+	u32 serial = in_be32((u32 *)CFG_FLASH_BASE);
 
-	if (in_be32(serial) == 0xffffffff)
+	if (serial == 0xffffffff)
 		return 0;
 
-	return in_be32(serial);
+	return serial;
 }
 
 
@@ -177,12 +166,15 @@ int misc_init_r(void)
 long int initdram(int board_type)
 {
 	long dram_size = 0;
-	u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
-	u16 generation = in_be16(boardVersReg) & 0xf0;
-	if (generation == HW_GENERATION_HCU3)
-		dram_size = 32*1024*1024;
-	else dram_size = 64*1024*1024;
-	fixed_hcu4_sdram(dram_size);
+	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
+	u16 generation = boardVersReg & 0xf0;
+	u16 index      = boardVersReg & 0x0f;
+
+	if (generation == HW_GENERATION_HCU3 && index < 0xf)
+		dram_size = 32 << 20;	/* 32 MB - RAM */
+	else
+		dram_size = 64 << 20;	/* 64 MB - RAM */
+	init_ppc405_sdram(dram_size);
 
 #ifdef DEBUG
 	show_sdram_registers();

board/netstal/hcu5/hcu5.c

@@ -309,15 +309,13 @@ int misc_init_r(void)
 	 */
 	if (mfspr(dbcr0) & 0x80000000) {
 		/* External debugger alive
-		 * enable trace facilty for Lauterback
-		 * CCR0[DAPUIB]=0 	Enable broadcast of instruction data
-		 *			to auxiliary processor interface
+		 * enable trace facilty for Lauterbach
 		 * CCR0[DTB]=0 		Enable broadcast of trace information
 		 * SDR0_PFC0[TRE] 	Trace signals are enabled instead of
 		 *			GPIO49-63
 		 */
-		mtspr(ccr0, mfspr(ccr0)  &~ 0x00108000);
-		mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100);
+	        mtspr(ccr0, mfspr(ccr0)  &~ (CCR0_DTB));
+		mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
 	}
 	return 0;
 }

board/netstal/hcu5/sdram.c

@@ -165,19 +165,25 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 	u32 val;
 	char str[] = "ECC generation -";
 #if defined(CONFIG_PRAM)
-	u32 *magic;
+	u32 *magicPtr;
+	u32 magic;
 
-	/* Check whether vxWorks is using EDR logging, if yes zero */
-	/* also PostMortem and user reserved memory */
-	magic = (u32 *)in_be32((u32 *)(start_address + num_bytes -
-				       (CONFIG_PRAM*1024) + sizeof(u32)));
-
-	debug("\n%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__,
-	       CONFIG_PRAM,
-	       start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),
-	       magic, in_be32(magic));
-	if (in_be32(magic) == 0xbeefbabe)
+	if ((mfspr(dbcr0) & 0x80000000) == 0) {
+		/* only if no external debugger is alive!
+		 * Check whether vxWorks is using EDR logging, if yes zero
+		 * also PostMortem and user reserved memory
+		 */
+		magicPtr = (u32 *)(start_address + num_bytes -
+				(CONFIG_PRAM*1024) + sizeof(u32));
+		magic = in_be32(magicPtr);
+		debug("%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
+		      __FUNCTION__, CONFIG_PRAM,
+		      magicPtr, magic);
+		if (magic == 0xbeefbabe) {
+			printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
 			num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
+		}
+	}
 #endif
 
 	sync();

board/netstar/nand.c

@@ -45,23 +45,12 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 	this->IO_ADDR_W = (void *) IO_ADDR_W;
 }
 
-/*
- *	chip R/B detection
- */
-/***
-static int netstar_nand_ready(struct mtd_info *mtd)
-{
-	return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
-}
-***/
-
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->hwcontrol = netstar_nand_hwcontrol;
-/*	nand->dev_ready = netstar_nand_ready; */
-	nand->chip_delay = 18;
+	nand->chip_delay = 400;
 	return 0;
 }
 #endif

board/pm854/pm854.c

@@ -29,14 +29,12 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
-#include <spd.h>
+#include <spd_sdram.h>
 
 #if defined(CONFIG_DDR_ECC)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 long int fixed_sdram(void);
@@ -77,7 +75,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 	puts("Initializing\n");
 

board/pm856/pm856.c

@@ -30,15 +30,13 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 
 #if defined(CONFIG_DDR_ECC)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 long int fixed_sdram(void);
 
@@ -231,7 +229,7 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
+
 
 	puts("Initializing\n");
 

board/qemu-mips/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o
+COBJS	= $(BOARD).o
 SOBJS	= lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

board/sbc8349/sbc8349.c

@@ -30,11 +30,8 @@
 #include <mpc83xx.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
-#endif
+#include <miiphy.h>
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif

board/sbc8548/sbc8548.c

@@ -30,7 +30,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -41,8 +41,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 void sdram_init(void);
 long int fixed_sdram (void);
@@ -56,9 +54,10 @@ int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	volatile u_char *rev= (void *)CFG_BD_REV;
 
 	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
-			(volatile)(*(u_char *)CFG_BD_REV) >> 4);
+			(*rev) >> 4);
 
 	/*
 	 * Initialize local bus.
@@ -533,12 +532,12 @@ void
 ft_pci_setup(void *blob, bd_t *bd)
 {
 	int node, tmp[2];
-	const char *path;
 
 	node = fdt_path_offset(blob, "/aliases");
 	tmp[0] = 0;
 	if (node >= 0) {
 #ifdef CONFIG_PCI1
+		const char *path;
 		path = fdt_getprop(blob, node, "pci0", NULL);
 		if (path) {
 			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
@@ -546,6 +545,7 @@ ft_pci_setup(void *blob, bd_t *bd)
 		}
 #endif
 #ifdef CONFIG_PCIE1
+		const char *path;
 		path = fdt_getprop(blob, node, "pci1", NULL);
 		if (path) {
 			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;

board/sbc8560/sbc8560.c

@@ -27,13 +27,11 @@
  */
 
 
-extern long int spd_sdram (void);
-
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 
 long int fixed_sdram (void);
@@ -262,7 +260,7 @@ int checkboard (void)
 long int initdram (int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
+
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
 	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

board/sbc8641d/sbc8641d.c

@@ -34,21 +34,14 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup (void *blob, bd_t * bd);
-#endif
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc (unsigned int dram_size);
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
 void sdram_init (void);
 long int fixed_sdram (void);
 
@@ -233,7 +226,8 @@ void pci_init_board(void)
 	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 
 #ifdef CONFIG_PCI1
 {
@@ -241,7 +235,8 @@ void pci_init_board(void)
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 #ifdef DEBUG
-	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
+		>> MPC8641_PORBMSR_HA_SHIFT;
 	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 #endif
 	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
@@ -341,18 +336,34 @@ void pci_init_board(void)
 
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t * bd)
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup (void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
-	ft_cpu_setup (blob, bd);
+	ft_cpu_setup(blob, bd);
 
-	p = ft_get_prop (blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32 (bd->bi_memstart);
-		*p = cpu_to_be32 (bd->bi_memsize);
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
 	}
 }
 #endif

board/scb9328/flash.c

@@ -44,6 +44,7 @@
 
 #if ( SCB9328_FLASH_BUS_WIDTH == 1 )
 #  define FLASH_BUS vu_char
+#  define FLASH_BUS_RET u_char
 #  if ( SCB9328_FLASH_INTERLEAVE == 1 )
 #    define FLASH_CMD( x ) x
 #  else
@@ -53,6 +54,7 @@
 
 #elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
 #  define FLASH_BUS vu_short
+#  define FLASH_BUS_RET u_short
 #  if ( SCB9328_FLASH_INTERLEAVE == 1 )
 #    define FLASH_CMD( x ) x
 #  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
@@ -64,6 +66,7 @@
 
 #elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
 #  define FLASH_BUS vu_long
+#  define FLASH_BUS_RET u_long
 #  if ( SCB9328_FLASH_INTERLEAVE == 1 )
 #    define FLASH_CMD( x ) x
 #  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
@@ -81,7 +84,7 @@
 
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 
-static FLASH_BUS flash_status_reg (void)
+static FLASH_BUS_RET flash_status_reg (void)
 {
 
 	FLASH_BUS *addr = (FLASH_BUS *) 0;

board/siemens/SCM/scm.h

@@ -29,7 +29,7 @@
 /*----------------*/
 
 /* Message */
-typedef struct can_msg {
+struct can_msg {
     uchar	ctrl_0;
     uchar	ctrl_1;
     uchar	arbit_0;
@@ -38,7 +38,9 @@ typedef struct can_msg {
     uchar	arbit_3;
     uchar	config;
     uchar	data[8];
-} can_msg_t;
+} __attribute__ ((packed));
+
+typedef struct can_msg can_msg_t;
 
 /* CAN Register */
 typedef struct can_reg {
@@ -50,35 +52,35 @@ typedef struct can_reg {
     ushort	gbl_mask_std;
     uint	gbl_mask_extd;
     uint	msg15_mask;
-    can_msg_t	msg1 __attribute__ ((packed));
+    can_msg_t	msg1;
     uchar	clkout;
-    can_msg_t	msg2 __attribute__ ((packed));
+    can_msg_t	msg2;
     uchar	bus_config;
-    can_msg_t	msg3 __attribute__ ((packed));
+    can_msg_t	msg3;
     uchar	bit_timing_0;
-    can_msg_t	msg4 __attribute__ ((packed));
+    can_msg_t	msg4;
     uchar	bit_timing_1;
-    can_msg_t	msg5 __attribute__ ((packed));
+    can_msg_t	msg5;
     uchar	interrupt;
-    can_msg_t	msg6 __attribute__ ((packed));
+    can_msg_t	msg6;
     uchar	resv1;
-    can_msg_t	msg7 __attribute__ ((packed));
+    can_msg_t	msg7;
     uchar	resv2;
-    can_msg_t	msg8 __attribute__ ((packed));
+    can_msg_t	msg8;
     uchar	resv3;
-    can_msg_t	msg9 __attribute__ ((packed));
+    can_msg_t	msg9;
     uchar	p1conf;
-    can_msg_t	msg10 __attribute__ ((packed));
+    can_msg_t	msg10;
     uchar	p2conf;
-    can_msg_t	msg11 __attribute__ ((packed));
+    can_msg_t	msg11;
     uchar	p1in;
-    can_msg_t	msg12 __attribute__ ((packed));
+    can_msg_t	msg12;
     uchar	p2in;
-    can_msg_t	msg13 __attribute__ ((packed));
+    can_msg_t	msg13;
     uchar	p1out;
-    can_msg_t	msg14 __attribute__ ((packed));
+    can_msg_t	msg14;
     uchar	p2out;
-    can_msg_t	msg15 __attribute__ ((packed));
+    can_msg_t	msg15;
     uchar	ser_res_addr;
     uchar	resv_cs[0x8000-0x100];	/* 0x8000 is the min size for CS */
 } can_reg_t;

board/stxgp3/stxgp3.c

@@ -29,15 +29,13 @@
  */
 
 
-extern long int spd_sdram (void);
-
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 
 long int fixed_sdram (void);
@@ -281,7 +279,6 @@ long int
 initdram (int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 #if defined(CONFIG_DDR_DLL)
 	{

board/stxssa/stxssa.c

@@ -29,15 +29,13 @@
  */
 
 
-extern long int spd_sdram (void);
-
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 
 long int fixed_sdram (void);
@@ -297,7 +295,6 @@ long int
 initdram (int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 #if defined(CONFIG_DDR_DLL)
 	{

board/tqm5200/tqm5200.c

@@ -43,6 +43,10 @@
 #include "mt48lc16m16a2-75.h"
 #endif
 
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_PS2MULT
@@ -155,10 +159,13 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
 
 	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
 		sdram_start(0);
-	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	if (!dramsize) {
 		sdram_start(1);
 		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	}
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
@@ -792,5 +799,6 @@ int board_get_height (void)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/tqm834x/tqm834x.c

@@ -27,7 +27,6 @@
 #include <mpc83xx.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 #include <asm-ppc/mmu.h>
 #include <pci.h>
@@ -59,7 +58,6 @@ int tqm834x_num_flash_banks;
 /* External definitions */
 ulong flash_get_size (ulong base, int banknum);
 extern flash_info_t flash_info[];
-extern long spd_sdram (void);
 
 /* Local functions */
 static int detect_num_flash_banks(void);

board/tqm85xx/sdram.c

@@ -27,7 +27,6 @@
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
-#include <spd.h>
 
 struct sdram_conf_s {
 	unsigned long size;

board/tqm85xx/tqm85xx.c

@@ -32,7 +32,6 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
 #include <flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,7 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
 extern flash_info_t flash_info[];	/* FLASH chips info */
 
 void local_bus_init (void);
-long int fixed_sdram (void);
 ulong flash_get_size (ulong base, int banknum);
 
 #ifdef CONFIG_PS2MULT

board/w7o/w7o.h

@@ -31,9 +31,6 @@
 #define PPC405GP_GPIO0_ODR	0xef600718L	/* GPIO Open Drain */
 #define PPC405GP_GPIO0_IR	0xef60071cL	/* GPIO Input */
 
-/* AMCC 405GP DCRs */
-#define CPC0_CR0		0xb1		/* Chip control register 0 */
-
 /* LMG FPGA <=> CPU GPIO signals */
 #define LMG_XCV_INIT		0x10000000L
 #define LMG_XCV_PROG		0x04000000L

common/cmd_mem.c

@@ -417,7 +417,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/* check if we are copying to Flash */
 	if ( (addr2info(dest) != NULL)
 #ifdef CONFIG_HAS_DATAFLASH
-	   && (!addr_dataflash(addr))
+	   && (!addr_dataflash(dest))
 #endif
 	   ) {
 		int rc;

common/cmd_nvedit.c

@@ -550,10 +550,11 @@ int getenv_r (char *name, char *buf, unsigned len)
 	return (-1);
 }
 
-#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
+#if ((defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
-    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))) \
+    && !defined(CFG_ENV_IS_NOWHERE))
 int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern char * env_name_spec;
@@ -605,10 +606,11 @@ U_BOOT_CMD(
 	"    - delete environment variable 'name'\n"
 );
 
-#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
+#if ((defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
-    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))) \
+    && !defined(CFG_ENV_IS_NOWHERE))
 U_BOOT_CMD(
 	saveenv, 1, 0,	do_saveenv,
 	"saveenv - save environment variables to persistent storage\n",

common/env_dataflash.c

@@ -44,22 +44,22 @@ extern uchar default_environment[];
 uchar env_get_char_spec (int index)
 {
 	uchar c;
-	read_dataflash (CFG_ENV_ADDR+index+offsetof(env_t,data),1,&c);
+	read_dataflash(CFG_ENV_ADDR + index + offsetof(env_t,data),
+	1, (char *)&c);
 	return (c);
 }
 
 void env_relocate_spec (void)
 {
-	read_dataflash (CFG_ENV_ADDR,CFG_ENV_SIZE,(uchar *)env_ptr);
+	read_dataflash(CFG_ENV_ADDR, CFG_ENV_SIZE, (char *)env_ptr);
 }
 
 int saveenv(void)
 {
-/* env must be copied to do not alter env structure in memory*/
-unsigned char temp[CFG_ENV_SIZE];
-int i;
+	/* env must be copied to do not alter env structure in memory*/
+	unsigned char temp[CFG_ENV_SIZE];
 	memcpy(temp, env_ptr, CFG_ENV_SIZE);
-	return write_dataflash (CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE);
+	return write_dataflash(CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE);
 }
 
 /************************************************************************
@@ -77,13 +77,14 @@ int env_init(void)
 		AT91F_DataflashInit();	/* prepare for DATAFLASH read/write */
 
 		/* read old CRC */
-		read_dataflash (CFG_ENV_ADDR+offsetof(env_t,crc),sizeof(ulong),&crc);
+		read_dataflash(CFG_ENV_ADDR + offsetof(env_t, crc),
+			sizeof(ulong), (char *)&crc);
 		new = 0;
 		len = ENV_SIZE;
 		off = offsetof(env_t,data);
 		while (len > 0) {
 			int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-			read_dataflash (CFG_ENV_ADDR+off,n , buf);
+			read_dataflash(CFG_ENV_ADDR + off, n, (char *)buf);
 			new = crc32 (new, buf, n);
 			len -= n;
 			off += n;

common/kgdb.c

@@ -107,7 +107,7 @@ static char remcomRegBuffer[BUFMAX];
 static int initialized = 0;
 static int kgdb_active = 0, first_entry = 1;
 static struct pt_regs entry_regs;
-static u_int error_jmp_buf[BUFMAX/2];
+static long error_jmp_buf[BUFMAX/2];
 static int longjmp_on_fault = 0;
 #ifdef KGDB_DEBUG
 static int kdebug = 1;
@@ -310,7 +310,7 @@ handle_exception (struct pt_regs *regs)
 	/* probably should check which exception occured as well */
 	if (longjmp_on_fault) {
 		longjmp_on_fault = 0;
-		kgdb_longjmp((long*)error_jmp_buf, KGDBERR_MEMFAULT);
+		kgdb_longjmp(error_jmp_buf, KGDBERR_MEMFAULT);
 		panic("kgdb longjump failed!\n");
 	}
 
@@ -324,7 +324,7 @@ handle_exception (struct pt_regs *regs)
 
 	printf("kgdb: handle_exception; trap [0x%x]\n", kgdb_trap(regs));
 
-	if (kgdb_setjmp((long*)error_jmp_buf) != 0)
+	if (kgdb_setjmp(error_jmp_buf) != 0)
 		panic("kgdb: error or fault in entry init!\n");
 
 	kgdb_enter(regs, &kd);
@@ -379,7 +379,7 @@ handle_exception (struct pt_regs *regs)
 			printf("kgdb:  remcomInBuffer: %s\n", remcomInBuffer);
 #endif
 
-		errnum = kgdb_setjmp((long*)error_jmp_buf);
+		errnum = kgdb_setjmp(error_jmp_buf);
 
 		if (errnum == 0) switch (remcomInBuffer[0]) {
 
@@ -532,7 +532,7 @@ void
 kgdb_error(int errnum)
 {
 	longjmp_on_fault = 0;
-	kgdb_longjmp((long*)error_jmp_buf, errnum);
+	kgdb_longjmp(error_jmp_buf, errnum);
 	panic("kgdb_error: longjmp failed!\n");
 }
 

config.mk

@@ -69,6 +69,9 @@ PLATFORM_CPPFLAGS+= -D__ARM__
 endif
 endif
 
+# Load generated board configuration
+sinclude $(OBJTREE)/include/autoconf.mk
+
 ifdef	ARCH
 sinclude $(TOPDIR)/$(ARCH)_config.mk	# include architecture dependend rules
 endif
@@ -87,9 +90,6 @@ ifdef	BOARD
 sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk	# include board specific rules
 endif
 
-# Load generated board configuration
-sinclude $(OBJTREE)/include/autoconf.mk
-
 #########################################################################
 
 CONFIG_SHELL	:= $(shell if [ -x "$$BASH" ]; then echo $$BASH; \

cpu/arm1136/interrupts.c

@@ -37,145 +37,11 @@
 # include <asm/arch/omap2420.h>
 #endif
 
-#include <asm/proc-armv/ptrace.h>
-
 #define TIMER_LOAD_VAL 0
 
 /* macro to read the 32 bit timer */
 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
 
-#ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-						 "bic %0, %0, #0x80\n"
-						 "msr cpsr_c, %0"
-						 : "=r" (temp)
-						 :
-						 : "memory");
-}
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-						 "orr %1, %0, #0xc0\n"
-						 "msr cpsr_c, %1"
-						 : "=r" (old), "=r" (temp)
-						 :
-						 : "memory");
-	return(old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-		"USER_26",  "FIQ_26",   "IRQ_26",   "SVC_26",
-		"UK4_26",   "UK5_26",   "UK6_26",   "UK7_26",
-		"UK8_26",   "UK9_26",   "UK10_26",  "UK11_26",
-		"UK12_26",  "UK13_26",  "UK14_26",  "UK15_26",
-		"USER_32",  "FIQ_32",   "IRQ_32",   "SVC_32",
-		"UK4_32",   "UK5_32",   "UK6_32",   "ABT_32",
-		"UK8_32",   "UK9_32",   "UK10_32",  "UND_32",
-		"UK12_32",  "UK13_32",  "UK14_32",  "SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-			"sp : %08lx  ip : %08lx  fp : %08lx\n",
-			instruction_pointer (regs),
-			regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-			regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-			regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-			regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-			flags & CC_N_BIT ? 'N' : 'n',
-			flags & CC_Z_BIT ? 'Z' : 'z',
-			flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-			interrupts_enabled (regs) ? "on" : "off",
-			fast_interrupts_enabled (regs) ? "on" : "off",
-			processor_modes[processor_mode (regs)],
-			thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
 /* Use the IntegratorCP function from board/integratorcp.c */
 #else

cpu/arm720t/interrupts.c

@@ -60,137 +60,9 @@ static struct _irq_handler IRQ_HANDLER[N_IRQS];
 #endif	/* CONFIG_S3C4510B */
 
 #ifdef CONFIG_USE_IRQ
-/* enable IRQ/FIQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0x80\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else /* CONFIG_USE_IRQ */
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] =
-		{ "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
-"UK6_26", "UK7_26",
-		"UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
-				"UK14_26", "UK15_26",
-		"USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
-				"UK6_32", "ABT_32",
-		"UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
-				"UK14_32", "SYS_32"
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
-			"sp : %08lx  ip : %08lx	 fp : %08lx\n",
-			instruction_pointer (regs),
-			regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
-			regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
-			regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
-			regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-			flags & CC_N_BIT ? 'N' : 'n',
-			flags & CC_Z_BIT ? 'Z' : 'z',
-			flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-			interrupts_enabled (regs) ? "on" : "off",
-			fast_interrupts_enabled (regs) ? "on" : "off",
-			processor_modes[processor_mode (regs)],
-			thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-#elif defined(CONFIG_S3C4510B)
+#if defined(CONFIG_S3C4510B)
 	unsigned int pending;
 
 	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
@@ -212,7 +84,7 @@ void do_irq (struct pt_regs *pt_regs)
 #error do_irq() not defined for this CPU type
 #endif
 }
-
+#endif
 
 #ifdef CONFIG_S3C4510B
 static void default_isr( void *data) {

cpu/arm920t/interrupts.c

@@ -31,149 +31,20 @@
 
 #include <common.h>
 #include <arm920t.h>
-#include <asm/proc-armv/ptrace.h>
 
 #ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx  fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
+#include <asm/proc-armv/ptrace.h>
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined (CONFIG_USE_IRQ)
 #if defined (ARM920_IRQ_CALLBACK)
 	ARM920_IRQ_CALLBACK();
-	return;
 #elif defined (CONFIG_ARCH_INTEGRATOR)
 	/* ASSUMED to be a timer interrupt  */
 	/* Just clear it - count handled in */
 	/* integratorap.c                   */
 	*(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
-#endif /* ARCH_INTEGRATOR */
 #else
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
+#error do_irq() not defined for this cpu type
 #endif
 }
+#endif

cpu/arm920t/s3c24x0/serial.c

@@ -110,7 +110,6 @@ void serial_setbrg(void)
 static int serial_init_dev(const int dev_index)
 {
 	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
-	int i;
 
 	/* FIFO enable, Tx/Rx FIFO clear */
 	uart->UFCON = 0x07;

cpu/arm925t/interrupts.c

@@ -36,146 +36,11 @@
 #include <arm925t.h>
 #include <configs/omap1510.h>
 
-#include <asm/proc-armv/ptrace.h>
-
 #define TIMER_LOAD_VAL 0xffffffff
 
 /* macro to read the 32 bit timer */
 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
 
-#ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx	 fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 static ulong timestamp;
 static ulong lastdec;
 

cpu/arm926ejs/at91cap9/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= ether.o timer.o spi.o usb.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm926ejs/at91cap9/config.mk

@@ -0,0 +1,2 @@
+PLATFORM_CPPFLAGS += -march=armv5te
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)

cpu/arm926ejs/at91cap9/ether.c

@@ -1,6 +1,7 @@
 /*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,19 +23,13 @@
  */
 
 #include <common.h>
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init(void)
-{
-	printf("Skipping flash_init\n");
-	return(0);
-}
+#include <asm/arch/AT91CAP9.h>
 
-int write_buff(void *info, uchar *src, ulong addr, ulong cnt)
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
+void at91cap9_eth_initialize(bd_t *bi)
 {
-	printf("write_buff not implemented\n");
-	return(-1);
+	macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
 }
+#endif

cpu/arm926ejs/at91cap9/lowlevel_init.S

@@ -0,0 +1,43 @@
+/*
+ * AT91CAP9 setup stuff
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Clocks/SDRAM initialization is handled by at91bootstrap,
+	 * no need to do it here...
+	 */
+	mov	pc, lr
+
+	.ltorg
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

cpu/arm926ejs/at91cap9/spi.c

@@ -0,0 +1,119 @@
+/*
+ * Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+/* Max Value = 10MHz to be compliant to the Continuous Array Read function */
+#define AT91C_SPI_CLK	10000000
+
+/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xFA << 16)
+#define DATAFLASH_TCHS	(0x8 << 24)
+
+#define AT91C_TIMEOUT_WRDY		200000
+#define AT91C_SPI_PCS0_DATAFLASH_CARD	0xE	/* Chip Select 0: NPCS0%1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD	0x7	/* Chip Select 3: NPCS3%0111 */
+
+void AT91F_SpiInit(void)
+{
+	/* Reset the SPI */
+	AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST;
+
+	/* Configure SPI in Master Mode with No CS selected !!! */
+	AT91C_BASE_SPI0->SPI_MR =
+		AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+	/* Configure CS0 */
+	AT91C_BASE_SPI0->SPI_CSR[0] =
+		AT91C_SPI_CPOL |
+		(AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
+		(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
+		((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+}
+
+void AT91F_SpiEnable(int cs)
+{
+	switch (cs) {
+	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+		AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI0->SPI_MR |=
+			((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+		break;
+	case 3:
+		AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI0->SPI_MR |=
+			((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+		break;
+	}
+
+	/* SPI_Enable */
+	AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
+{
+	unsigned int timeout;
+
+	pDesc->state = BUSY;
+
+	AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+	/* Initialize the Transmit and Receive Pointer */
+	AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt;
+	AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt;
+
+	/* Intialize the Transmit and Receive Counters */
+	AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size;
+	AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size;
+
+	if (pDesc->tx_data_size != 0) {
+		/* Initialize the Next Transmit and Next Receive Pointer */
+		AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt;
+		AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt;
+
+		/* Intialize the Next Transmit and Next Receive Counters */
+		AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size;
+		AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size;
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+	timeout = 0;
+
+	AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+	while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) &&
+		((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
+	AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+	pDesc->state = IDLE;
+
+	if (timeout >= CFG_SPI_WRITE_TOUT) {
+		printf("Error Timeout\n\r");
+		return DATAFLASH_ERROR;
+	}
+
+	return DATAFLASH_OK;
+}
+#endif

cpu/arm926ejs/at91cap9/timer.c

@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * We're using the AT91CAP9 PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ */
+#define TIMER_LOAD_VAL	0xfffff
+#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR)
+#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR)
+#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
+#define TICKS_TO_USEC(ticks) ((ticks) / 6)
+
+ulong get_timer_masked(void);
+ulong resettime;
+
+AT91PS_PITC p_pitc;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init(void)
+{
+	/*
+	 * Enable PITC Clock
+	 * The clock is already enabled for system controller in boot
+	 */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+
+	/* Enable PITC */
+	AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN;
+
+	/* Load PITC_PIMR with the right timer value */
+	AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL;
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+static inline ulong get_timer_raw(void)
+{
+	ulong now = READ_TIMER;
+	if (now >= resettime)
+		return now - resettime;
+	else
+		return 0xFFFFFFFFUL - (resettime - now) ;
+}
+
+void reset_timer_masked(void)
+{
+	resettime = READ_TIMER;
+}
+
+ulong get_timer_masked(void)
+{
+	return TICKS_TO_USEC(get_timer_raw());
+
+}
+
+void udelay_masked(unsigned long usec)
+{
+	ulong tmp;
+
+	tmp = get_timer(0);
+	while (get_timer(tmp) < usec)	/* our timer works in usecs */
+		; /* NOP */
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	ulong now = get_timer_masked();
+
+	if (now >= base)
+		return now - base;
+	else
+		return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ;
+}
+
+void udelay(unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * on the AT91CAP9ADK board
+ */
+void reset_cpu(ulong ignored)
+{
+	/* this is the way Linux does it */
+	AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) |
+				    AT91C_RSTC_PROCRST |
+				    AT91C_RSTC_PERRST;
+
+	while (1);
+	/* Never reached */
+}