MPC5121e ADS PCI support take 3
Adds PCI support for MPC5121 Tested with drivers/net/rtl8139.c Support is conditional since PCI on old silicon does not work. ads5121_PCI_config turns on PCI In this version, condition compilation of PCI code has been moved from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as suggested by Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: John Rigby <jrigby@freescale.com>
This commit is contained in:
John Rigby
Wolfgang Denk
parent
44b4dbed41
commit
5f91db7f58
11
Makefile
11
Makefile
@ -733,8 +733,15 @@ motionpro_config: unconfig
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#########################################################################
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## MPC512x Systems
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#########################################################################
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ads5121_config: unconfig
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@$(MKCONFIG) ads5121 ppc mpc512x ads5121
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ads5121_config \
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ads5121_PCI_config \
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: unconfig
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@echo "" >$(obj)include/config.h
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@if [ "$(findstring _PCI_,$@)" ] ; then \
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echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
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$(XECHO) "... with PCI enabled" ; \
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fi
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@$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
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#########################################################################
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@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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COBJS-y := $(BOARD).o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -34,6 +34,7 @@
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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213
board/ads5121/pci.c
Normal file
213
board/ads5121/pci.c
Normal file
@ -0,0 +1,213 @@
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/global_data.h>
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#include <pci.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
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static struct pci_controller pci_hose;
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/**************************************************************************
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* pci_init_board()
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*
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*/
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void
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pci_init_board(void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile law512x_t *pci_law;
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volatile pot512x_t *pci_pot;
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volatile pcictrl512x_t *pci_ctrl;
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volatile pciconf512x_t *pci_conf;
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u16 reg16;
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u32 reg32;
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u32 dev;
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struct pci_controller *hose;
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/* Set PCI divider for 33MHz */
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reg32 = immr->clk.scfr[0];
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reg32 &= ~(SCFR1_PCI_DIV_MASK);
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reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
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immr->clk.scfr[0] = reg32;
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pci_law = immr->sysconf.pcilaw;
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pci_pot = immr->ios.pot;
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pci_ctrl = &immr->pci_ctrl;
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pci_conf = &immr->pci_conf;
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hose = &pci_hose;
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/*
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* Release PCI RST Output signal
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*/
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pci_ctrl->gcr = 0;
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udelay(2000);
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pci_ctrl->gcr = 1;
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/* We need to wait at least a 1sec based on PCI specs */
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{
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int i;
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for (i = 0; i < 1000; i++)
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udelay(1000);
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}
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
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pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI mem space - prefetch */
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pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
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/* PCI IO space */
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pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
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/* PCI mmio - non-prefetch mem space */
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pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
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/*
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* Configure PCI Inbound Translation Windows
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*/
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/* we need RAM mapped to PCI space for the devices to
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* access main memory */
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pci_ctrl[0].pitar1 = 0x0;
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pci_ctrl[0].pibar1 = 0x0;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEM_BASE,
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CFG_PCI_MEM_PHYS,
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CFG_PCI_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CFG_PCI_MMIO_BASE,
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CFG_PCI_MMIO_PHYS,
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CFG_PCI_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CFG_PCI_IO_BASE,
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CFG_PCI_IO_PHYS,
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CFG_PCI_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CFG_IMMR + 0x8300),
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(CFG_IMMR + 0x8304));
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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}
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#if defined(CONFIG_OF_LIBFDT)
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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int nodeoffset;
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int tmp[2];
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const char *path;
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nodeoffset = fdt_path_offset(blob, "/aliases");
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if (nodeoffset >= 0) {
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path = fdt_getprop(blob, nodeoffset, "pci", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(pci_hose.first_busno);
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tmp[1] = cpu_to_be32(pci_hose.last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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}
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}
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#endif /* CONFIG_OF_LIBFDT */
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@ -67,12 +67,14 @@ int get_clocks (void)
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u8 cpmf;
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u8 sys_div;
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u8 ips_div;
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u8 pci_div;
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u32 ref_clk = CFG_MPC512X_CLKIN;
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u32 spll;
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u32 sys_clk;
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u32 core_clk;
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u32 csb_clk;
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u32 ips_clk;
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u32 pci_clk;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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@ -95,8 +97,16 @@ int get_clocks (void)
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/* in case we cannot get a sane IPS divisor, fail gracefully */
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ips_clk = 0;
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}
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pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
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if (pci_div != 0) {
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pci_clk = csb_clk / pci_div;
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} else {
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/* in case we cannot get a sane IPS divisor, fail gracefully */
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pci_clk = 333333;
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}
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gd->ips_clk = ips_clk;
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gd->pci_clk = pci_clk;
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gd->csb_clk = csb_clk;
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gd->cpu_clk = core_clk;
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gd->bus_clk = csb_clk;
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@ -115,11 +125,12 @@ ulong get_bus_freq (ulong dummy)
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int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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printf ("Clock configuration:\n");
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printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000);
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printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
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printf (" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000);
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printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
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printf("Clock configuration:\n");
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printf(" CPU: %4d MHz\n", gd->cpu_clk / 1000000);
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printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
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printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000);
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printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000);
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printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
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return 0;
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}
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@ -103,6 +103,7 @@ typedef struct global_data {
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#if defined(CONFIG_MPC512X)
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u32 ips_clk;
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u32 csb_clk;
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u32 pci_clk;
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#endif /* CONFIG_MPC512X */
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#if defined(CONFIG_MPC8220)
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unsigned long bExtUart;
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@ -29,7 +29,7 @@
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typedef struct law512x {
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u32 bar; /* Base Addr Register */
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u32 ar; /* Attributes Register */
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} law521x_t;
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} law512x_t;
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/*
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* System configuration registers
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@ -47,9 +47,9 @@ typedef struct sysconf512x {
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u32 lpcs6aw; /* LP CS6 Access Window */
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u32 lpcs7aw; /* LP CS7 Access Window */
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u8 res1[0x1c];
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law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
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law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
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u8 res2[0x28];
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law521x_t ddrlaw; /* DDR Local Access Window */
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law512x_t ddrlaw; /* DDR Local Access Window */
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u8 res3[0x18];
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u32 mbxbar; /* MBX Base Address */
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u32 srambar; /* SRAM Base Address */
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@ -241,21 +241,70 @@ typedef struct dma512x {
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* PCI Software Configuration Registers
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*/
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typedef struct pciconf512x {
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u8 fixme[0x80];
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u32 config_address;
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u32 config_data;
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u32 int_ack;
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u8 res[116];
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} pciconf512x_t;
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/*
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* PCI Outbound Translation Register
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*/
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typedef struct pci_outbound_window {
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u32 potar;
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u8 res0[4];
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u32 pobar;
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u8 res1[4];
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u32 pocmr;
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u8 res2[4];
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} pot512x_t;
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/*
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* Sequencer
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*/
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typedef struct ios512x {
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u8 fixme[0x100];
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pot512x_t pot[6];
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u8 res0[0x60];
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u32 pmcr;
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u8 res1[4];
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u32 dtcr;
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u8 res2[4];
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} ios512x_t;
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/*
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* PCI Controller
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*/
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typedef struct pcictrl512x {
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u8 fixme[0x100];
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u32 esr;
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u32 ecdr;
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u32 eer;
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u32 eatcr;
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u32 eacr;
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u32 eeacr;
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u32 edlcr;
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u32 edhcr;
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u32 gcr;
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u32 ecr;
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u32 gsr;
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u8 res0[12];
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u32 pitar2;
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u8 res1[4];
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u32 pibar2;
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u32 piebar2;
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u32 piwar2;
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u8 res2[4];
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u32 pitar1;
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u8 res3[4];
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u32 pibar1;
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u32 piebar1;
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u32 piwar1;
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u8 res4[4];
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u32 pitar0;
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u8 res5[4];
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u32 pibar0;
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u8 res6[4];
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u32 piwar0;
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u8 res7[132];
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} pcictrl512x_t;
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@ -34,6 +34,9 @@
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* 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
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* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
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* 0x8200_0000 - 0x8200_001F CPLD (32 B)
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* 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
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* 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
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* 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
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* 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
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*/
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@ -43,7 +46,7 @@
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC512X 1 /* MPC512X family */
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#undef CONFIG_PCI
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/* CONFIG_PCI is defined at config time */
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#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
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@ -217,6 +220,31 @@
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* PCI
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*/
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#ifdef CONFIG_PCI
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/*
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* General PCI
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*/
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#define CFG_PCI_MEM_BASE 0xA0000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
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#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
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#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
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#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_IO_BASE 0x00000000
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#define CFG_PCI_IO_PHYS 0x84000000
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||||
#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
|
||||
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
|
||||
|
||||
@ -46,6 +46,7 @@
|
||||
#define LPCS6AW 0x003C
|
||||
#define LPCA7AW 0x0040
|
||||
#define SRAMBAR 0x00C4
|
||||
#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
|
||||
|
||||
#define LPC_OFFSET 0x10000
|
||||
|
||||
@ -189,6 +190,10 @@
|
||||
#define SCFR1_IPS_DIV_MASK 0x03800000
|
||||
#define SCFR1_IPS_DIV_SHIFT 23
|
||||
|
||||
#define SCFR1_PCI_DIV 0x6
|
||||
#define SCFR1_PCI_DIV_MASK 0x00700000
|
||||
#define SCFR1_PCI_DIV_SHIFT 20
|
||||
|
||||
/* SCFR2 System Clock Frequency Register 2
|
||||
*/
|
||||
#define SCFR2_SYS_DIV 0xFC000000
|
||||
@ -404,4 +409,83 @@
|
||||
#define I2C_IF 0x02
|
||||
#define I2C_RXAK 0x01
|
||||
|
||||
/* POTAR - PCI Outbound Translation Address Register
|
||||
*/
|
||||
#define POTAR_TA_MASK 0x000fffff
|
||||
|
||||
/* POBAR - PCI Outbound Base Address Register
|
||||
*/
|
||||
#define POBAR_BA_MASK 0x000fffff
|
||||
|
||||
/* POCMR - PCI Outbound Comparision Mask Register
|
||||
*/
|
||||
#define POCMR_EN 0x80000000
|
||||
#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
|
||||
#define POCMR_PRE 0x20000000 /* prefetch enable */
|
||||
#define POCMR_SBS 0x00100000 /* special byte swap enable */
|
||||
#define POCMR_CM_MASK 0x000fffff
|
||||
#define POCMR_CM_4G 0x00000000
|
||||
#define POCMR_CM_2G 0x00080000
|
||||
#define POCMR_CM_1G 0x000C0000
|
||||
#define POCMR_CM_512M 0x000E0000
|
||||
#define POCMR_CM_256M 0x000F0000
|
||||
#define POCMR_CM_128M 0x000F8000
|
||||
#define POCMR_CM_64M 0x000FC000
|
||||
#define POCMR_CM_32M 0x000FE000
|
||||
#define POCMR_CM_16M 0x000FF000
|
||||
#define POCMR_CM_8M 0x000FF800
|
||||
#define POCMR_CM_4M 0x000FFC00
|
||||
#define POCMR_CM_2M 0x000FFE00
|
||||
#define POCMR_CM_1M 0x000FFF00
|
||||
#define POCMR_CM_512K 0x000FFF80
|
||||
#define POCMR_CM_256K 0x000FFFC0
|
||||
#define POCMR_CM_128K 0x000FFFE0
|
||||
#define POCMR_CM_64K 0x000FFFF0
|
||||
#define POCMR_CM_32K 0x000FFFF8
|
||||
#define POCMR_CM_16K 0x000FFFFC
|
||||
#define POCMR_CM_8K 0x000FFFFE
|
||||
#define POCMR_CM_4K 0x000FFFFF
|
||||
|
||||
/* PITAR - PCI Inbound Translation Address Register
|
||||
*/
|
||||
#define PITAR_TA_MASK 0x000fffff
|
||||
|
||||
/* PIBAR - PCI Inbound Base/Extended Address Register
|
||||
*/
|
||||
#define PIBAR_MASK 0xffffffff
|
||||
#define PIEBAR_EBA_MASK 0x000fffff
|
||||
|
||||
/* PIWAR - PCI Inbound Windows Attributes Register
|
||||
*/
|
||||
#define PIWAR_EN 0x80000000
|
||||
#define PIWAR_SBS 0x40000000
|
||||
#define PIWAR_PF 0x20000000
|
||||
#define PIWAR_RTT_MASK 0x000f0000
|
||||
#define PIWAR_RTT_NO_SNOOP 0x00040000
|
||||
#define PIWAR_RTT_SNOOP 0x00050000
|
||||
#define PIWAR_WTT_MASK 0x0000f000
|
||||
#define PIWAR_WTT_NO_SNOOP 0x00004000
|
||||
#define PIWAR_WTT_SNOOP 0x00005000
|
||||
#define PIWAR_IWS_MASK 0x0000003F
|
||||
#define PIWAR_IWS_4K 0x0000000B
|
||||
#define PIWAR_IWS_8K 0x0000000C
|
||||
#define PIWAR_IWS_16K 0x0000000D
|
||||
#define PIWAR_IWS_32K 0x0000000E
|
||||
#define PIWAR_IWS_64K 0x0000000F
|
||||
#define PIWAR_IWS_128K 0x00000010
|
||||
#define PIWAR_IWS_256K 0x00000011
|
||||
#define PIWAR_IWS_512K 0x00000012
|
||||
#define PIWAR_IWS_1M 0x00000013
|
||||
#define PIWAR_IWS_2M 0x00000014
|
||||
#define PIWAR_IWS_4M 0x00000015
|
||||
#define PIWAR_IWS_8M 0x00000016
|
||||
#define PIWAR_IWS_16M 0x00000017
|
||||
#define PIWAR_IWS_32M 0x00000018
|
||||
#define PIWAR_IWS_64M 0x00000019
|
||||
#define PIWAR_IWS_128M 0x0000001A
|
||||
#define PIWAR_IWS_256M 0x0000001B
|
||||
#define PIWAR_IWS_512M 0x0000001C
|
||||
#define PIWAR_IWS_1G 0x0000001D
|
||||
#define PIWAR_IWS_2G 0x0000001E
|
||||
|
||||
#endif /* __MPC512X_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user