* Patch by Jim Sandoz, 07 Nov 2002:

Increase number of network RX buffers (PKTBUFSRX in
  "include/net.h") for EEPRO100 based boards (especially SP8240)
  which showed "Receiver is not ready" errors when U-Boot was
  processing the receive buffers slower than the network controller
  was filling them.

* Get rid of obsolete include/mpc74xx.h

CHANGELOG

@@ -2,6 +2,48 @@
 Changes since for U-Boot 0.1.0:
 ======================================================================
 
+* Patch by Jim Sandoz, 07 Nov 2002:
+  Increase number of network RX buffers (PKTBUFSRX in
+  "include/net.h") for EEPRO100 based boards (especially SP8240)
+  which showed "Receiver is not ready" errors when U-Boot was
+  processing the receive buffers slower than the network controller
+  was filling them.
+
+* Patch by Andreas Oberritter, 09 Nov 2002:
+  Change behaviour of NetLoop(): return -1 for errors, filesize
+  otherwise; return code 0 is valid an means no file loaded - in this
+  case the environment still gets updated!
+
+* Patches by Jon Diekema, 9 Nov 2002:
+  - improve ADC/DAC clocking on the SACSng board to align
+    the failing edges of LRCLK and SCLK
+  - sbc8260 configuration tweaks
+  - add status LED support for 82xx systems
+  - wire sspi/sspo commands into command handler; improved error
+    handlering
+  - add timestamp support and alternate memory test to the
+    SACSng configuration
+
+* Patch by Vince Husovsky, 7 Nov 2002:
+  Add "-n" to linker options to get rid of "Not enough room for
+  program headers" problem
+
+* Patch by David Müller, 05 Nov 2002
+  Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
+  so we can use an already existing name
+
+* Patch by Pierre Aubert, 05 Nov 2002
+  Hardware relatied improvments in FDC boot code
+
+* Patch by Holger Schurig, 5 Nov 2002:
+  Make the PXA really change it's frequency
+
+* Patch by Pierre Aubert, 05 Nov 2002
+  Add support for slave serial Spartan 2 FPGAs
+
+* Fix uninitialized memory (MAC  address)  in  8xx  SCC/FEC  ethernet
+  drivers
+
 * Add support for log buffer which can be passed to Linux kernel's
   syslog mechanism; used especially for POST results.
 

README

@@ -266,6 +266,11 @@ Example: For a TQM823L module, all configuration settings are in
 "include/configs/TQM823L.h".
 
 
+Many of the options are named exactly as the corresponding Linux
+kernel configuration options. The intention is to make it easier to
+build a config tool - later.
+
+
 The following options need to be configured:
 
 - CPU Type:	Define exactly one of
@@ -1523,10 +1528,6 @@ Note2: you must edit your u-boot.lds file to reflect this
 configuration.
 
 
-Many of the options are named exactly as the corresponding Linux
-kernel configuration options. The intention is to make it easier to
-build a config tool - later.
-
 Low Level (hardware related) configuration options:
 
 - CFG_CACHELINE_SIZE:
@@ -1538,6 +1539,32 @@ Low Level (hardware related) configuration options:
 		to be able to adjust the position of the IMMR
 		register after a reset.
 
+- Floppy Disk Support:
+		CFG_FDC_DRIVE_NUMBER
+
+		the default drive number (default value 0)
+
+		CFG_ISA_IO_STRIDE
+
+		defines the spacing between fdc chipset registers
+		(default value 1)
+
+		CFG_ISA_IO_OFFSET
+
+                defines the offset of register from address. It
+                depends on which part of the data bus is connected to
+                the fdc chipset. (default value 0)
+
+                If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and
+                CFG_FDC_DRIVE_NUMBER are undefined, they take their
+                default value.
+
+                if CFG_FDC_HW_INIT is defined, then the function
+                fdc_hw_init() is called at the beginning of the FDC
+                setup. fdc_hw_init() must be provided by the board
+                source code. It is used to make hardware dependant
+                initializations.
+
 - CFG_IMMR:	Physical address of the Internal Memory Mapped
 		Register; DO NOT CHANGE! (11-4)
 		[MPC8xx systems only]

board/hymod/bsp.c

@@ -197,7 +197,7 @@ do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 			copy_filename (BootFile, argv[2], sizeof (BootFile));
 			load_addr = simple_strtoul (argv[3], NULL, 16);
 
-			if (NetLoop (TFTP) == 0) {
+			if (NetLoop (TFTP) <= 0) {
 				printf ("tftp transfer failed - aborting fgpa load\n");
 				return 1;
 			}

board/hymod/fetch.c

@@ -89,7 +89,7 @@ fetch_and_parse(bd_t *bd, char *fn, ulong addr, int (*cback)(uchar *, uchar *))
     copy_filename(BootFile, fn, sizeof (BootFile));
     load_addr = addr;
 
-    if (NetLoop(TFTP) == 0) {
+    if (NetLoop(TFTP) <= 0) {
 	printf("tftp transfer of file '%s' failed\n", fn);
 	return (0);
     }

board/sacsng/clkinit.c

@@ -286,7 +286,6 @@ uint Daq_BRG_Rate(uint brg)
 }
 
 uint Daq_Get_SampleRate(void)
-
 {
      /*
       * Read the BRG's to return the actual sample rate.
@@ -294,68 +293,12 @@ uint Daq_Get_SampleRate(void)
      return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
 }
 
-uint Daq_Set_SampleRate(uint rate, uint force)
-
+void Daq_Init_Clocks(int sample_rate, int sample_64x)
 {
     DECLARE_GLOBAL_DATA_PTR;
-    uint mclk_divisor; /* MCLK divisor */
-    uint rate_curr;    /* Current sample rate */
-
-    /*
-     * Limit the sample rate to some sensible values.
-     */
-    if (Daq64xSampling) {
-      if (rate > MAX_64x_SAMPLE_RATE) {
-	  rate = MAX_64x_SAMPLE_RATE;
-      }
-    }
-    else {
-      if (rate > MAX_128x_SAMPLE_RATE) {
-	  rate = MAX_128x_SAMPLE_RATE;
-      }
-    }
-    if (rate < MIN_SAMPLE_RATE) {
-        rate = MIN_SAMPLE_RATE;
-    }
-
-    /* Check to see if we are really changing rates */
-    rate_curr = Daq_Get_SampleRate();
-    if ((rate != rate_curr) || force) {
-        /*
-	 * Dynamically adjust MCLK based on the new sample rate.
-	 */
-
-        /* Compute the divisors */
-        mclk_divisor = BRG_INT_CLK / (rate * MCLK_DIVISOR * SCLK_DIVISOR);
-
-	/* Setup MCLK */
-	Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
-
-	/* Setup SCLK */
-#       ifdef RUN_SCLK_ON_BRG_INT
-	   Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
-#       else
-	   Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
-#       endif
-
-#       ifdef RUN_LRCLK_ON_BRG_INT
-	    Daq_BRG_Set_Count(LRCLK_BRG,
-			      mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
-#       else
-	    Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
-#       endif
-
-	/* Read the BRG's to return the actual sample rate. */
-	rate_curr = Daq_Get_SampleRate();
-    }
-
-    return (rate_curr);
-}
-
-void Daq_Init_Clocks(int sample_rate, int sample_64x)
-
-{
     volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
+    uint mclk_divisor; /* MCLK divisor */
+    int  flag;         /* Interrupt state */ 
 
     /* Save off the clocking data */
     Daq64xSampling = sample_64x;
@@ -363,18 +306,11 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
     /*
      * Limit the sample rate to some sensible values.
      */
-    if (Daq64xSampling) {
-      if (sample_rate > MAX_64x_SAMPLE_RATE) {
-	  sample_rate = MAX_64x_SAMPLE_RATE;
-      }
-    }
-    else {
-      if (sample_rate > MAX_128x_SAMPLE_RATE) {
-	  sample_rate = MAX_128x_SAMPLE_RATE;
-      }
+    if (sample_rate > MAX_64x_SAMPLE_RATE) {
+        sample_rate = MAX_64x_SAMPLE_RATE;	
     }
     if (sample_rate < MIN_SAMPLE_RATE) {
-        sample_rate = MIN_SAMPLE_RATE;
+        sample_rate = MIN_SAMPLE_RATE;	
     }
 
     /*
@@ -398,8 +334,41 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
         Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
 #   endif
 
-    /* Setup the BRG rates */
-    Daq_Set_SampleRate(sample_rate, TRUE);
+    /*
+     * Dynamically adjust MCLK based on the new sample rate.
+     */
+
+    /* Compute the divisors */
+    mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
+
+    /*
+     * Disable interrupt and save the current state
+     */
+    flag = disable_interrupts();
+
+    /* Setup MCLK */
+    Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
+#   endif
+
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(LRCLK_BRG, 
+			  mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
+#   endif
+
+    /*
+     * Restore the Interrupt state
+     */
+     if (flag) {
+         enable_interrupts();
+     }
 
     /* Enable the clock drivers */
     iopa->pdat &= ~SLRCLK_EN_MASK;
@@ -410,116 +379,276 @@ void Daq_Stop_Clocks(void)
 {
 #ifdef TIGHTEN_UP_BRG_TIMING
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flag;           /* Interrupt flags */
 #endif
 
 #   ifdef TIGHTEN_UP_BRG_TIMING
-        /*
-         * Reset MCLK BRG
+        /* 
+         * Obtain MCLK BRG reset/disabled value
          */
 #       if (MCLK_BRG == 0)
-            immr->im_brgc1 |=  CPM_BRG_RST;
-            immr->im_brgc1 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 1)
-            immr->im_brgc2 |=  CPM_BRG_RST;
-            immr->im_brgc2 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 2)
-            immr->im_brgc3 |=  CPM_BRG_RST;
-            immr->im_brgc3 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 3)
-            immr->im_brgc4 |=  CPM_BRG_RST;
-            immr->im_brgc4 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 4)
-            immr->im_brgc5 |=  CPM_BRG_RST;
-            immr->im_brgc5 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 5)
-            immr->im_brgc6 |=  CPM_BRG_RST;
-            immr->im_brgc6 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 6)
-            immr->im_brgc7 |=  CPM_BRG_RST;
-            immr->im_brgc7 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 7)
-            immr->im_brgc8 |=  CPM_BRG_RST;
-            immr->im_brgc8 &= ~CPM_BRG_RST;
+            mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 
-        /*
-         * Reset SCLK BRG
+        /* 
+         * Obtain SCLK BRG reset/disabled value
          */
 #       if (SCLK_BRG == 0)
-            immr->im_brgc1 |=  CPM_BRG_RST;
-            immr->im_brgc1 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 1)
-            immr->im_brgc2 |=  CPM_BRG_RST;
-            immr->im_brgc2 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 2)
-            immr->im_brgc3 |=  CPM_BRG_RST;
-            immr->im_brgc3 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 3)
-            immr->im_brgc4 |=  CPM_BRG_RST;
-            immr->im_brgc4 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 4)
-            immr->im_brgc5 |=  CPM_BRG_RST;
-            immr->im_brgc5 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 5)
-            immr->im_brgc6 |=  CPM_BRG_RST;
-            immr->im_brgc6 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 6)
-            immr->im_brgc7 |=  CPM_BRG_RST;
-            immr->im_brgc7 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 7)
-            immr->im_brgc8 |=  CPM_BRG_RST;
-            immr->im_brgc8 &= ~CPM_BRG_RST;
+            sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 
-        /*
-         * Reset LRCLK BRG
+        /* 
+         * Obtain LRCLK BRG reset/disabled value
          */
 #       if (LRCLK_BRG == 0)
-            immr->im_brgc1 |=  CPM_BRG_RST;
-            immr->im_brgc1 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 1)
-            immr->im_brgc2 |=  CPM_BRG_RST;
-            immr->im_brgc2 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 2)
-            immr->im_brgc3 |=  CPM_BRG_RST;
-            immr->im_brgc3 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 3)
-            immr->im_brgc4 |=  CPM_BRG_RST;
-            immr->im_brgc4 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 4)
-            immr->im_brgc5 |=  CPM_BRG_RST;
-            immr->im_brgc5 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 5)
-            immr->im_brgc6 |=  CPM_BRG_RST;
-            immr->im_brgc6 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 6)
-            immr->im_brgc7 |=  CPM_BRG_RST;
-            immr->im_brgc7 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 7)
-            immr->im_brgc8 |=  CPM_BRG_RST;
-            immr->im_brgc8 &= ~CPM_BRG_RST;
+            lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
 #       endif
+	
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+        /* 
+         * Set reset on MCLK BRG
+         */
+#       if (MCLK_BRG == 0)
+            *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+            *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+            *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+            *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+            *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+            *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+            *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+            *IM_BRGC8 = mclk_brg;
+#       endif
+
+        /* 
+         * Set reset on SCLK BRG
+         */
+#       if (SCLK_BRG == 0)
+            *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+            *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+            *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+            *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+            *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+            *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+            *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+            *IM_BRGC8 = sclk_brg;
+#       endif
+
+        /* 
+         * Set reset on LRCLK BRG
+         */
+#       if (LRCLK_BRG == 0)
+            *IM_BRGC1 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+            *IM_BRGC2 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+            *IM_BRGC3 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+            *IM_BRGC4 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+            *IM_BRGC5 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+            *IM_BRGC6 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+            *IM_BRGC7 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+            *IM_BRGC8 = lrclk_brg;
+#       endif
+	
+        /* 
+         * Clear reset on MCLK BRG
+         */
+#       if (MCLK_BRG == 0)
+            *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 1)
+            *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 2)
+            *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 3)
+            *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 4)
+            *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 5)
+            *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 6)
+            *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 7)
+            *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+
+        /* 
+         * Clear reset on SCLK BRG
+         */
+#       if (SCLK_BRG == 0)
+            *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 1)
+            *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 2)
+            *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 3)
+            *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 4)
+            *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 5)
+            *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 6)
+            *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 7)
+            *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+
+        /* 
+         * Clear reset on LRCLK BRG
+         */
+#       if (LRCLK_BRG == 0)
+            *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 1)
+            *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 2)
+            *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 3)
+            *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 4)
+            *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 5)
+            *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 6)
+            *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 7)
+            *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+	
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+            enable_interrupts();
+	}
 #   else
         /*
          * Reset the clocks
@@ -536,99 +665,99 @@ void Daq_Start_Clocks(int sample_rate)
 #ifdef TIGHTEN_UP_BRG_TIMING
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 
-    uint          mclk_brg;       /* MCLK  BRG value */
-    uint          sclk_brg;       /* SCLK  BRG value */
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
+    register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
     uint          lrclk_brg;      /* LRCLK BRG value */
-    uint          temp_lrclk_brg; /* Temporary LRCLK BRG value */
-    uint	  real_lrclk_brg; /* Permanent LRCLK BRG value */
     unsigned long flags;          /* Interrupt flags */
     uint          sclk_cnt;       /* SCLK count */
     uint          delay_cnt;      /* Delay count */
 #endif
 
 #   ifdef TIGHTEN_UP_BRG_TIMING
-        /*
+        /* 
          * Obtain the enabled MCLK BRG value
          */
 #       if (MCLK_BRG == 0)
-            mclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 1)
-            mclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 2)
-            mclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 3)
-            mclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 4)
-            mclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 5)
-            mclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 6)
-            mclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (MCLK_BRG == 7)
-            mclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 
-        /*
+        /* 
          * Obtain the enabled SCLK BRG value
          */
 #       if (SCLK_BRG == 0)
-            sclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 1)
-            sclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 2)
-            sclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 3)
-            sclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 4)
-            sclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 5)
-            sclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 6)
-            sclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (SCLK_BRG == 7)
-            sclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 
-        /*
+        /* 
          * Obtain the enabled LRCLK BRG value
          */
 #       if (LRCLK_BRG == 0)
-            lrclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 1)
-            lrclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 2)
-            lrclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 3)
-            lrclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 4)
-            lrclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 5)
-            lrclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 6)
-            lrclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 #       if (LRCLK_BRG == 7)
-            lrclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+            lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
 #       endif
 
 	/* Save off the real LRCLK value */
@@ -639,7 +768,7 @@ void Daq_Start_Clocks(int sample_rate)
 
 	/* Compute the delay as a function of SCLK count */
         delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
-	if (sample_rate == 43402) {
+	if (DaqSampleRate == 43402) {
 	  delay_cnt++;
 	}
 
@@ -649,117 +778,129 @@ void Daq_Start_Clocks(int sample_rate)
         /* Insert the count */
 	temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;
 
-        /*
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+        /* 
          * Enable MCLK BRG
          */
 #       if (MCLK_BRG == 0)
-            immr->im_brgc1 = mclk_brg;
+            *IM_BRGC1 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 1)
-            immr->im_brgc2 = mclk_brg;
+            *IM_BRGC2 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 2)
-            immr->im_brgc3 = mclk_brg;
+            *IM_BRGC3 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 3)
-            immr->im_brgc4 = mclk_brg;
+            *IM_BRGC4 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 4)
-            immr->im_brgc5 = mclk_brg;
+            *IM_BRGC5 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 5)
-            immr->im_brgc6 = mclk_brg;
+            *IM_BRGC6 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 6)
-            immr->im_brgc7 = mclk_brg;
+            *IM_BRGC7 = mclk_brg;
 #       endif
 #       if (MCLK_BRG == 7)
-            immr->im_brgc8 = mclk_brg;
+            *IM_BRGC8 = mclk_brg;
 #       endif
 
-        /*
+        /* 
          * Enable SCLK BRG
          */
 #       if (SCLK_BRG == 0)
-            immr->im_brgc1 = sclk_brg;
+            *IM_BRGC1 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 1)
-            immr->im_brgc2 = sclk_brg;
+            *IM_BRGC2 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 2)
-            immr->im_brgc3 = sclk_brg;
+            *IM_BRGC3 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 3)
-            immr->im_brgc4 = sclk_brg;
+            *IM_BRGC4 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 4)
-            immr->im_brgc5 = sclk_brg;
+            *IM_BRGC5 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 5)
-            immr->im_brgc6 = sclk_brg;
+            *IM_BRGC6 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 6)
-            immr->im_brgc7 = sclk_brg;
+            *IM_BRGC7 = sclk_brg;
 #       endif
 #       if (SCLK_BRG == 7)
-            immr->im_brgc8 = sclk_brg;
+            *IM_BRGC8 = sclk_brg;
 #       endif
 
-        /*
+        /* 
          * Enable LRCLK BRG (1st time - temporary)
          */
 #       if (LRCLK_BRG == 0)
-             immr->im_brgc1 = temp_lrclk_brg;
+            *IM_BRGC1 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 1)
-             immr->im_brgc2 = temp_lrclk_brg;
+            *IM_BRGC2 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 2)
-             immr->im_brgc3 = temp_lrclk_brg;
+            *IM_BRGC3 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 3)
-             immr->im_brgc4 = temp_lrclk_brg;
+            *IM_BRGC4 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 4)
-             immr->im_brgc5 = temp_lrclk_brg;
+            *IM_BRGC5 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 5)
-             immr->im_brgc6 = temp_lrclk_brg;
+            *IM_BRGC6 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 6)
-             immr->im_brgc7 = temp_lrclk_brg;
+            *IM_BRGC7 = temp_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 7)
-             immr->im_brgc8 = temp_lrclk_brg;
+            *IM_BRGC8 = temp_lrclk_brg;
 #       endif
-
-        /*
+	
+        /* 
          * Enable LRCLK BRG (2nd time - permanent)
          */
 #       if (LRCLK_BRG == 0)
-             immr->im_brgc1 = real_lrclk_brg;
+            *IM_BRGC1 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 1)
-             immr->im_brgc2 = real_lrclk_brg;
+            *IM_BRGC2 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 2)
-             immr->im_brgc3 = real_lrclk_brg;
+            *IM_BRGC3 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 3)
-             immr->im_brgc4 = real_lrclk_brg;
+            *IM_BRGC4 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 4)
-             immr->im_brgc5 = real_lrclk_brg;
+            *IM_BRGC5 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 5)
-             immr->im_brgc6 = real_lrclk_brg;
+            *IM_BRGC6 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 6)
-             immr->im_brgc7 = real_lrclk_brg;
+            *IM_BRGC7 = real_lrclk_brg;
 #       endif
 #       if (LRCLK_BRG == 7)
-             immr->im_brgc8 = real_lrclk_brg;
+            *IM_BRGC8 = real_lrclk_brg;
 #       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+        }
 #   else
         /*
          * Enable the clocks

board/sacsng/clkinit.h

@@ -61,6 +61,9 @@
                                  /* The 8260 (Mask B.3) seems to have     */
                                  /* problems generating LRCLK from SCLK   */
 
+#define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
+				   /* to wait for the clock to stabilize  */
+
 #define CPM_CLK      (gd->bd->bi_cpmfreq)
 #define DFBRG        4
 #define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
@@ -80,6 +83,15 @@
 #define CPM_BRG_EXTC_CLK5       2
 #define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5
 
+#define IM_BRGC1 ((uint *)0xf00119f0)
+#define IM_BRGC2 ((uint *)0xf00119f4)
+#define IM_BRGC3 ((uint *)0xf00119f8)
+#define IM_BRGC4 ((uint *)0xf00119fc)
+#define IM_BRGC5 ((uint *)0xf00115f0)
+#define IM_BRGC6 ((uint *)0xf00115f4)
+#define IM_BRGC7 ((uint *)0xf00115f8)
+#define IM_BRGC8 ((uint *)0xf00115fc)
+
 /*
  * External declarations
  */
@@ -105,7 +117,6 @@ extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
 extern uint Daq_BRG_Rate(uint brg);
 
 extern uint Daq_Get_SampleRate(void);
-extern uint Daq_Set_SampleRate(uint rate, uint force);
 
 extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
 extern void Daq_Stop_Clocks(void);

board/sacsng/sacsng.c

@@ -26,7 +26,6 @@
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>
-/*NO// #include <memtest.h> */
 #include <i2c.h>
 #include <spi.h>
 
@@ -486,9 +485,25 @@ int misc_init_r(void)
 	}
     }
 
+    /* 
+     * Stop the clocks and wait for at least 1 LRCLK period
+     * to make sure the clocking has really stopped.
+     */
+    Daq_Stop_Clocks();
+    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+    /*
+     * Initialize the clocks with the new rates
+     */
     Daq_Init_Clocks(sample_rate, sample_64x);
     sample_rate = Daq_Get_SampleRate();
+
+    /*
+     * Start the clocks and wait for at least 1 LRCLK period
+     * to make sure the clocking has become stable.
+     */
     Daq_Start_Clocks(sample_rate);
+    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
 
     sprintf(str_buf, "%d", sample_rate);
     setenv("DaqSampleRate", str_buf);
@@ -792,10 +807,12 @@ void spi_dac_chipsel(int cs)
  * chip selects: it calls the appropriate function to control the SPI
  * chip selects.
  */
-spi_chipsel_type spi_chipsel[2] = {
+spi_chipsel_type spi_chipsel[] = {
 	spi_adc_chipsel,
 	spi_dac_chipsel
 };
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
 #endif /* CFG_CMD_SPI */
 
 #endif /* CONFIG_MISC_INIT_R */

common/cmd_elf.c

@@ -111,7 +111,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/* Check to see if we need to tftp the image ourselves before starting */
 
 	if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) {
-		if (NetLoop (TFTP) == 0)
+		if (NetLoop (TFTP) <= 0)
 			return 1;
 		printf ("Automatic boot of VxWorks image at address 0x%08lx ... \n", addr);
 	}

common/cmd_fdc.c

@@ -173,19 +173,35 @@ const static FD_GEO_STRUCT floppy_type[2] = {
 
 static FDC_COMMAND_STRUCT cmd; /* global command struct */
 
+/* If the boot drive number is undefined, we assume it's drive 0             */
+#ifndef CFG_FDC_DRIVE_NUMBER
+#define CFG_FDC_DRIVE_NUMBER 0
+#endif
+
+/* Hardware access */
+#ifndef CFG_ISA_IO_STRIDE
+#define CFG_ISA_IO_STRIDE 1
+#endif
+
+#ifndef CFG_ISA_IO_OFFSET
+#define CFG_ISA_IO_OFFSET 0
+#endif
+
+
 /* Supporting Functions */
 /* reads a Register of the FDC */
 unsigned char read_fdc_reg(unsigned int addr)
 {
-	volatile unsigned char *val = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS | addr);
-	return val[0];
+	volatile unsigned char *val = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + (addr * CFG_ISA_IO_STRIDE) + CFG_ISA_IO_OFFSET);
+        
+	return val [0];
 }
 
 /* writes a Register of the FDC */
 void write_fdc_reg(unsigned int addr, unsigned char val)
 {
-		volatile unsigned char *tmp = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS | addr);
-		tmp[0]=val;
+        volatile unsigned char *tmp = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + (addr * CFG_ISA_IO_STRIDE) + CFG_ISA_IO_OFFSET);
+	tmp[0]=val;
 }
 
 /* waits for an interrupt (polling) */
@@ -263,7 +279,8 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 	head = sect / pFG->sect; /* head nr */
 	sect =  sect % pFG->sect; /* remaining blocks */
 	sect++; /* sectors are 1 based */
-	PRINTF("Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",track,head,sect,pCMD->drive,pCMD->blnr);
+	PRINTF("Cmd 0x%02x Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",pCMD->cmd[0],track,head,sect,pCMD->drive,pCMD->blnr);
+
 	if(head|=0) { /* max heads = 2 */
 		pCMD->cmd[DRIVE]=pCMD->drive | 0x04; /* head 1 */
 		pCMD->cmd[HEAD]=(unsigned char) head; /* head register */
@@ -538,20 +555,20 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 		select_fdc_drive(pCMD);
 		pCMD->blnr=0; /* set to the 1st block */
 		if(fdc_recalibrate(pCMD,pFG)==FALSE)
-			break;
+			continue;
 		if((pCMD->result[STATUS_0]&0x10)==0x10)
-			break;
+			continue;
 		/* ok drive connected check for disk */
 		state|=(1<<drives);
 		pCMD->blnr=pFG->size; /* set to the last block */
 		if(fdc_seek(pCMD,pFG)==FALSE)
-			break;
+			continue;
 		pCMD->blnr=0; /* set to the 1st block */
 		if(fdc_recalibrate(pCMD,pFG)==FALSE)
-			break;
+			continue;
 		pCMD->cmd[COMMAND]=FDC_CMD_READ_ID;
 		if(fdc_issue_cmd(pCMD,pFG)==FALSE)
-			break;
+			continue;
 		state|=(0x10<<drives);
 	}
 	stop_fdc_drive(pCMD);
@@ -575,12 +592,16 @@ int fdc_setup(FDC_COMMAND_STRUCT *pCMD,	FD_GEO_STRUCT *pFG)
 {
 
 	int i;
+
+#ifdef CFG_FDC_HW_INIT
+        fdc_hw_init ();
+#endif
 	/* first, we reset the FDC via the DOR */
 	write_fdc_reg(FDC_DOR,0x00);
 	for(i=0; i<255; i++) /* then we wait some time */
 		udelay(500);
 	/* then, we clear the reset in the DOR */
-	pCMD->drive=0;
+	pCMD->drive=CFG_FDC_DRIVE_NUMBER;
 	select_fdc_drive(pCMD);
 	/* initialize the CCR */
 	write_fdc_reg(FDC_CCR,pFG->rate);
@@ -602,7 +623,7 @@ int fdc_setup(FDC_COMMAND_STRUCT *pCMD,	FD_GEO_STRUCT *pFG)
 	}
 	/* assuming drive 0 for rest of configuration
 	 * issue the configure command */
-	pCMD->drive=0;
+	pCMD->drive=CFG_FDC_DRIVE_NUMBER;
 	select_fdc_drive(pCMD);
 	pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
 	if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
@@ -641,11 +662,11 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	switch (argc) {
 	case 1:
 		addr = CFG_LOAD_ADDR;
-		boot_drive=0; /* default boot from drive 0 */
+		boot_drive=CFG_FDC_DRIVE_NUMBER; 
 		break;
 	case 2:
 		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_drive=0; /* default boot from drive 0 */
+		boot_drive=CFG_FDC_DRIVE_NUMBER;
 		break;
 	case 3:
 		addr = simple_strtoul(argv[1], NULL, 16);

common/cmd_log.c

@@ -92,7 +92,7 @@ void logbuff_log(char *msg)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	if (gd->flags & GD_FLG_RELOC) {
+	if ((gd->flags & GD_FLG_RELOC)&&(getenv ("logstart") != NULL)) {
 		logbuff_printk(msg);
 	} else {
 		puts(msg);
@@ -109,10 +109,10 @@ void logbuff_reset (void)
 		ext_tag=(unsigned long *)(log_buf)-3;
 		ext_log_start=(unsigned long *)(log_buf)-2;
 		ext_logged_chars=(unsigned long *)(log_buf)-1;
-//		if (*ext_tag!=LOGBUFF_MAGIC) {
+/*		if (*ext_tag!=LOGBUFF_MAGIC) {	*/
 			logged_chars=log_start=0;
 			*ext_tag=LOGBUFF_MAGIC;
-//		}
+/*		}	*/
 		log_size=logged_chars;
 	}
 }

common/cmd_net.c

@@ -132,12 +132,16 @@ netboot_common (int proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
 		return 1;
 	}
 
-	if ((size = NetLoop(proto)) == 0)
+	if ((size = NetLoop(proto)) < 0)
 		return 1;
 
 	/* NetLoop ok, update environment */
 	netboot_update_env();
 
+	/* done if no file was loaded (no errors though) */
+	if (size == 0)
+		return 0;
+
 	/* flush cache */
 	flush_cache(load_addr, size);
 

common/cmd_nvedit.c

@@ -42,6 +42,7 @@
 #include <common.h>
 #include <command.h>
 #include <environment.h>
+#include <watchdog.h>
 #include <cmd_nvedit.h>
 #include <linux/stddef.h>
 #include <asm/byteorder.h>
@@ -459,6 +460,8 @@ char *getenv (uchar *name)
 {
 	int i, nxt;
 
+	WATCHDOG_RESET();
+
 	for (i=0; env_get_char(i) != '\0'; i=nxt+1) {
 		int val;
 

common/cmd_spi.c

@@ -32,14 +32,20 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_SPI)
 
-#define MAX_SPI_BYTES	32	/* max number of bytes we can handle */
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#ifndef MAX_SPI_BYTES
+#   define MAX_SPI_BYTES 32	/* Maximum number of bytes we can handle */
+#endif
 
 /*
  * External table of chip select functions (see the appropriate board
  * support for the actual definition of the table).
  */
 extern spi_chipsel_type spi_chipsel[];
-
+extern int spi_chipsel_cnt;
 
 /*
  * Values from last command.
@@ -60,7 +66,7 @@ static uchar din[MAX_SPI_BYTES];
  * The command prints out the hexadecimal string received via SPI.
  */
 
-int do_spi (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char  *cp = 0;
 	uchar tmp;
@@ -78,26 +84,38 @@ int do_spi (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 			device = simple_strtoul(argv[1], NULL, 10);
 		if (argc >= 3)
 			bitlen = simple_strtoul(argv[2], NULL, 10);
-		if (argc >= 4)
-		cp = argv[3];
-		for(j = 0; *cp; j++, cp++) {
-			tmp = *cp - '0';
-			if(tmp > 9)
-				tmp -= ('A' - '0') - 10;
-			if(tmp > 15)
-				tmp -= ('a' - 'A');
-			if(tmp > 15) {
-				printf("Conversion error on %c, bailing out.\n", *cp);
-				break;
+		if (argc >= 4) {
+			cp = argv[3];
+			for(j = 0; *cp; j++, cp++) {
+				tmp = *cp - '0';
+				if(tmp > 9)
+					tmp -= ('A' - '0') - 10;
+				if(tmp > 15)
+					tmp -= ('a' - 'A');
+				if(tmp > 15) {
+					printf("Hex conversion error on %c, giving up.\n", *cp);
+					return 1;
+				}
+				if((j % 2) == 0)
+					dout[j / 2] = (tmp << 4);
+				else
+					dout[j / 2] |= tmp;
 			}
-			if((j % 2) == 0)
-				dout[j / 2] = (tmp << 4);
-			else
-				dout[j / 2] |= tmp;
 		}
 	}
 
-printf("spi_chipsel[%d] = %08X\n", device, (uint)spi_chipsel[device]);
+	if ((device < 0) || (device >=  spi_chipsel_cnt)) {
+		printf("Invalid device %d, giving up.\n", device);
+		return 1;
+	} 
+	if ((bitlen < 0) || (bitlen >  (MAX_SPI_BYTES * 8))) {
+		printf("Invalid bitlen %d, giving up.\n", bitlen);
+		return 1;
+	} 
+
+	debug ("spi_chipsel[%d] = %08X\n",
+		device, (uint)spi_chipsel[device]);
+
 	if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) {
 		printf("Error with the SPI transaction.\n");
 		rcode = 1;
@@ -113,4 +131,3 @@ printf("spi_chipsel[%d] = %08X\n", device, (uint)spi_chipsel[device]);
 }
 
 #endif	/* CFG_CMD_SPI */
-

common/command.c

@@ -46,6 +46,7 @@
 
 #include <cmd_eeprom.h>
 #include <cmd_i2c.h>
+#include <cmd_spi.h>
 #include <cmd_immap.h>
 #include <cmd_rtc.h>
 
@@ -316,6 +317,7 @@ cmd_tbl_t cmd_tbl[] = {
 	CMD_TBL_MISC		/* sleep */
 	CMD_TBL_SMCINFO
 	CMD_TBL_SPIINFO
+	CMD_TBL_SPI
 	CMD_TBL_STACK
 	CMD_TBL_STEP
 	CMD_TBL_TFTPB

common/devices.c

@@ -26,7 +26,12 @@
 #include <stdarg.h>
 #include <malloc.h>
 #include <devices.h>
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
+#endif
 
 list_t devlist = 0;
 device_t *stdio_devices[] = { NULL, NULL, NULL };

common/soft_spi.c

@@ -29,9 +29,6 @@
 
 #if defined(CONFIG_SOFT_SPI)
 
-#define DEBUG_SPI
-
-
 /*-----------------------------------------------------------------------
  * Definitions
  */

common/spartan2.c

@@ -35,7 +35,7 @@
 #endif
 
 #undef CFG_FPGA_CHECK_BUSY
-#define CFG_FPGA_PROG_FEEDBACK
+#undef CFG_FPGA_PROG_FEEDBACK
 
 /* Note: The assumption is that we cannot possibly run fast enough to
  * overrun the device (the Slave Parallel mode can free run at 50MHz).
@@ -438,14 +438,150 @@ static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
 
 static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 {
-	printf ("%s: Slave Serial Loading is still unsupported\n",
-			__FUNCTION__);
-	return FPGA_FAIL;
+        int ret_val = FPGA_FAIL;	/* assume the worst */
+	Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
+        int i;
+        char  val;
+        
+	PRINTF ("%s: start with interface functions @ 0x%p\n",
+			__FUNCTION__, fn);
+
+	if (fn) {
+		size_t bytecount = 0;
+		unsigned char *data = (unsigned char *) buf;
+		int cookie = desc->cookie;	/* make a local copy */
+		unsigned long ts;		/* timestamp */
+
+		PRINTF ("%s: Function Table:\n"
+				"ptr:\t0x%p\n"
+				"struct: 0x%p\n"
+				"pgm:\t0x%p\n"
+				"init:\t0x%p\n"
+				"clk:\t0x%p\n"
+				"wr:\t0x%p\n"
+				"done:\t0x%p\n\n",
+				__FUNCTION__, &fn, fn, fn->pgm, fn->init, 
+				fn->clk, fn->wr, fn->done); 
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		printf ("Loading FPGA Device %d...\n", cookie);
+#endif
+
+		/*
+		 * Run the pre configuration function if there is one.
+		 */
+		if (*fn->pre) {
+			(*fn->pre) (cookie);
+		}
+
+		/* Establish the initial state */
+		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */
+
+                /* Wait for INIT state (init low)                            */
+		ts = get_timer (0);		/* get current time */
+		do {
+			CONFIG_FPGA_DELAY ();
+			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
+				puts ("** Timeout waiting for INIT to start.\n");
+				return FPGA_FAIL;
+			}
+		} while (!(*fn->init) (cookie));
+                
+		/* Get ready for the burn */
+		CONFIG_FPGA_DELAY ();
+		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */
+
+		ts = get_timer (0);		/* get current time */
+		/* Now wait for INIT to go high */
+		do {
+			CONFIG_FPGA_DELAY ();
+			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
+				puts ("** Timeout waiting for INIT to clear.\n");
+				return FPGA_FAIL;
+			}
+		} while ((*fn->init) (cookie));
+
+		/* Load the data */
+		while (bytecount < bsize) {
+                    
+                        /* Xilinx detects an error if INIT goes low (active)
+                           while DONE is low (inactive) */
+                        if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+                                puts ("** CRC error during FPGA load.\n");
+                                return (FPGA_FAIL);
+                        }
+                        val = data [bytecount ++];
+                        i = 8;
+                        do {
+                                /* Deassert the clock */
+                                (*fn->clk) (FALSE, TRUE, cookie);
+                                CONFIG_FPGA_DELAY ();
+                                /* Write data */
+                                (*fn->wr) ((val < 0), TRUE, cookie);
+                                CONFIG_FPGA_DELAY ();
+                                /* Assert the clock */
+                                (*fn->clk) (TRUE, TRUE, cookie);
+                                CONFIG_FPGA_DELAY ();
+                                val <<= 1;
+                                i --;
+                        } while (i > 0);
+                        
+#ifdef CFG_FPGA_PROG_FEEDBACK
+			if (bytecount % (bsize / 40) == 0)
+				putc ('.');		/* let them know we are alive */
+#endif
+		}
+
+		CONFIG_FPGA_DELAY ();
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		putc ('\n');			/* terminate the dotted line */
+#endif
+
+		/* now check for done signal */
+		ts = get_timer (0);		/* get current time */
+		ret_val = FPGA_SUCCESS;
+                (*fn->wr) (TRUE, TRUE, cookie);
+
+		while (! (*fn->done) (cookie)) {
+			/* XXX - we should have a check in here somewhere to
+			 * make sure we aren't busy forever... */
+
+			CONFIG_FPGA_DELAY ();
+			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			CONFIG_FPGA_DELAY ();
+			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+
+                        putc ('*');
+                        
+			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
+				puts ("** Timeout waiting for DONE to clear.\n");
+				ret_val = FPGA_FAIL;
+				break;
+			}
+		}
+		putc ('\n');			/* terminate the dotted line */
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		if (ret_val == FPGA_SUCCESS) {
+			puts ("Done.\n");
+		}
+		else {
+			puts ("Fail.\n");
+		}
+#endif
+
+	} else {
+		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+	}
+
+	return ret_val;
 }
 
 static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 {
-	printf ("%s: Slave Serial Dumping is still unsupported\n",
+        /* Readback is only available through the Slave Parallel and         */
+        /* boundary-scan interfaces.                                         */
+	printf ("%s: Slave Serial Dumping is unavailable\n",
 			__FUNCTION__);
 	return FPGA_FAIL;
 }
@@ -453,12 +589,59 @@ static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan2_Slave_Serial_fns *fn =
+	Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn =
 			(Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns);
 
 	if (fn) {
-		printf ("%s: Slave Serial Loading is still unsupported\n",
-				__FUNCTION__);
+		ulong addr;
+
+		/* Get the relocated table address */
+		addr = (ulong) fn + reloc_offset;
+		fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr;
+
+		if (!fn_r->relocated) {
+
+			if (memcmp (fn_r, fn,
+						sizeof (Xilinx_Spartan2_Slave_Serial_fns))
+				== 0) {
+				/* good copy of the table, fix the descriptor pointer */
+				desc->iface_fns = fn_r;
+			} else {
+				PRINTF ("%s: Invalid function table at 0x%p\n",
+						__FUNCTION__, fn_r);
+				return FPGA_FAIL;
+			}
+
+			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+					desc);
+
+			addr = (ulong) (fn->pre) + reloc_offset;
+			fn_r->pre = (Xilinx_pre_fn) addr;
+
+			addr = (ulong) (fn->pgm) + reloc_offset;
+			fn_r->pgm = (Xilinx_pgm_fn) addr;
+
+			addr = (ulong) (fn->init) + reloc_offset;
+			fn_r->init = (Xilinx_init_fn) addr;
+
+			addr = (ulong) (fn->done) + reloc_offset;
+			fn_r->done = (Xilinx_done_fn) addr;
+
+			addr = (ulong) (fn->clk) + reloc_offset;
+			fn_r->clk = (Xilinx_clk_fn) addr;
+
+			addr = (ulong) (fn->wr) + reloc_offset;
+			fn_r->wr = (Xilinx_wr_fn) addr;
+
+			fn_r->relocated = TRUE;
+
+		} else {
+			/* this table has already been moved */
+			/* XXX - should check to see if the descriptor is correct */
+			desc->iface_fns = fn_r;
+		}
+
+		ret_val = FPGA_SUCCESS;
 	} else {
 		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
 	}

config.mk

@@ -116,7 +116,7 @@ endif
 AFLAGS_DEBUG := -Wa,-gstabs
 AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
 
-LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
+LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
 
 # Location of a usable BFD library, where we define "usable" as
 # "built for ${HOST}, supports ${TARGET}".  Sensible values are

cpu/74xx_7xx/cache.S

@@ -1,5 +1,5 @@
 #include <config.h>
-#include <mpc74xx.h>
+#include <74xx_7xx.h>
 #include <version.h>
 
 #include <ppc_asm.tmpl>

cpu/arm920t/speed.c

@@ -42,7 +42,7 @@
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * CONFIG_PLL_INPUT_FREQ should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  *
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -64,7 +64,7 @@ static ulong get_PLLCLK(int pllreg)
     p = ((r & 0x003F0) >> 4) + 2;
     s = r & 0x3;
 
-    return((CONFIG_PLL_INPUT_FREQ * m) / (p << s));
+    return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
 }
 
 /* return FCLK frequency */

cpu/mpc8260/interrupts.c

@@ -29,6 +29,9 @@
 #include <mpc8260.h>
 #include <mpc8260_irq.h>
 #include <asm/processor.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
 
 /****************************************************************************/
 
@@ -292,7 +295,7 @@ void timer_interrupt (struct pt_regs *regs)
 {
 #if defined(CONFIG_WATCHDOG) || defined(CFG_HYMOD_DBLEDS)
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-#endif							/* CONFIG_WATCHDOG */
+#endif	/* CONFIG_WATCHDOG */
 
 	/* Restore Decrementer Count */
 	set_dec (decrementer_count);
@@ -306,19 +309,19 @@ void timer_interrupt (struct pt_regs *regs)
 	if ((timestamp % CFG_HZ) == 0) {
 #if defined(CFG_CMA_LCD_HEARTBEAT)
 		extern void lcd_heartbeat (void);
-#endif							/* CFG_CMA_LCD_HEARTBEAT */
+#endif	/* CFG_CMA_LCD_HEARTBEAT */
 #if defined(CFG_HYMOD_DBLEDS)
 		volatile iop8260_t *iop = &immr->im_ioport;
 		static int shift = 0;
-#endif							/* CFG_HYMOD_DBLEDS */
+#endif	/* CFG_HYMOD_DBLEDS */
 
 #if defined(CFG_CMA_LCD_HEARTBEAT)
 		lcd_heartbeat ();
-#endif							/* CFG_CMA_LCD_HEARTBEAT */
+#endif	/* CFG_CMA_LCD_HEARTBEAT */
 
 #if defined(CONFIG_WATCHDOG)
 		reset_8260_watchdog (immr);
-#endif							/* CONFIG_WATCHDOG */
+#endif	/* CONFIG_WATCHDOG */
 
 #if defined(CFG_HYMOD_DBLEDS)
 		/* hymod daughter board LEDs */
@@ -326,9 +329,13 @@ void timer_interrupt (struct pt_regs *regs)
 			shift = 0;
 		iop->iop_pdatd =
 				(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
-#endif							/* CFG_HYMOD_DBLEDS */
+#endif	/* CFG_HYMOD_DBLEDS */
 	}
-#endif							/* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
+#endif	/* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
+
+#ifdef CONFIG_STATUS_LED
+	status_led_tick (timestamp);
+#endif	/* CONFIG_STATUS_LED */
 }
 
 /****************************************************************************/

cpu/mpc8xx/fec.c

@@ -76,6 +76,7 @@ int fec_initialize(bd_t *bis)
 	struct eth_device* dev;
 
 	dev = (struct eth_device*) malloc(sizeof *dev);
+	memset(dev, 0, sizeof *dev);
 
 	sprintf(dev->name, "FEC ETHERNET");
 	dev->iobase = 0;

cpu/mpc8xx/scc.c

@@ -75,6 +75,7 @@ int scc_initialize(bd_t *bis)
 	struct eth_device* dev;
 
 	dev = (struct eth_device*) malloc(sizeof *dev);
+	memset(dev, 0, sizeof *dev);
 
 	sprintf(dev->name, "SCC ETHERNET");
 	dev->iobase = 0;

cpu/xscale/start.S

@@ -175,10 +175,11 @@ OSTIMER_BASE:	.word	0x40a00000
 #define OIER	0x1C
 
 	/* Clock Manager Registers					    */
+#ifdef CFG_CPUSPEED
 CC_BASE:	.word	0x41300000
 #define CCCR	0x00
 cpuspeed:	.word	CFG_CPUSPEED
-
+#endif
 	/* RS: ???							    */
 	.macro CPWAIT
 	mrc  p15,0,r0,c2,c0,0
@@ -194,10 +195,14 @@ cpu_init_crit:
 	mov	r1, #0x00
 	str	r1, [r0, #ICMR]
 
+#ifdef CFG_CPUSPEED
 	/* set clock speed */
 	ldr	r0, CC_BASE
 	ldr	r1, cpuspeed
 	str	r1, [r0, #CCCR]
+	mov	r0, #3
+	mcr	p14, 0, r0, c6, c0, 0
+#endif
 
 	/*
 	 * before relocating, we have to setup RAM timing

doc/README.commands

@@ -90,6 +90,7 @@ setdcr		6		# IBM 4XX DCR registers
 setenv		6
 smcinfo		3
 spiinfo		3
+sspi		4
 stack		5
 step		4
 tftpboot	4

include/cmd_confdefs.h

@@ -76,6 +76,7 @@
 #define CFG_CMD_HWFLOW	0x0000020000000000	/* RTS/CTS hw flow control	*/
 #define CFG_CMD_SAVES	0x0000040000000000	/* save S record dump		*/
 #define CFG_CMD_VFD	0x0000080000000000	/* Display bitmap on VFD display*/
+#define CFG_CMD_SPI	0x0000100000000000	/* SPI utility			*/
 
 #define CFG_CMD_ALL	0xFFFFFFFFFFFFFFFF	/* ALL commands			*/
 
@@ -110,7 +111,8 @@
 			CFG_CMD_SCSI	| \
 			CFG_CMD_SDRAM	| \
 			CFG_CMD_USB	| \
-			CFG_CMD_VFD	)
+			CFG_CMD_VFD	| \
+			CFG_CMD_SPI	)
 
 /* Default configuration
  */

include/cmd_spi.h

@@ -38,7 +38,7 @@
   <dout>    - Hexadecimal string that gets sent\n" \
 ),
 
-int do_spi       (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+int do_spi       (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 #else
 #define CMD_TBL_SPI

include/common.h

@@ -156,6 +156,7 @@ int	misc_init_r   (void);
 
 /* $(BOARD)/$(BOARD).c */
 void	reset_phy     (void);
+void    fdc_hw_init   (void);
 
 /* $(BOARD)/eeprom.c */
 void eeprom_init  (void);

include/configs/ELPPC.h

@@ -310,7 +310,7 @@
 
 /*
  * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
+ * look in include/74xx_7xx.h for the defines used here
  */
 
 #define CFG_L2

include/configs/EVB64260.h

@@ -400,7 +400,7 @@
 
 /*-----------------------------------------------------------------------
  * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
+ * look in include/74xx_7xx.h for the defines used here
  */
 
 #define CFG_L2

include/configs/KUP4K.h

@@ -41,7 +41,7 @@
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#define CONFIG_BAUDRATE		9600	/* console baudrate		*/
 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else

include/configs/LANTEC.h

@@ -100,6 +100,7 @@
 					     & ~CFG_CMD_PCI	\
 					     & ~CFG_CMD_PCMCIA	\
 					     & ~CFG_CMD_SCSI	\
+					     & ~CFG_CMD_SPI	\
 					     & ~CFG_CMD_USB	\
 					     & ~CFG_CMD_VFD	)
 

include/configs/MPC8260ADS.h

@@ -120,6 +120,7 @@
 				 CFG_CMD_PCI	| \
 				 CFG_CMD_PCMCIA | \
 				 CFG_CMD_SCSI	| \
+				 CFG_CMD_SPI	| \
 				 CFG_CMD_VFD	| \
 				 CFG_CMD_USB	) )
 

include/configs/ZUMA.h

@@ -344,7 +344,7 @@
 
 /*-----------------------------------------------------------------------
  * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
+ * look in include/74xx_7xx.h for the defines used here
  */
 
 #define CFG_L2

include/configs/ep8260.h

@@ -284,6 +284,7 @@
 					~CFG_CMD_PCI    & \
 					~CFG_CMD_PCMCIA & \
 					~CFG_CMD_SCSI   & \
+					~CFG_CMD_SPI	& \
 					~CFG_CMD_USB	& \
 					~CFG_CMD_VFD	& \
 					~CFG_CMD_DTT )

include/configs/hymod.h

@@ -149,6 +149,7 @@
 					CFG_CMD_PCI	| \
 					CFG_CMD_USB	| \
 					CFG_CMD_SCSI	| \
+					CFG_CMD_SPI	| \
 					CFG_CMD_VFD	| \
 					CFG_CMD_DTT	) )
 

include/configs/sacsng.h

@@ -252,10 +252,12 @@
 
 
 /*
- * select SPI support configuration
+ * Select SPI support configuration
  */
-#define  CONFIG_SOFT_SPI		/* enable SPI driver		*/
-
+#define CONFIG_SOFT_SPI		/* Enable SPI driver */
+#define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */
+#undef  DEBUG_SPI               /* Disable SPI debugging */  
+ 
 /*
  * Software (bit-bang) SPI driver configuration
  */
@@ -274,7 +276,7 @@
                         else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
 #define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
                         else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
-#define SPI_DELAY	/*udelay(1)*/	/* 1/2 SPI clock duration */
+#define SPI_DELAY                       /* No delay is needed */
 #endif /* CONFIG_SOFT_SPI */
 
 
@@ -485,6 +487,11 @@
 #define CFG_PROMPT_HUSH_PS2     "> "
 #endif
 
+/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
+ * of an image is printed by image commands like bootm or iminfo.
+ */
+#define CONFIG_TIMESTAMP
+
 /* What U-Boot subsytems do you want enabled? */
 #ifdef CONFIG_ETHER_ON_FCC
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
@@ -544,6 +551,7 @@
 #define CFG_LOAD_ADDR		0x400000   /* default load address */
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
 
+#define CFG_ALT_MEMTEST                 /* Select full-featured memory test */
 #define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
 					/* the exception vector table */
 					/* to the end of the DRAM  */

include/configs/sbc8260.h

@@ -294,9 +294,7 @@
  * is on the board edge side of both the LED strip and the DS0-DS7
  * switch.
  */
-#if 0
-# define CONFIG_MISC_INIT_R
-#endif
+#undef	CONFIG_MISC_INIT_R
 
 /* Set to a positive value to delay for running BOOTCOMMAND */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
@@ -312,6 +310,43 @@
 # define DEBUG_BOOTKEYS		0
 #endif
 
+/* Define this to contain any number of null terminated strings that
+ * will be part of the default enviroment compiled into the boot image.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serverip=192.168.123.201\0" \
+	"ipaddr=192.168.123.203\0" \
+	"reprog="\
+		"tftpboot 0x140000 /bdi2000/u-boot.bin; " \
+		"protect off 1:0; " \
+		"erase 1:0; " \
+		"cp.b 140000 40000000 $(filesize); " \
+		"protect on 1:0\0" \
+	"zapenv="\
+		"protect off 1:1; " \
+		"erase 1:1; " \
+		"protect on 1:1\0" \
+	"root-on-initrd="\
+		"setenv bootcmd "\
+		"version;" \
+		"echo;" \
+		"bootp;" \
+		"setenv bootargs root=/dev/ram0 rw " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+		"run boot-hook;" \
+		"bootm\0" \
+	"root-on-nfs="\
+		"setenv bootcmd "\
+		"version;" \
+		"echo;" \
+		"bootp;" \
+		"setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$(serverip):$(rootpath) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\\;" \
+		"run boot-hook;" \
+		"bootm\0" \
+	"boot-hook=echo boot-hook\0"
+
 /* Define a command string that is automatically executed when no character
  * is read on the console interface withing "Boot Delay" after reset.
  */
@@ -352,6 +387,16 @@
 /* Monitor Command Prompt */
 #define CFG_PROMPT		"=> "
 
+#undef  CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
+ * of an image is printed by image commands like bootm or iminfo.
+ */
+#define CONFIG_TIMESTAMP
+
 /* What U-Boot subsytems do you want enabled? */
 #ifdef CONFIG_ETHER_ON_FCC
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
@@ -405,9 +450,10 @@
 
 #define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
 
-#define CFG_LOAD_ADDR		0x140000   /* default load address */
+#define CFG_LOAD_ADDR		0x400000   /* default load address */
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
 
+#define CFG_ALT_MEMTEST			/* Select full-featured memory test */
 #define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
 					/* the exception vector table */
 					/* to the end of the DRAM  */

include/configs/smdk2400.h

@@ -43,7 +43,7 @@
 #define CONFIG_SMDK2400		1	/* on an SAMSUNG SMDK2400 Board */
 
 /* input clock of PLL */
-#define CONFIG_PLL_INPUT_FREQ	12000000 /* SMDK2400 has 12 MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000 /* SMDK2400 has 12 MHz input clock */
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/

include/configs/smdk2410.h

@@ -44,7 +44,7 @@
 #define CONFIG_SMDK2410		1	/* on a SAMSUNG SMDK2410 Board  */
 
 /* input clock of PLL */
-#define CONFIG_PLL_INPUT_FREQ	12000000/* the SMDK2410 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */
 
 
 #define USE_920T_MMU		1

include/configs/trab.h

@@ -42,7 +42,7 @@
 #undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz */
 
 /* input clock of PLL */
-#define CONFIG_PLL_INPUT_FREQ	12000000 /* TRAB has 12 MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 

include/lists.h

@@ -39,7 +39,7 @@ void    *ListGetPtrToItem(list_t list, int itemPosition);
 void    ListRemoveItem(list_t list, void *itemDestination, int itemPosition);
 void    ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove);
 
-#if 0
+#if 0	/* rarely ever used; kept here for reference just in case ... */
 void    ListDisposePtrList(list_t list);
 void    ListGetItem(list_t list, void *itemDestination, int itemPosition);
 void    ListReplaceItem(list_t list, void *ptrToItem, int itemPosition);
@@ -72,6 +72,6 @@ int     ListGetItemSize(list_t list);
 int     GetIntListFromParmInfo(va_list parmInfo, int numIntegers, list_t *integerList);
 int     ListInsertAfterItem(list_t list, void *ptrToItem, void *ptrToItemToInsertAfter, CompareFunction compareFunction);
 int     ListInsertBeforeItem(list_t list, void *ptrToItem, void *ptrToItemToInsertBefore, CompareFunction compareFunction);
-#endif 0
+#endif /* 0 */
 
 #endif	/* _LISTS_H_ */

include/mpc74xx.h

@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * mpc74xx.h
- *
- * MPC74xx specific definitions
- */
-
-#ifndef __MPC74XX_H__
-#define __MPC74XX_H__
-
-/*----------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET        0x0100      /* default system reset offset */
-
-/*----------------------------------------------------------------
- * l2cr values
- */
-#define l2cr 1017
-
-#define L2CR_L2E         0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
-#define L2CR_L2SIZ_2M    0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
-#define L2CR_L2SIZ_1M    0x30000000 /* ... 1MB */
-#define L2CR_L2SIZ_HM    0x20000000 /* ... 512K */
-#define L2CR_L2SIZ_QM    0x10000000 /* ... 256k */
-#define L2CR_L2CLK_1     0x02000000 /* bits 4-6 clock ratio div 1 */
-#define L2CR_L2CLK_1_5   0x04000000 /* bits 4-6 clock ratio div 1.5 */
-#define L2CR_L2CLK_2     0x08000000 /* bits 4-6 clock ratio div 2 */
-#define L2CR_L2CLK_2_5   0x0a000000 /* bits 4-6 clock ratio div 2.5 */
-#define L2CR_L2CLK_3     0x0c000000 /* bits 4-6 clock ratio div 3 */
-#define L2CR_L2CLK_3_5   0x06000000 /* bits 4-6 clock ratio div 3.5 */
-#define L2CR_L2CLK_4     0x0e000000 /* bits 4-6 clock ratio div 4 */
-#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
-#define L2CR_DO          0x00400000 /* bit 9 - enable caching of instr. in L2 */
-#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2WT        0x00080000 /* bit 12 - l2 write-through */
-#define L2CR_TS          0x00040000 /* bit 13 - test support on */
-#define L2CR_TS_OFF      -L2CR_TS   /* bit 13 - test support off */
-#define L2CR_L2OH_5      0x00000000 /* bits 14-15 - output hold time = short */
-#define L2CR_L2OH_1      0x00010000 /* bits 14-15 - output hold time = medium */
-#define L2CR_L2OH_INV    0x00020000 /* bits 14-15 - output hold time = long */
-#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
-
-/*----------------------------------------------------------------
- * BAT settings.  Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K             0x00000000
-#define BATU_BL_256K             0x00000004
-#define BATU_BL_512K             0x0000000c
-#define BATU_BL_1M               0x0000001c
-#define BATU_BL_2M               0x0000003c
-#define BATU_BL_4M               0x0000007c
-#define BATU_BL_8M               0x000000fc
-#define BATU_BL_16M              0x000001fc
-#define BATU_BL_32M              0x000003fc
-#define BATU_BL_64M              0x000007fc
-#define BATU_BL_128M             0x00000ffc
-#define BATU_BL_256M             0x00001ffc
-
-#define BATU_VS                  0x00000002
-#define BATU_VP                  0x00000001
-#define BATU_INVALID             0x00000000
-
-#define BATL_WRITETHROUGH        0x00000040	/* W */
-#define BATL_CACHEINHIBIT        0x00000020	/* I */
-#define BATL_COHERENT            0x00000010	/* M */
-#define BATL_GUARDED             0x00000008	/* G */
-
-#define BATL_NO_ACCESS           0x00000000
-#define BATL_RO                  0x00000001
-#define BATL_RW                  0x00000002
-
-#endif  /* __MPC74XX_H__ */

include/net.h

@@ -27,7 +27,12 @@
  *
  */
 
+#ifndef	CONFIG_EEPRO100
 #define PKTBUFSRX	4
+#else
+#define PKTBUFSRX	8
+#endif
+
 #define PKTALIGN	32
 
 typedef ulong		IPaddr_t;

include/spartan2.h

@@ -52,10 +52,12 @@ typedef struct {
 
 /* Slave Serial Implementation function table */
 typedef struct {
+	Xilinx_pre_fn	pre;
 	Xilinx_pgm_fn	pgm;
 	Xilinx_clk_fn	clk;
-	Xilinx_rdata_fn	rdata;
-	Xilinx_wdata_fn	wdata;
+	Xilinx_init_fn	init;
+	Xilinx_done_fn	done;
+	Xilinx_wr_fn	wr;
 	int           	relocated;
 } Xilinx_Spartan2_Slave_Serial_fns;
 

net/eth.c

@@ -229,7 +229,6 @@ int eth_init(bd_t *bis)
 		if (eth_current->init(eth_current, bis)) {
 			eth_current->state = ETH_STATE_ACTIVE;
 
-			printf("%s configured\n", eth_current->name);
 			return 1;
 		}
 

net/net.c

@@ -187,7 +187,7 @@ restart:
 	switch (net_check_prereq (protocol)) {
 	case 1:
 		/* network not configured */
-		return 0;
+		return (-1);
 
 #ifdef CONFIG_NET_MULTI
 	case 2:
@@ -257,7 +257,7 @@ restart:
 		if (ctrlc()) {
 		        eth_halt();
 			printf("\nAbort\n");
-			return 0;
+			return (-1);
 		}
 
 
@@ -295,7 +295,7 @@ restart:
 			return NetBootFileXferSize;
 
 		case NETLOOP_FAIL:
-			return 0;
+			return (-1);
 		}
 	}
 }

ppc_config.mk

@@ -22,3 +22,4 @@
 #
 
 PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
+PLATFORM_LDFLAGS  += -n