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* Vince Husovsky, 7 Nov 2002:

Browse Source 
Add "-n" to linker options to get rid of "Not enough room for
  program headers" problem

* Patch by David Mller, 05 Nov 2002
  Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
  so we can use an already existing name

* Patch by Pierre Aubert, 05 Nov 2002
  Hardware related improvements in FDC boot code

* Patch by Holger Schurig, 5 Nov 2002:
  Make the PXA really change it's frequency

* Patch by Pierre Aubert, 05 Nov 2002
  Add support for slave serial Spartan 2 FPGAs

* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
  drivers
This commit is contained in:
wdenk 2002-11-10 22:06:23 +00:00
parent 2a3cb02076
commit 7f6c2cbc2b
17 changed files with 302 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
CHANGELOG
View File

@ -2,6 +2,26 @@
Changes since for U-Boot 0.1.0:
======================================================================
* Vince Husovsky, 7 Nov 2002:
Add "-n" to linker options to get rid of "Not enough room for
program headers" problem
* Patch by David Müller, 05 Nov 2002
Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
so we can use an already existing name
* Patch by Pierre Aubert, 05 Nov 2002
Hardware relatied improvments in FDC boot code
* Patch by Holger Schurig, 5 Nov 2002:
Make the PXA really change it's frequency
* Patch by Pierre Aubert, 05 Nov 2002
Add support for slave serial Spartan 2 FPGAs
* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
drivers
* Add support for log buffer which can be passed to Linux kernel's
syslog mechanism; used especially for POST results.

35
README
View File

@ -266,6 +266,11 @@ Example: For a TQM823L module, all configuration settings are in
"include/configs/TQM823L.h".
Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
The following options need to be configured:
- CPU Type: Define exactly one of
@ -1523,10 +1528,6 @@ Note2: you must edit your u-boot.lds file to reflect this
configuration.
Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
Low Level (hardware related) configuration options:
- CFG_CACHELINE_SIZE:
@ -1538,6 +1539,32 @@ Low Level (hardware related) configuration options:
to be able to adjust the position of the IMMR
register after a reset.
- Floppy Disk Support:
CFG_FDC_DRIVE_NUMBER
the default drive number (default value 0)
CFG_ISA_IO_STRIDE
defines the spacing between fdc chipset registers
(default value 1)
CFG_ISA_IO_OFFSET
defines the offset of register from address. It
depends on which part of the data bus is connected to
the fdc chipset. (default value 0)
If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and
CFG_FDC_DRIVE_NUMBER are undefined, they take their
default value.
if CFG_FDC_HW_INIT is defined, then the function
fdc_hw_init() is called at the beginning of the FDC
setup. fdc_hw_init() must be provided by the board
source code. It is used to make hardware dependant
initializations.
- CFG_IMMR: Physical address of the Internal Memory Mapped
Register; DO NOT CHANGE! (11-4)
[MPC8xx systems only]

49
common/cmd_fdc.c
View File

@ -173,19 +173,35 @@ const static FD_GEO_STRUCT floppy_type[2] = {
static FDC_COMMAND_STRUCT cmd; /* global command struct */
/* If the boot drive number is undefined, we assume it's drive 0 */
#ifndef CFG_FDC_DRIVE_NUMBER
#define CFG_FDC_DRIVE_NUMBER 0
#endif
/* Hardware access */
#ifndef CFG_ISA_IO_STRIDE
#define CFG_ISA_IO_STRIDE 1
#endif
#ifndef CFG_ISA_IO_OFFSET
#define CFG_ISA_IO_OFFSET 0
#endif
/* Supporting Functions */
/* reads a Register of the FDC */
unsigned char read_fdc_reg(unsigned int addr)
{
volatile unsigned char *val = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS | addr);
return val[0];
volatile unsigned char *val = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + (addr * CFG_ISA_IO_STRIDE) + CFG_ISA_IO_OFFSET);
return val [0];
}
/* writes a Register of the FDC */
void write_fdc_reg(unsigned int addr, unsigned char val)
{
volatile unsigned char *tmp = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS | addr);
tmp[0]=val;
volatile unsigned char *tmp = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + (addr * CFG_ISA_IO_STRIDE) + CFG_ISA_IO_OFFSET);
tmp[0]=val;
}
/* waits for an interrupt (polling) */
@ -263,7 +279,8 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
head = sect / pFG->sect; /* head nr */
sect = sect % pFG->sect; /* remaining blocks */
sect++; /* sectors are 1 based */
PRINTF("Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",track,head,sect,pCMD->drive,pCMD->blnr);
PRINTF("Cmd 0x%02x Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",pCMD->cmd[0],track,head,sect,pCMD->drive,pCMD->blnr);
if(head|=0) { /* max heads = 2 */
pCMD->cmd[DRIVE]=pCMD->drive | 0x04; /* head 1 */
pCMD->cmd[HEAD]=(unsigned char) head; /* head register */
@ -538,20 +555,20 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
select_fdc_drive(pCMD);
pCMD->blnr=0; /* set to the 1st block */
if(fdc_recalibrate(pCMD,pFG)==FALSE)
break;
continue;
if((pCMD->result[STATUS_0]&0x10)==0x10)
break;
continue;
/* ok drive connected check for disk */
state|=(1<<drives);
pCMD->blnr=pFG->size; /* set to the last block */
if(fdc_seek(pCMD,pFG)==FALSE)
break;
continue;
pCMD->blnr=0; /* set to the 1st block */
if(fdc_recalibrate(pCMD,pFG)==FALSE)
break;
continue;
pCMD->cmd[COMMAND]=FDC_CMD_READ_ID;
if(fdc_issue_cmd(pCMD,pFG)==FALSE)
break;
continue;
state|=(0x10<<drives);
}
stop_fdc_drive(pCMD);
@ -575,12 +592,16 @@ int fdc_setup(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
{
int i;
#ifdef CFG_FDC_HW_INIT
fdc_hw_init ();
#endif
/* first, we reset the FDC via the DOR */
write_fdc_reg(FDC_DOR,0x00);
for(i=0; i<255; i++) /* then we wait some time */
udelay(500);
/* then, we clear the reset in the DOR */
pCMD->drive=0;
pCMD->drive=CFG_FDC_DRIVE_NUMBER;
select_fdc_drive(pCMD);
/* initialize the CCR */
write_fdc_reg(FDC_CCR,pFG->rate);
@ -602,7 +623,7 @@ int fdc_setup(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
}
/* assuming drive 0 for rest of configuration
* issue the configure command */
pCMD->drive=0;
pCMD->drive=CFG_FDC_DRIVE_NUMBER;
select_fdc_drive(pCMD);
pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
@ -641,11 +662,11 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
boot_drive=0; /* default boot from drive 0 */
boot_drive=CFG_FDC_DRIVE_NUMBER;
break;
case 2:
addr = simple_strtoul(argv[1], NULL, 16);
boot_drive=0; /* default boot from drive 0 */
boot_drive=CFG_FDC_DRIVE_NUMBER;
break;
case 3:
addr = simple_strtoul(argv[1], NULL, 16);

5
common/devices.c
View File

@ -26,7 +26,12 @@
#include <stdarg.h>
#include <malloc.h>
#include <devices.h>
#ifdef CONFIG_LOGBUFFER
#include <logbuff.h>
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
#endif
list_t devlist = 0;
device_t *stdio_devices[] = { NULL, NULL, NULL };

199
common/spartan2.c
View File

@ -35,7 +35,7 @@
#endif
#undef CFG_FPGA_CHECK_BUSY
#define CFG_FPGA_PROG_FEEDBACK
#undef CFG_FPGA_PROG_FEEDBACK
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
@ -438,14 +438,150 @@ static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is still unsupported\n",
__FUNCTION__);
return FPGA_FAIL;
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
int i;
char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
#ifdef CFG_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
return FPGA_FAIL;
}
} while (!(*fn->init) (cookie));
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
}
} while ((*fn->init) (cookie));
/* Load the data */
while (bytecount < bsize) {
/* Xilinx detects an error if INIT goes low (active)
while DONE is low (inactive) */
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
puts ("** CRC error during FPGA load.\n");
return (FPGA_FAIL);
}
val = data [bytecount ++];
i = 8;
do {
/* Deassert the clock */
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val < 0), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
#ifdef CFG_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
CONFIG_FPGA_DELAY ();
#ifdef CFG_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
(*fn->wr) (TRUE, TRUE, cookie);
while (! (*fn->done) (cookie)) {
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
putc ('*');
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
}
}
putc ('\n'); /* terminate the dotted line */
#ifdef CFG_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS) {
puts ("Done.\n");
}
else {
puts ("Fail.\n");
}
#endif
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is still unsupported\n",
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
printf ("%s: Slave Serial Dumping is unavailable\n",
__FUNCTION__);
return FPGA_FAIL;
}
@ -453,12 +589,59 @@ static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Serial_fns *fn =
Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn =
(Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns);
if (fn) {
printf ("%s: Slave Serial Loading is still unsupported\n",
__FUNCTION__);
ulong addr;
/* Get the relocated table address */
addr = (ulong) fn + reloc_offset;
fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr;
if (!fn_r->relocated) {
if (memcmp (fn_r, fn,
sizeof (Xilinx_Spartan2_Slave_Serial_fns))
== 0) {
/* good copy of the table, fix the descriptor pointer */
desc->iface_fns = fn_r;
} else {
PRINTF ("%s: Invalid function table at 0x%p\n",
__FUNCTION__, fn_r);
return FPGA_FAIL;
}
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
desc);
addr = (ulong) (fn->pre) + reloc_offset;
fn_r->pre = (Xilinx_pre_fn) addr;
addr = (ulong) (fn->pgm) + reloc_offset;
fn_r->pgm = (Xilinx_pgm_fn) addr;
addr = (ulong) (fn->init) + reloc_offset;
fn_r->init = (Xilinx_init_fn) addr;
addr = (ulong) (fn->done) + reloc_offset;
fn_r->done = (Xilinx_done_fn) addr;
addr = (ulong) (fn->clk) + reloc_offset;
fn_r->clk = (Xilinx_clk_fn) addr;
addr = (ulong) (fn->wr) + reloc_offset;
fn_r->wr = (Xilinx_wr_fn) addr;
fn_r->relocated = TRUE;
} else {
/* this table has already been moved */
/* XXX - should check to see if the descriptor is correct */
desc->iface_fns = fn_r;
}
ret_val = FPGA_SUCCESS;
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}

2
config.mk
View File

@ -116,7 +116,7 @@ endif
AFLAGS_DEBUG := -Wa,-gstabs
AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
# Location of a usable BFD library, where we define "usable" as
# "built for ${HOST}, supports ${TARGET}". Sensible values are

4
cpu/arm920t/speed.c
View File

@ -42,7 +42,7 @@
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_PLL_INPUT_FREQ should be defined as the input frequency of the PLL.
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
@ -64,7 +64,7 @@ static ulong get_PLLCLK(int pllreg)
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
return((CONFIG_PLL_INPUT_FREQ * m) / (p << s));
return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
}
/* return FCLK frequency */

1
cpu/mpc8xx/fec.c
View File

@ -76,6 +76,7 @@ int fec_initialize(bd_t *bis)
struct eth_device* dev;
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FEC ETHERNET");
dev->iobase = 0;

1
cpu/mpc8xx/scc.c
View File

@ -75,6 +75,7 @@ int scc_initialize(bd_t *bis)
struct eth_device* dev;
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "SCC ETHERNET");
dev->iobase = 0;

7
cpu/xscale/start.S
View File

@ -175,10 +175,11 @@ OSTIMER_BASE: .word 0x40a00000
#define OIER 0x1C
/* Clock Manager Registers */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
cpuspeed: .word CFG_CPUSPEED
#endif
/* RS: ??? */
.macro CPWAIT
mrc p15,0,r0,c2,c0,0
@ -194,10 +195,14 @@ cpu_init_crit:
mov r1, #0x00
str r1, [r0, #ICMR]
#ifdef CFG_CPUSPEED
/* set clock speed */
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
mov r0, #3
mcr p14, 0, r0, c6, c0, 0
#endif
/*
* before relocating, we have to setup RAM timing

1
include/common.h
View File

@ -156,6 +156,7 @@ int misc_init_r (void);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
void fdc_hw_init (void);
/* $(BOARD)/eeprom.c */
void eeprom_init (void);

2
include/configs/smdk2400.h
View File

@ -43,7 +43,7 @@
#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
/* input clock of PLL */
#define CONFIG_PLL_INPUT_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */

2
include/configs/smdk2410.h
View File

@ -44,7 +44,7 @@
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_PLL_INPUT_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
#define USE_920T_MMU 1

2
include/configs/trab.h
View File

@ -42,7 +42,7 @@
#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
/* input clock of PLL */
#define CONFIG_PLL_INPUT_FREQ 12000000 /* TRAB has 12 MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

6
include/spartan2.h
View File

@ -52,10 +52,12 @@ typedef struct {
/* Slave Serial Implementation function table */
typedef struct {
Xilinx_pre_fn pre;
Xilinx_pgm_fn pgm;
Xilinx_clk_fn clk;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
Xilinx_init_fn init;
Xilinx_done_fn done;
Xilinx_wr_fn wr;
int relocated;
} Xilinx_Spartan2_Slave_Serial_fns;

1
net/eth.c
View File

@ -229,7 +229,6 @@ int eth_init(bd_t *bis)
if (eth_current->init(eth_current, bis)) {
eth_current->state = ETH_STATE_ACTIVE;
printf("%s configured\n", eth_current->name);
return 1;
}

1
ppc_config.mk
View File

@ -22,3 +22,4 @@
#
PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
PLATFORM_LDFLAGS += -n