DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface
type cases.
Fixes: 6b7ebff001 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Since, commit 62f9b65447 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in
the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or
is scanning the bus, passing -1 here should keep it functional either way.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Cc: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
i2c bugfixes for 2020.01
- i2c: i2c_cdns: fix write timeout on fifo boundary
fixes timout issue when writting number of bytes is multiple
of the FIFO depth.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJd77jyAAoJEB6zHgIOrC/IyYUH/iAUH4wo5qnOBiQU+MJluaiu
D8tMiJH13eW4gWnAqdGrOE9Q763asHIMshQpLK+4eXe4f4mZQ7re4CRNcYJrULeY
2StsJzl4sn/H4P5EiRuUWjkB7wnGRDD6ArH3j1uMJN4lpwCB0ZbqMQZpjt3wI2H4
KuE42d/ll08Aj0AvwdusffLIxlw5M1Z94uQSHoC3UTkPYN4VD5zXgdxv5eH6PZWe
paWmHQ0g7fL4UnYGWa0Jpx10SZpcut06dTeVGpsGiEOhaJHvpjYd4JAs/TTUxhFx
d5ZRjo1fStYmBXQIblhPNlJQkW4cqa/B+81f5aZbN/1yCijJWS2G8anGtY2ikPs=
=f0dF
-----END PGP SIGNATURE-----
Merge tag 'u-boot-atmel-fixes-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
- First set of u-boot-atmel fixes for 2020.01 cycle:
This set includes a small fix for gpio bank names, one for removing
unused headers (also touches some other boards), and a fix for the QSPI
env read on one of the boards.
This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).
Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.
In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.
Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
(tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
stm32f746-disco, stm32f769-disco and wandboard)
-----BEGIN PGP SIGNATURE-----
iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXe//LA4cYWd1c3RAZGVu
eC5kZQAKCRBM6ATMmsalXOqBAJ9N6oTID0v092duxoUoO5xAeqIKxgCfS/YvgGx4
KGgiPWQv0V1bGxXyYNA=
=PoNP
-----END PGP SIGNATURE-----
Merge tag 'fixes-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix crash and board reset when drawing RLE8 bitmaps
bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
(tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
stm32f746-disco, stm32f769-disco and wandboard)
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Implement dma_get_cfg() interface to pass flow id information for DMA
clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and
UDMA (DMA provider) support "flows" within a given RX DMA channel. This
allows different network packets to be segregated while using same RX
DMA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Sometimes, there would be a need to exchange data between DMA provider
and DMA client which are very specific to DMA driver of the SoC/platform
and are not generic enough to be put into struct dma. Therefore, introduce
dma_get_cfg() interface to get DMA provider specific data from client
device. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Fixes: e766849713 ("net: ftgmac100: convert the RX/TX descriptor arrays")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This bus is used to access internal SoC PHYs. These PHYs are configured
by the ENETC driver directly, but it's useful to have command line access
to this MDIO to debug the system especially when using new external PHYs.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On some boards MDIO may get stuck if it detects echo on the line. This is
a know hardware issue, there is a board fix for it. In case we're running
on a board that doesn't have the fix, we don't want to loop here forever
and freeze U-Boot.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This reduces the time needed to establish a link as we don't reset the link
each time the interface is used. Our Link capabilities do not change at
run-time so there is no need to re-apply PHY configuration each time.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The original code enabled link speeds up to 1Gbps, but the interface can
go up to 2.5G, enable that speed to in PHY AN mask.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify
the code.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface. The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique. Add an optional DT property used
to change SMBus address if needed.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.
Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register. Keep that functionality too, so we don't break existing drivers.
Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix vendor name in MV88E61xx option description.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Support probing and init for 88E6071 switch.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Extend the driver to init switch register offsets from variables
instead of compile time macros and enable detection of 88E6071 and
compatible devices. Ethernet transfer (e.g. tftp) does not work yet,
so enable the registration of the 'indirect mii' bus for easier PHY
register access by 'mii' command.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KSZ8081 PHY has a factory test mode which is set at the de-assertion
of the reset line based on the RXER (KSZ8081RNA/RND) or TXC
(KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a
pull-up, the factory test mode should be cleared by manually writing a 0
(according to the datasheet).
Create another ksz8081_config function to handle this case.
Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia quad-phys may take longer to initialize. This commit adds
a polling mechanism for a global alarm bit that tells if phy init
sequence is completed.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This allows passing arbitrary addresses through macb_miiphy_read and
macb_miiphy_write, therefore enabling the mii command to access
all mdio bus devices instead of only the defined phy.
Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
To support accessing arbitrary addresses the mii/mdio bus it is
necessary that the macb_mdio_read and macb_mdio_write functions
do not implicitly use the address of the connected phy.
The function signature is extended according to the Linux kernel
equivalent.
Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
I've noticed that in most cases when genphy_update_link() is called, the
ethernet driver (mt7628-eth in this case) fails with the first ethernet
packets. Resulting in a timeout of the first tftp command. Increasing
the delay in the link check look from 1 to 50 ms and moving it below the
BMSR register read fixes this issue, resulting in a stable ethernet
traffic, even after initial link autonogotiation.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This version of the RTL-8168 chip can be found on some add-in cards sold
by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it
needs to have the ChipCmd register programmed after the DMA descriptors
have been set up, so make sure that happens by adding an entry to the
chip information table.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Changes to mvpp2.c require the MVMDIO module which in turn uses
DM_MDIO.
Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit ports mvpp2 to use the recently introduced Marvell MDIO
(MVMDIO) driver. It removes direct interaction with the SMI & XSMI
busses. This commit is based in part on earlier work by
Ken Ma <make@marvell.com> in Marvell's own downstream repo:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39.
The above refrenced work was based on an MVMDIO implementation that
never made it into U-Boot. With this patch the mvpp2 driver switches
to use the new MVMDIO driver that is based on a more universal
mdio-uclass implementation.
Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If the phy doesn't match with any existing u-boot drivers, the phy
framework will connect it to the generic one which uid ==
0xffffffff. In this case, act as if the phy wouldn't be declared in
dts. Otherwise, in case of 3310 (for which the driver doesn't exist)
the link is marked as always down. Removing phy entry from dts in case
of 3310 is not a good option because it is required for the
phy_fw_down procedure.
This patch fixes the issue with the link always down on MCBIN board.
nhed: added NULL deref test.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Issue:
- Network stuck if autonegotion fails.
Issue root cause:
- When autonegotiation fails during port open procedure, the packet
processor configuration does not finish and open procedure exits
with error.
- However, this doesn't prevent u-boot network framework from
calling send and receive procedures.
- Using transmit and receive functions of misconfigured packet
processor will cause traffic to get stuck.
Fix:
- Continue packet processor configuration even if autonegotiation
fails. Only error message is triggered in this case.
- Exit transmit and receive functions if there is no PHY link
indication.
- U-boot network framework now calls open procedure again during next
transmit initiation.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Refactor SGMII configuration to group all settings together and reduce
number of MDIO transactions.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not
dependent on RGMII delay") of mainline linux kernel.
The driver would only set the IO impedance value when RGMII internal delays
were enabled. There is no reason for this. Move the IO impedance block
out of the RGMII delay block.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay
handling") of mainline linux kernel.
The current code is assuming the reset default of the delay control
register was to have delay disabled. This is what the datasheet shows as
the register's initial value. However, that's not actually true: the
default is controlled by the PHY's pin strapping.
This patch:
- insures the other direction's delay is disabled If the interface mode is
selected as RX or TX delay only
- validates the delay values and fail if they are not in range
- checks if the board is strapped to have a delay and is configured to use
"rgmii" mode and warning is generated that "rgmii-id" should have been
used.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable
output clock") of mainline linux kernel.
Generally, the output clock pin is only used for testing and only serves as
a source of RF noise after this. It could be used to daisy-chain PHYs, but
this is uncommon. Since the PHY can disable the output, make doing so an
option. I do this by adding another enumeration to the allowed values of
ti,clk-output-sel.
The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
expect: to select the REF_CLK as the output. Rather it meant "keep clock
output setting as is", which, depending on PHY strapping, might not be
outputting REF_CLK.
Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
Omitting the property will leave the setting as is (which was the previous
behavior in this case).
Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK.
Change this so they generate an error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
