wait_for_bit() is missing reset watchdog in case watchdog
is configured.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Dedicate VPLL for DP
- Enable VPLL frac mode
These changes are done by hand and PCW generation
needs to be checked and validated again.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is enabling support for SPL QSPI boot.
First of all it is necessary to generate atf-spi.ub which is different
format than atf-uboot.ub (this can be made as legacy image too)
ADDR=`arm-xilinx-linux-gnueabi-readelf -a bl31.elf | grep "Entry point
address" | cut -d ':' -f 2 | sed -e 's/^[ \t]*//'`
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
./tools/mkimage -f auto -A arm64 -T firmware -C none -O u-boot -a $ADDR
-e $ADDR -n "atf1" -E -b arch/arm/dts/zynqmp-zcu102.dtb -d bl31.bin
atf-uboot.ub
./tools/mkimage -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR
-n "atf-for-qspi" -E -d bl31.bin atf-spi.ub
This patch is using this QSPI layout with offsets:
0 boot.bin
512k atf-ub
640k u-boot.bin
1280k u-boot.img
Which corresponding by writing these images(read from MMC)
mmcinfo
sf probe
load mmc 0 10000000 boot.bin
sf erase 0 +$filesize
sf write 10000000 0 $filesize
load mmc 0 10000000 atf-spi.ub
sf erase 0x80000 +$filesize
sf write 10000000 0x80000 $filesize
load mmc 0 10000000 u-boot.bin
sf erase 0xa0000 +$filesize
sf write 10000000 0xa0000 $filesize
load mmc 0 10000000 u-boot.img
sf erase 0x140000 +$filesize
sf write 10000000 0x140000 $filesize
For testing u-boot running in EL3 you can break atf-spi.ub like this:
sf probe
sf erase 0x80000 +4
Then u-boot.img is executed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
One print requires line ending to be aligned with SW running
after it. Prints look weird without it.
For example:
U-Boot SPL 2017.01-01801-g1fb1292c7b9d (Jan 16 2017 - 12:50:53)
EL Level: EL3
Trying to boot from SPINOTICE: ATF running on XCZU15EG/silicon
v2/RTL5.1 at 0xfffe5000, with PMU firmware
NOTICE: BL31: Secure code at 0x0
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
New scan should unbind all block devices not to be listed again.
Without this patch if scsi reset or scan is called new block devices are
created which point to the same id and lun.
For example:
ZynqMP> scsi scan
scsi_scan: if_type=2, devnum=0: sdhci@ff170000.blk, 6, 0
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 0
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 1
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 2
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 3
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 4
scanning bus for devices...
Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A
Type: Hard Disk
Capacity: 57241.8 MB = 55.9 GB (117231408 x 512)
Reported-by: Ken Ma <make@marvell.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes incorrect pointer on offset device in device tree blob.
When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII"
it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying
to change frequency.
Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for non processor mode, this mode doesnt have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Glue logic depends on DM_USB that's why remove !DM_USB
code because only this default case is tested.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
By enabling DM_USB information about number of storage devices
was lost.
Get this information back simply by printing number of devices detected
via BLK uclass.
For example:
scanning bus 0 for devices... 7 USB Device(s) found
scanning usb for storage devices... 3 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
By enabling BLK by default this is the next driver which needs to get
support for DM_USB. Adding generic DWC3 glue logic which only
parse nodes and read device mode. Based on it probe proper
host/peripheral DWC3 drivers for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a TI DWC3 peripheral driver with driver model support and the
driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.
Xilinx: Remove dwc3-omap changes + limit zynqmp static init
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add in code to initialize the DWC3 gadget controller so that we can do
RNDIS in SPL on these platforms.
Xilinx: Remove am43xx changes and add usb/common to Makefile compilation
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add support to get maximum speed from dt so that usb drivers
makes use of it for DT parsing.
Xilinx: Fix error message.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add a misc driver for DWC3 wrapper, so that based on dr_mode the
USB devices can bind to USB host or USB device drivers.
Xilinx: Remove changes related to dwc3-omap.c
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
devm_zalloc() is already defined in dm/device.h header, so
devm_zalloc can be removed from linux_compact.h beader file.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Consolidate the net device, usb eth device and gadget device
struct to single struct and a single global variable so that the
same can be passed as priv of ethernet driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
network_started of struct eth_dev can be accessed using local
variable dev and no reason to access it with the global struct.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch is fixing missing fclose() calls
in error patch introduced by:
"tools: mkimage: Use fstat instead of stat to avoid malicious hacks"
(sha1: ebe0f53f48)
Reported-by: Coverity (CID: 155064, 155065)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This functionality should be covered by:
"mtd: cfi_flash: Write buffer size adjustment for M29EW Numonyx devices"
(sha1: 6f13889eb0)
That's why remove this macro and hack.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
cc108 is handled via zynq-common.h config. The only missing
piece is different ENV_OFFSET setting for qspi boot mode
but this depends on user configuration. This board is tested via jtag
boot mode only that's why if qspi mode is required we can fix it later.
Comment was added to zynq-common.h not to be lost.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Prepare v2016.11
- Add missing CONFIG_ macros to Kconfig. It should be fixed in future
- Fix spl_mmc fpga code
- Add missing defconfig macros
- Remove FPGA macros because it was moved to Kconfig in mainline
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
which is missing in below commit
"imx: mx6ull_14x14_evk: add plugin defconfig"
(sha1: b90ebf49bb)
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.
Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.
When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.
Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.
This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.
Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.
Signed-off-by: Andrew F. Davis <afd@ti.com>
