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clk: sifive: Sync-up DT bindings header with upstream Linux

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The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Anup Patel 2019-06-25 06:31:15 +00:00 committed by Andes
parent c236802696
commit 66591a719a
3 changed files with 19 additions and 30 deletions
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2
drivers/clk/sifive/fu540-prci.c
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@ -38,7 +38,7 @@
#include <linux/math64.h>
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
#include <dt-bindings/clk/sifive-fu540-prci.h>
#include <dt-bindings/clock/sifive-fu540-prci.h>
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:

29
include/dt-bindings/clk/sifive-fu540-prci.h
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@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
*
* Copyright (C) 2018 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H
#define __LINUX_CLK_SIFIVE_FU540_PRCI_H
/* Clock indexes for use by Device Tree data */
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_TLCLK 3
#endif

18
include/dt-bindings/clock/sifive-fu540-prci.h Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018-2019 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
*/
#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
/* Clock indexes for use by Device Tree data and the PRCI driver */
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_TLCLK 3
#endif