clk: sifive: Sync-up WRPLL library with upstream Linux
Now that SiFive clock driver is merged in upstream Linux, we sync-up WRPLL library used by SiFive clock driver with upstream Linux sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Anup Patel
Andes
parent
d04c79d2b2
commit
c236802696
@ -1,20 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Copyright (C) 2018 SiFive, Inc.
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* Copyright (C) 2018-2019 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This library supports configuration parsing and reprogramming of
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* the CLN28HPC variant of the Analog Bits Wide Range PLL. The
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* intention is for this library to be reusable for any device that
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@ -29,6 +18,7 @@
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* References:
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* - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
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* - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
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* https://static.dev.sifive.com/FU540-C000-v1.0.pdf
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*/
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#include <linux/bug.h>
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@ -84,40 +74,38 @@
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* range selection.
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*
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* Return: The RANGE value to be presented to the PLL configuration inputs,
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* or -1 upon error.
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* or a negative return code upon error.
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*/
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static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
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{
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u8 range;
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if (post_divr_freq < MIN_POST_DIVR_FREQ ||
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post_divr_freq > MAX_POST_DIVR_FREQ) {
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WARN(1, "%s: post-divider reference freq out of range: %lu",
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__func__, post_divr_freq);
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return -1;
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return -ERANGE;
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}
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if (post_divr_freq < 11000000)
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range = 1;
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else if (post_divr_freq < 18000000)
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range = 2;
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else if (post_divr_freq < 30000000)
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range = 3;
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else if (post_divr_freq < 50000000)
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range = 4;
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else if (post_divr_freq < 80000000)
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range = 5;
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else if (post_divr_freq < 130000000)
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range = 6;
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else
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range = 7;
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switch (post_divr_freq) {
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case 0 ... 10999999:
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return 1;
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case 11000000 ... 17999999:
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return 2;
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case 18000000 ... 29999999:
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return 3;
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case 30000000 ... 49999999:
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return 4;
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case 50000000 ... 79999999:
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return 5;
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case 80000000 ... 129999999:
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return 6;
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}
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return range;
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return 7;
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}
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/**
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* __wrpll_calc_fbdiv() - return feedback fixed divide value
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* @c: ptr to a struct analogbits_wrpll_cfg record to read from
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* @c: ptr to a struct wrpll_cfg record to read from
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*
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* The internal feedback path includes a fixed by-two divider; the
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* external feedback path does not. Return the appropriate divider
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@ -132,7 +120,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
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* Return: 2 if internal feedback is enabled or 1 if external feedback
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* is enabled.
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*/
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static u8 __wrpll_calc_fbdiv(struct analogbits_wrpll_cfg *c)
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static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c)
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{
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return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
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}
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@ -172,7 +160,7 @@ static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
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*vco_rate = MIN_VCO_FREQ;
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} else {
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divq = ilog2(s);
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*vco_rate = target_rate << divq;
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*vco_rate = (u64)target_rate << divq;
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}
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wcd_out:
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@ -181,7 +169,7 @@ wcd_out:
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/**
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* __wrpll_update_parent_rate() - update PLL data when parent rate changes
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* @c: ptr to a struct analogbits_wrpll_cfg record to write PLL data to
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* @c: ptr to a struct wrpll_cfg record to write PLL data to
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* @parent_rate: PLL input refclk rate (pre-R-divider)
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*
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* Pre-compute some data used by the PLL configuration algorithm when
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@ -189,46 +177,40 @@ wcd_out:
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* computation when the parent rate remains constant - expected to be
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* the common case.
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*
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* Returns: 0 upon success or -1 if the reference clock rate is out of range.
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* Returns: 0 upon success or -ERANGE if the reference clock rate is
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* out of range.
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*/
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static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
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static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
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unsigned long parent_rate)
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{
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u8 max_r_for_parent;
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if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
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return -1;
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return -ERANGE;
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c->_parent_rate = parent_rate;
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c->parent_rate = parent_rate;
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max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
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c->_max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
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c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
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/* Round up */
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c->_init_r = div_u64(parent_rate + MAX_POST_DIVR_FREQ - 1,
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MAX_POST_DIVR_FREQ);
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c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
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return 0;
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}
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/*
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* Public functions
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*/
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/**
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* analogbits_wrpll_configure() - compute PLL configuration for a target rate
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* @c: ptr to a struct analogbits_wrpll_cfg record to write into
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* wrpll_configure() - compute PLL configuration for a target rate
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* @c: ptr to a struct wrpll_cfg record to write into
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* @target_rate: target PLL output clock rate (post-Q-divider)
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* @parent_rate: PLL input refclk rate (pre-R-divider)
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*
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* Given a pointer to a PLL context @c, a desired PLL target output
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* rate @target_rate, and a reference clock input rate @parent_rate,
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* compute the appropriate PLL signal configuration values. PLL
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* reprogramming is not glitchless, so the caller should switch any
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* downstream logic to a different clock source or clock-gate it
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* before presenting these values to the PLL configuration signals.
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* Compute the appropriate PLL signal configuration values and store
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* in PLL context @c. PLL reprogramming is not glitchless, so the
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* caller should switch any downstream logic to a different clock
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* source or clock-gate it before presenting these values to the PLL
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* configuration signals.
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*
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* The caller must pass this function a pre-initialized struct
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* analogbits_wrpll_cfg record: either initialized to zero (with the
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* wrpll_cfg record: either initialized to zero (with the
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* exception of the .name and .flags fields) or read from the PLL.
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*
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* Context: Any context. Caller must protect the memory pointed to by @c
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@ -236,41 +218,26 @@ static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
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*
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* Return: 0 upon success; anything else upon failure.
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*/
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int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
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u32 target_rate,
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unsigned long parent_rate)
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int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
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unsigned long parent_rate)
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{
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unsigned long ratio;
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u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
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u32 best_f, f, post_divr_freq, fbcfg;
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u32 best_f, f, post_divr_freq;
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u8 fbdiv, divq, best_r, r;
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if (!c)
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return -1;
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int range;
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if (c->flags == 0) {
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WARN(1, "%s called with uninitialized PLL config", __func__);
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return -1;
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}
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fbcfg = WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK;
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if ((c->flags & fbcfg) == fbcfg) {
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WARN(1, "%s called with invalid PLL config", __func__);
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return -1;
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}
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if (c->flags == WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
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WARN(1, "%s: external feedback mode not currently supported",
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__func__);
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return -1;
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return -EINVAL;
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}
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/* Initialize rounding data if it hasn't been initialized already */
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if (parent_rate != c->_parent_rate) {
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if (parent_rate != c->parent_rate) {
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if (__wrpll_update_parent_rate(c, parent_rate)) {
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pr_err("%s: PLL input rate is out of range\n",
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__func__);
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return -1;
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return -ERANGE;
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}
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}
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@ -281,11 +248,12 @@ int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
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c->flags |= WRPLL_FLAGS_BYPASS_MASK;
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return 0;
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}
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c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
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/* Calculate the Q shift and target VCO rate */
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divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
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if (divq == 0)
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if (!divq)
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return -1;
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c->divq = divq;
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@ -301,8 +269,7 @@ int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
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* Consider all values for R which land within
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* [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
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*/
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for (r = c->_init_r; r <= c->_max_r; ++r) {
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/* What is the best F we can pick in this case? */
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for (r = c->init_r; r <= c->max_r; ++r) {
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f_pre_div = ratio * r;
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f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
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f >>= (fbdiv - 1);
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@ -334,46 +301,54 @@ int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
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post_divr_freq = div_u64(parent_rate, best_r);
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/* Pick the best PLL jitter filter */
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c->range = __wrpll_calc_filter_range(post_divr_freq);
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range = __wrpll_calc_filter_range(post_divr_freq);
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if (range < 0)
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return range;
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c->range = range;
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return 0;
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}
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/**
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* analogbits_wrpll_calc_output_rate() - calculate the PLL's target output rate
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* @c: ptr to a struct analogbits_wrpll_cfg record to read from
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* wrpll_calc_output_rate() - calculate the PLL's target output rate
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* @c: ptr to a struct wrpll_cfg record to read from
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* @parent_rate: PLL refclk rate
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*
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* Given a pointer to the PLL's current input configuration @c and the
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* PLL's input reference clock rate @parent_rate (before the R
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* pre-divider), calculate the PLL's output clock rate (after the Q
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* post-divider)
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* post-divider).
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*
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* Context: Any context. Caller must protect the memory pointed to by @c
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* from simultaneous modification.
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*
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* Return: the PLL's output clock rate, in Hz.
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* Return: the PLL's output clock rate, in Hz. The return value from
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* this function is intended to be convenient to pass directly
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* to the Linux clock framework; thus there is no explicit
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* error return value.
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*/
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unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
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unsigned long parent_rate)
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unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
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unsigned long parent_rate)
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{
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u8 fbdiv;
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u64 n;
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WARN(c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK,
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"external feedback mode not yet supported");
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if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
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WARN(1, "external feedback mode not yet supported");
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return ULONG_MAX;
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}
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fbdiv = __wrpll_calc_fbdiv(c);
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n = parent_rate * fbdiv * (c->divf + 1);
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n = div_u64(n, (c->divr + 1));
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n = div_u64(n, c->divr + 1);
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n >>= c->divq;
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return n;
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}
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/**
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* analogbits_wrpll_calc_max_lock_us() - return the time for the PLL to lock
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* @c: ptr to a struct analogbits_wrpll_cfg record to read from
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* wrpll_calc_max_lock_us() - return the time for the PLL to lock
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* @c: ptr to a struct wrpll_cfg record to read from
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*
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* Return the minimum amount of time (in microseconds) that the caller
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* must wait after reprogramming the PLL to ensure that it is locked
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@ -383,7 +358,7 @@ unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
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* Return: the minimum amount of time the caller must wait for the PLL
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* to lock (in microseconds)
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*/
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unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c)
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unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
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{
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return MAX_LOCK_US;
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}
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@ -174,7 +174,7 @@ struct __prci_data {
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* bypass mux is not glitchless.
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*/
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struct __prci_wrpll_data {
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struct analogbits_wrpll_cfg c;
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struct wrpll_cfg c;
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void (*bypass)(struct __prci_data *pd);
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void (*no_bypass)(struct __prci_data *pd);
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u8 cfg0_offs;
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@ -244,7 +244,7 @@ static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
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/**
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* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
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* @c: ptr to a struct analogbits_wrpll_cfg record to write config into
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* @c: ptr to a struct wrpll_cfg record to write config into
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* @r: value read from the PRCI PLL configuration register
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*
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* Given a value @r read from an FU540 PRCI PLL configuration register,
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@ -256,7 +256,7 @@ static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
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*
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* Context: Any context.
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*/
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static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
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static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
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{
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u32 v;
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@ -287,7 +287,7 @@ static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
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/**
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* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
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* @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
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* @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
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*
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* Using a set of WRPLL configuration values pointed to by @c,
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* assemble a PRCI PLL configuration register value, and return it to
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@ -300,7 +300,7 @@ static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
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* Returns: a value suitable for writing into a PRCI PLL configuration
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* register
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*/
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static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
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static u32 __prci_wrpll_pack(struct wrpll_cfg *c)
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{
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u32 r = 0;
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@ -348,11 +348,11 @@ static void __prci_wrpll_read_cfg(struct __prci_data *pd,
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*/
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static void __prci_wrpll_write_cfg(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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struct analogbits_wrpll_cfg *c)
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struct wrpll_cfg *c)
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{
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__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
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memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
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memcpy(&pwd->c, c, sizeof(struct wrpll_cfg));
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}
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/* Core clock mux control */
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@ -403,7 +403,7 @@ static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
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return wrpll_calc_output_rate(&pwd->c, parent_rate);
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}
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static unsigned long sifive_fu540_prci_wrpll_round_rate(
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@ -412,13 +412,13 @@ static unsigned long sifive_fu540_prci_wrpll_round_rate(
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unsigned long *parent_rate)
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct analogbits_wrpll_cfg c;
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struct wrpll_cfg c;
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memcpy(&c, &pwd->c, sizeof(c));
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analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
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wrpll_configure_for_rate(&c, rate, *parent_rate);
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return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
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return wrpll_calc_output_rate(&c, *parent_rate);
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}
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static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
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@ -429,7 +429,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
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struct __prci_data *pd = pc->pd;
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int r;
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r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
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r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
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if (r)
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return -ERANGE;
|
||||
|
||||
@ -438,7 +438,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
|
||||
|
||||
__prci_wrpll_write_cfg(pd, pwd, &pwd->c);
|
||||
|
||||
udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
|
||||
udelay(wrpll_calc_max_lock_us(&pwd->c));
|
||||
|
||||
if (pwd->no_bypass)
|
||||
pwd->no_bypass(pd);
|
||||
|
||||
@ -1,19 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Copyright (C) 2018 SiFive, Inc.
|
||||
* Copyright (C) 2018-2019 SiFive, Inc.
|
||||
* Wesley Terpstra
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
|
||||
@ -25,7 +14,7 @@
|
||||
#define DIVQ_VALUES 6
|
||||
|
||||
/*
|
||||
* Bit definitions for struct analogbits_wrpll_cfg.flags
|
||||
* Bit definitions for struct wrpll_cfg.flags
|
||||
*
|
||||
* WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
|
||||
* programmed to enter bypass
|
||||
@ -34,10 +23,6 @@
|
||||
* feedback mode
|
||||
* WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
|
||||
* feedback mode (not yet supported by this driver)
|
||||
*
|
||||
* The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WRPLL_FLAGS_EXT_FEEDBACK_FLAG are
|
||||
* mutually exclusive. If both bits are set, or both are zero, the struct
|
||||
* analogbits_wrpll_cfg record is uninitialized or corrupt.
|
||||
*/
|
||||
#define WRPLL_FLAGS_BYPASS_SHIFT 0
|
||||
#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
|
||||
@ -49,53 +34,46 @@
|
||||
#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
|
||||
|
||||
/**
|
||||
* struct analogbits_wrpll_cfg - WRPLL configuration values
|
||||
* @divr: reference divider value (6 bits), as presented to the PLL signals.
|
||||
* @divf: feedback divider value (9 bits), as presented to the PLL signals.
|
||||
* @divq: output divider value (3 bits), as presented to the PLL signals.
|
||||
* @flags: PLL configuration flags. See above for more information.
|
||||
* @range: PLL loop filter range. See below for more information.
|
||||
* @_output_rate_cache: cached output rates, swept across DIVQ.
|
||||
* @_parent_rate: PLL refclk rate for which values are valid
|
||||
* @_max_r: maximum possible R divider value, given @parent_rate
|
||||
* @_init_r: initial R divider value to start the search from
|
||||
* struct wrpll_cfg - WRPLL configuration values
|
||||
* @divr: reference divider value (6 bits), as presented to the PLL signals
|
||||
* @divf: feedback divider value (9 bits), as presented to the PLL signals
|
||||
* @divq: output divider value (3 bits), as presented to the PLL signals
|
||||
* @flags: PLL configuration flags. See above for more information
|
||||
* @range: PLL loop filter range. See below for more information
|
||||
* @output_rate_cache: cached output rates, swept across DIVQ
|
||||
* @parent_rate: PLL refclk rate for which values are valid
|
||||
* @max_r: maximum possible R divider value, given @parent_rate
|
||||
* @init_r: initial R divider value to start the search from
|
||||
*
|
||||
* @divr, @divq, @divq, @range represent what the PLL expects to see
|
||||
* on its input signals. Thus @divr and @divf are the actual divisors
|
||||
* minus one. @divq is a power-of-two divider; for example, 1 =
|
||||
* divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
|
||||
*
|
||||
* When initially passing a struct analogbits_wrpll_cfg record, the
|
||||
* When initially passing a struct wrpll_cfg record, the
|
||||
* record should be zero-initialized with the exception of the @flags
|
||||
* field. The only flag bits that need to be set are either
|
||||
* WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
|
||||
*
|
||||
* Field names beginning with an underscore should be considered
|
||||
* private to the wrpll-cln28hpc.c code.
|
||||
*/
|
||||
struct analogbits_wrpll_cfg {
|
||||
struct wrpll_cfg {
|
||||
u8 divr;
|
||||
u8 divq;
|
||||
u8 range;
|
||||
u8 flags;
|
||||
u16 divf;
|
||||
u32 _output_rate_cache[DIVQ_VALUES];
|
||||
unsigned long _parent_rate;
|
||||
u8 _max_r;
|
||||
u8 _init_r;
|
||||
/* private: */
|
||||
u32 output_rate_cache[DIVQ_VALUES];
|
||||
unsigned long parent_rate;
|
||||
u8 max_r;
|
||||
u8 init_r;
|
||||
};
|
||||
|
||||
/*
|
||||
* Function prototypes
|
||||
*/
|
||||
int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
|
||||
unsigned long parent_rate);
|
||||
|
||||
int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
|
||||
u32 target_rate,
|
||||
unsigned long parent_rate);
|
||||
unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
|
||||
|
||||
unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c);
|
||||
|
||||
unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
|
||||
unsigned long parent_rate);
|
||||
unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
|
||||
unsigned long parent_rate);
|
||||
|
||||
#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user