powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
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@ -20,6 +20,12 @@
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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* Use the L1 data cache line size value for the minimum DMA buffer alignment
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* on PowerPC.
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*/
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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/*
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* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
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*/
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