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nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

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Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Scott McNutt <smcnutt@psyent.com>
This commit is contained in:
Anton Staaf 2011-10-17 16:46:05 -07:00 committed by Wolfgang Denk
parent a8fc12eb8e
commit 6fa6035ff2
1 changed files with 11 additions and 0 deletions
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11
arch/nios2/include/asm/cache.h
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@ -27,4 +27,15 @@
extern void flush_dcache (unsigned long start, unsigned long size);
extern void flush_icache (unsigned long start, unsigned long size);
/*
* Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
* bytes. If the board configuration has not specified one we default to the
* largest of these values for alignment of DMA buffers.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 32
#endif
#endif /* __ASM_NIOS2_CACHE_H_ */