When reading the base address of the a REDIST region
through KVM_VGIC_V3_ADDR_TYPE_REDIST we expect the
redistributor region list to be populated with a single
element.
However list_first_entry() expects the list to be non empty.
Instead we should use list_first_entry_or_null which effectively
returns NULL if the list is empty.
Fixes: dbd9733ab6 ("KVM: arm/arm64: Replace the single rdist region by a list")
Cc: <Stable@vger.kernel.org> # v4.18+
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reported-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210412150034.29185-1-eric.auger@redhat.com
Currently there are a number of places in the SVE code where we check both
system_supports_sve() and TIF_SVE. This is a bit redundant given that we
should never get into a situation where we have set TIF_SVE without having
SVE support and it is not clear that silently ignoring a mistakenly set
TIF_SVE flag is the most sensible error handling approach. For now let's
just drop the system_supports_sve() checks since this will at least reduce
overhead a little.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210412172320.3315-1-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
and using ranged values to allow better compatibility with regulator
steps), gpu opps on px30, infrared receiver on rockpro64,
USB3 support on rk3328, MMC alias fixups, dt-compatible fixes.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmByvnMQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdga73B/9EvLxu08VwgERaPs1n6XrjpDwfid7u9ops
wi5/bLqeBK4Jrg7jrlN1snwzfqnqPeDe2amZyi1CwCnPJNmloIkMIdLtSwIdc2ws
85O8Oa3Yus3boRh+bQ67F8vP6QNNfu0u9q5Nqe3cQhp/R8PaCZy1gVVjX4ZJiFz8
qmcPsI92czrlK0zcjWU7LfIzYVUZ/XPKTcBDkpQb1wPJ2/j6mHz4a4XXrfltLtKJ
P1XpseI4YqIFt77cZV0bpeO49/wq5UX6KSdYDdpYzO9e8FUPT6Khhc4CpApsIxyY
QgHPe6pgJj/KZHI8/Qo9I0nLjxNTJXmad0FNIBvinuyATv2zSt4M
=Zu51
-----END PGP SIGNATURE-----
Merge tag 'v5.13-rockchip-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New board the NanoPi R4S, OPP adjustments on rk3399 (sync with vendor
and using ranged values to allow better compatibility with regulator
steps), gpu opps on px30, infrared receiver on rockpro64,
USB3 support on rk3328, MMC alias fixups, dt-compatible fixes.
* tag 'v5.13-rockchip-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: move mmc aliases to board dts on rk3399
arm64: dts: rockchip: move mmc aliases to board dts on rk3368
arm64: dts: rockchip: move mmc aliases to board dts on rk3328
arm64: dts: rockchip: move mmc aliases to board dts on rk3308
arm64: dts: rockchip: move mmc aliases to board dts on px30
arm64: dts: rockchip: add new watchdog compatible to rk3399.dtsi
arm64: dts: rockchip: add new watchdog compatible to rk3328.dtsi
arm64: dts: rockchip: add new watchdog compatible to rk3308.dtsi
arm64: dts: rockchip: add new watchdog compatible to px30.dtsi
arm64: dts: rockchip: enable dwc3 usb for A95X Z2
arm64: dts: rockchip: add rk3328 dwc3 usb controller node
rockchip: rk3399: Add support for FriendlyARM NanoPi R4S
dt-bindings: Add doc for FriendlyARM NanoPi R4S
arm64: dts: rockchip: add phandle to timer0 on rk3368
arm64: dts: rockchip: add infrared receiver node to rockpro64
arm64: dts: rockchip: drop separate opp table on rk3399-puma
arm64: dts: rockchip: used range'd gpu opps on rk3399
arm64: dts: rockchip: synchronize rk3399 opps with vendor kernel
arm64: dts: rockchip: Add gpu opp nodes to px30 dtsi
Link: https://lore.kernel.org/r/2191862.ElGaqSPkdT@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
If instruction being single stepped caused a page fault, the kprobes
is cancelled to let the page fault handler continue as a normal page
fault. But the local irqflags are disabled so cpu will restore pstate
with DAIF masked. After pagefault is serviced, the kprobes is
triggerred again, we overwrite the saved_irqflag by calling
kprobes_save_local_irqflag(). NOTE, DAIF is masked in this new saved
irqflag. After kprobes is serviced, the cpu pstate is retored with
DAIF masked.
This patch is inspired by one patch for riscv from Liao Chang.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Link: https://lore.kernel.org/r/20210412174101.6bfb0594@xhacker.debian
Signed-off-by: Will Deacon <will@kernel.org>
Pull ARM cpufreq updates for v5.13 from Viresh Kumar:
"- Fix typos in s5pv210 cpufreq driver (Bhaskar Chowdhury).
- Armada 37xx: Fix cpufreq changing base CPU speed to 800 MHz from
1000 MHz (Pali Rohár and Marek Behún).
- cpufreq-dt: Return -EPROBE_DEFER on failure to add table (Quanyang
Wang).
- Minor cleanup in cppc driver (Tom Saeger).
- Add frequency invariance support for CPPC driver and generalize
freq invariance support arch-topology driver (Viresh Kumar)."
* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
cpufreq: armada-37xx: Fix module unloading
cpufreq: armada-37xx: Remove cur_frequency variable
cpufreq: armada-37xx: Fix determining base CPU frequency
cpufreq: armada-37xx: Fix driver cleanup when registration failed
clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0
clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHz
cpufreq: armada-37xx: Fix the AVS value for load L1
clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clock
cpufreq: armada-37xx: Fix setting TBG parent for load levels
cpufreq: dt: dev_pm_opp_of_cpumask_add_table() may return -EPROBE_DEFER
cpufreq: cppc: simplify default delay_us setting
cpufreq: Rudimentary typos fix in the file s5pv210-cpufreq.c
cpufreq: CPPC: Add support for frequency invariance
arch_topology: Export arch_freq_scale and helpers
arch_topology: Allow multiple entities to provide sched_freq_tick() callback
arch_topology: Rename freq_scale as arch_freq_scale
The entry from EL0 code checks the TFSRE0_EL1 register for any
asynchronous tag check faults in user space and sets the
TIF_MTE_ASYNC_FAULT flag. This is not done atomically, potentially
racing with another CPU calling set_tsk_thread_flag().
Replace the non-atomic ORR+STR with an STSET instruction. While STSET
requires ARMv8.1 and an assembler that understands LSE atomics, the MTE
feature is part of ARMv8.5 and already requires an updated assembler.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Fixes: 637ec831ea ("arm64: mte: Handle synchronous and asynchronous tag check faults")
Cc: <stable@vger.kernel.org> # 5.10.x
Reported-by: Will Deacon <will@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210409173710.18582-1-catalin.marinas@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Kernel mode NEON can be used in task or softirq context, but only in
a non-nesting manner, i.e., softirq context is only permitted if the
interrupt was not taken at a point where the kernel was using the NEON
in task context.
This means all users of kernel mode NEON have to be aware of this
limitation, and either need to provide scalar fallbacks that may be much
slower (up to 20x for AES instructions) and potentially less safe, or
use an asynchronous interface that defers processing to a later time
when the NEON is guaranteed to be available.
Given that grabbing and releasing the NEON is cheap, we can relax this
restriction, by increasing the granularity of kernel mode NEON code, and
always disabling softirq processing while the NEON is being used in task
context.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210302090118.30666-4-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The AArch64 asm syntax has this slightly tedious property that the names
used in mnemonics to refer to registers depend on whether the opcode in
question targets the entire 64-bits (xN), or only the least significant
8, 16 or 32 bits (wN). When writing parameterized code such as macros,
this can be annoying, as macro arguments don't lend themselves to
indexed lookups, and so generating a reference to wN in a macro that
receives xN as an argument is problematic.
For instance, an upcoming patch that modifies the implementation of the
cond_yield macro to be able to refer to 32-bit registers would need to
modify invocations such as
cond_yield 3f, x8
to
cond_yield 3f, 8
so that the second argument can be token pasted after x or w to emit the
correct register reference. Unfortunately, this interferes with the self
documenting nature of the first example, where the second argument is
obviously a register, whereas in the second example, one would need to
go and look at the code to find out what '8' means.
So let's fix this by defining wxN aliases for all xN registers, which
resolve to the 32-bit alias of each respective 64-bit register. This
allows the macro implementation to paste the xN reference after a w to
obtain the correct register name.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210302090118.30666-3-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The users of the conditional NEON yield macros have all been switched to
the simplified cond_yield macro, and so the NEON specific ones can be
removed.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210302090118.30666-2-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This change adds KASAN-KUnit tests support for the async HW_TAGS mode.
In async mode, tag fault aren't being generated synchronously when a
bad access happens, but are instead explicitly checked for by the kernel.
As each KASAN-KUnit test expect a fault to happen before the test is over,
check for faults as a part of the test handler.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-10-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
When MTE async mode is enabled TFSR_EL1 contains the accumulative
asynchronous tag check faults for EL1 and EL0.
During the suspend/resume operations the firmware might perform some
operations that could change the state of the register resulting in
a spurious tag check fault report.
Report asynchronous tag faults before suspend and clear the TFSR_EL1
register after resume to prevent this to happen.
Cc: Will Deacon <will@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-9-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
MTE provides a mode that asynchronously updates the TFSR_EL1 register
when a tag check exception is detected.
To take advantage of this mode the kernel has to verify the status of
the register at:
1. Context switching
2. Return to user/EL0 (Not required in entry from EL0 since the kernel
did not run)
3. Kernel entry from EL1
4. Kernel exit to EL1
If the register is non-zero a trace is reported.
Add the required features for EL1 detection and reporting.
Note: ITFSB bit is set in the SCTLR_EL1 register hence it guaranties that
the indirect writes to TFSR_EL1 are synchronized at exception entry to
EL1. On the context switch path the synchronization is guarantied by the
dsb() in __switch_to().
The dsb(nsh) in mte_check_tfsr_exit() is provisional pending
confirmation by the architects.
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-8-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
mte_enable_kernel_*() are not needed if KASAN_HW is disabled.
Add ash defines around the functions to conditionally compile the
functions.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-7-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
load_unaligned_zeropad() and __get/put_kernel_nofault() functions can
read past some buffer limits which may include some MTE granule with a
different tag.
When MTE async mode is enabled, the load operation crosses the boundaries
and the next granule has a different tag the PE sets the TFSR_EL1.TF1 bit
as if an asynchronous tag fault is happened.
Enable Tag Check Override (TCO) in these functions before the load and
disable it afterwards to prevent this to happen.
Note: The same condition can be hit in MTE sync mode but we deal with it
through the exception handling.
In the current implementation, mte_async_mode flag is set only at boot
time but in future kasan might acquire some runtime features that
that change the mode dynamically, hence we disable it when sync mode is
selected for future proof.
Cc: Will Deacon <will@kernel.org>
Reported-by: Branislav Rankov <Branislav.Rankov@arm.com>
Tested-by: Branislav Rankov <Branislav.Rankov@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-6-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch_enable_tagging() was left in memory.h after the introduction of
async mode to not break the bysectability of the KASAN KUNIT tests.
Remove the function now that KASAN has been fully converted.
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-4-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
MTE provides an asynchronous mode for detecting tag exceptions. In
particular instead of triggering a fault the arm64 core updates a
register which is checked by the kernel after the asynchronous tag
check fault has occurred.
Add support for MTE asynchronous mode.
The exception handling mechanism will be added with a future patch.
Note: KASAN HW activates async mode via kasan.mode kernel parameter.
The default mode is set to synchronous.
The code that verifies the status of TFSR_EL1 will be added with a
future patch.
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Andrey Konovalov <andreyknvl@google.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-2-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210324122235.1059292-7-heiko@sntech.de
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210324122235.1059292-6-heiko@sntech.de
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210324122235.1059292-5-heiko@sntech.de
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210324122235.1059292-4-heiko@sntech.de
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
For the Engicam-boards this means a split as the core
boards contains the emmc while the commit baseboard handles
sdmmc and sdio.
Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210324122235.1059292-3-heiko@sntech.de
Even though KVM sets up MDCR_EL2 to trap accesses to the SPE buffer and
sampling control registers and to inject an undefined exception, the
presence of FEAT_SPE is still advertised in the ID_AA64DFR0_EL1 register,
if the hardware supports it. Getting an undefined exception when accessing
a register usually happens for a hardware feature which is not implemented,
and indeed this is how PMU emulation is handled when the virtual machine
has been created without the KVM_ARM_VCPU_PMU_V3 feature. Let's be
consistent and never advertise FEAT_SPE, because KVM doesn't have support
for emulating it yet.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210409152154.198566-3-alexandru.elisei@arm.com
KVM sets up MDCR_EL2 to trap accesses to the SPE buffer and sampling
control registers and it relies on the fact that KVM injects an undefined
exception for unknown registers. This mechanism of injecting undefined
exceptions also prints a warning message for the host kernel; for example,
when a guest tries to access PMSIDR_EL1:
[ 2.691830] kvm [142]: Unsupported guest sys_reg access at: 80009e78 [800003c5]
[ 2.691830] { Op0( 3), Op1( 0), CRn( 9), CRm( 9), Op2( 7), func_read },
This is unnecessary, because KVM has explicitly configured trapping of
those registers and is well aware of their existence. Prevent the warning
by adding the SPE registers to the list of registers that KVM emulates.
The access function will inject the undefined exception.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210409152154.198566-2-alexandru.elisei@arm.com
Change my e-mail address to kabel@kernel.org, and fix my name in
non-code parts (add diacritical mark).
Link: https://lkml.kernel.org/r/20210325171123.28093-2-kabel@kernel.org
Signed-off-by: Marek Behún <kabel@kernel.org>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This adds RPMh regulators, coresight, AOSS qmp, ipcc, llcc for the
SC7280. It adds interconnect, PRNG and thermal pieces to SM8350. It
specifies the now required clocks for the SDM845 gcc, corrects the
firmware-name for adsp and cdsp on the db845c and defines DSI and panel
bits for Xiaomi Pocophone F1.
SM8150 gains iommu settings and the remaining I2C controllers and SM8250
gains Venus and the QMP PHY is updated to include the DP portion.
It adds the MSM8998 based OnePlus 5/5T device and enables sound support
on the Trogdor device family.
Lastly it adds the GIC hypervisor registers & interrupt for when Linux
is booted in EL2 on MSM8916.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmBwgw4bHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FWXoQAKpPf+oQc+wVvoGCk35T
Xq5MFxJvm69Ad2TjCgRkyKrb1Op02PlrzJT5CNTt8d2OZjiLH4VZnv6b6e5z8sEA
1PbAID09tCLxE6j2KV6RCt4L9JGslT6eQ2HQWCCIjte8ygI3meyjjsGr3j1BJcJM
0GdLp1UTvlcItQcVymf6OLw0z69hvNuOiEAaQ1BNF+Y9VRhM940nS35D/0vhZpdQ
fP8aeCslAnu020g88P0uJESEsCQPLjywBHK2JlyYmzZzr9/OZnJvETUG6fkMjxQ/
TnJiuaGBDk//yhULYxt0t2Xi1gK76snkTLKx09p6a/GBIyNgTUW7MdEPw3n14FL9
cuFpFTZTTKw0HtaHtu2HtM/WFlBE92XlWKSKTfsVI/qR9LJn+6p6Ewi61evsg04U
+z8RI+rOD/lOXbU6VtYbdPE7wTkNk4+vTTPzAWSsNr7GtuGoNR3Qb693PwV2gsdl
BgkxR5sZDZAesa7tfpeZnB57fOq3N9iZHbdQWx/JaEyvou24LjHchWQv8o0xN8Av
P67PlfMM6tqt5jFSs8aLp9C6bsZjkzX4OnhP7p6ah39YlR6/pNh32pk74+DSspF2
e/XyH4gO0zTJ6DgPozPBz70epH5ToDXQQEbcKQ+huFUtSOjNDdlrSKouGPcRufIn
c8fgySvA9ChVIFwxju9+/Urs
=7juS
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
More Qualcomm ARM64 DT updates for 5.13
This adds RPMh regulators, coresight, AOSS qmp, ipcc, llcc for the
SC7280. It adds interconnect, PRNG and thermal pieces to SM8350. It
specifies the now required clocks for the SDM845 gcc, corrects the
firmware-name for adsp and cdsp on the db845c and defines DSI and panel
bits for Xiaomi Pocophone F1.
SM8150 gains iommu settings and the remaining I2C controllers and SM8250
gains Venus and the QMP PHY is updated to include the DP portion.
It adds the MSM8998 based OnePlus 5/5T device and enables sound support
on the Trogdor device family.
Lastly it adds the GIC hypervisor registers & interrupt for when Linux
is booted in EL2 on MSM8916.
* tag 'qcom-arm64-for-5.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (25 commits)
arm64: dts: qcom: update usb qmp phy clock-cells property
arm64: dts: qcom: msm8916: Add GICv2 hypervisor registers/interrupt
arm64: dts: sdm845-db845c: make firmware filenames follow linux-firmware
arm64: dts: qcom: sdm845-xiaomi-beryllium: Add DSI and panel bits
arm64: dts: qcom: sc7280: Add Coresight support
arm64: dts: qcom: sc7280: Add AOSS QMP node
arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
arm64: dts: qcom: sc7280: Add device tree node for LLCC
arm64: dts: qcom: Add support for OnePlus 5/5T
arm64: dts: qcom: msm8998: Disable MSS remoteproc by default
arm64: dts: qcom: Move rmtfs memory region
arm64: dts: qcom: Add sound node for sc7180-trogdor-coachz
arm64: dts: qcom: sc7180-trogdor: Add lpass dai link for I2S driver
arm64: dts: qcom: use dp_phy to provide clocks to dispcc
arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode
arm64: dts: qcom: sm8250: Add venus DT node
arm64: dts: qcom: sm8250: Add videocc DT node
arm64: dts: qcom: sm8350: Add interconnects
arm64: dts: qcom: sm8350: Add support for PRNG EE
arm64: dts: qcom: sc7280: Add RPMh regulators for sc7280-idp
...
Link: https://lore.kernel.org/r/20210409163949.776530-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On vcpu reset, we expect all the registers to be brought back
to their initial state, which happens to be a bunch of zeroes.
However, some recent commit broke this, and is now leaving a bunch
of registers (such as the FP state) with whatever was left by the
guest. My bad.
Zero the reset of the state (32bit SPSRs and FPSIMD state).
Cc: stable@vger.kernel.org
Fixes: e47c2055c6 ("KVM: arm64: Make struct kvm_regs userspace-only")
Signed-off-by: Marc Zyngier <maz@kernel.org>
With CONFIG_CFI_CLANG, the compiler replaces function pointers with
jump table addresses, which breaks dynamic ftrace as the address of
ftrace_call is replaced with the address of ftrace_call.cfi_jt. Use
function_nocfi() to get the address of the actual function instead.
Suggested-by: Ben Dai <ben.dai@unisoc.com>
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210408182843.1754385-17-samitolvanen@google.com
__apply_alternatives makes indirect calls to functions whose address
is taken in assembly code using the alternative_cb macro. With
non-canonical CFI, the compiler won't replace these function
references with the jump table addresses, which trips CFI. Disable CFI
checking in the function to work around the issue.
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210408182843.1754385-16-samitolvanen@google.com
Disable CFI checking for functions that switch to linear mapping and
make an indirect call to a physical address, since the compiler only
understands virtual addresses and the CFI check for such indirect calls
would always fail.
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210408182843.1754385-15-samitolvanen@google.com
With CONFIG_CFI_CLANG, the compiler replaces function address
references with the address of the function's CFI jump table
entry. This means that __pa_symbol(function) returns the physical
address of the jump table entry, which can lead to address space
confusion as the jump table points to the function's virtual
address. Therefore, use the function_nocfi() macro to ensure we are
always taking the address of the actual function instead.
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210408182843.1754385-14-samitolvanen@google.com
With CONFIG_CFI_CLANG, the compiler replaces function addresses in
instrumented C code with jump table addresses. This change implements
the function_nocfi() macro, which returns the actual function address
instead.
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210408182843.1754385-13-samitolvanen@google.com
list_sort() internally casts the comparison function passed to it
to a different type with constant struct list_head pointers, and
uses this pointer to call the functions, which trips indirect call
Control-Flow Integrity (CFI) checking.
Instead of removing the consts, this change defines the
list_cmp_func_t type and changes the comparison function types of
all list_sort() callers to use const pointers, thus avoiding type
mismatches.
Suggested-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Tested-by: Nick Desaulniers <ndesaulniers@google.com>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210408182843.1754385-10-samitolvanen@google.com
This enables the SM8350 TLMM and GCC drivers, needed to boot the
platform.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmBp7XsbHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FH8YP/0eBFr+4HDacw90lt5cy
vWkEX+yXymuFb9HtHRG69bgNMUPNRPDl6sR7Jdq6Clb5LaE541XdhrHYeWtdNCNK
LSZyuqgMj3+kqtIsvNKCOQ1vxuwfd893dlX0mOKIMHl7OW4ti6MDsl9uFQZyVfeG
yuPYo2iIgmZYPssLKUfOkUWc41mV1M7RWeOXGPawbmtwb1BjjJ8dNtngvpV0sQTZ
YOqx+fivcI0v5wUfBNQs5zYa1pzDb6+7WxLLyJfqZ8qO3DJRAO7KIXhCoSKDnhAr
wYTJpvK26a09q1jW5MRaMHBQdELbd+1C8WCJyogxvXWTMUV/X7WbctoLZ/Y1dmqO
difsC6a3Vxj7NXxpeFvhz0ZmBYV53N4eMEHnU6wcKtSse2lPNZN//8+ohj+cC7hK
pca3B1p6o7S5Y3bL9Iy/T+zEuSAXu41vpzUI5dqmuSjkex38el/ymxzKM6wzEZU2
OHp9Lrcbek+jd1hjwixN/4KISO8HjWqAsWvGMLUCoMao/lQqP03kmE8AOJq0IKMm
YpsafVq1pUbjDc6KDgs8wxPOIAwQUXM0quF+2Bo8z0madeKxVAuz6t8A8DrxATaG
8BRvk1MWMAEKrQ6ycThFy2cNjr9BY3liI/r0j78Ote9K1xMSC+cFt0fnG5fr+JUT
/aZl/9lpE68RuOK7IKUIJF0h
=3aF9
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/defconfig
Qualcomm ARM64 defconfig udpate for 5.13
This enables the SM8350 TLMM and GCC drivers, needed to boot the
platform.
* tag 'qcom-arm64-defconfig-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable Qualcomm SM8350 TLMM and GCC
Link: https://lore.kernel.org/r/20210404164841.712845-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
CONFIG_ARM64_VHE was introduced with ARMv8.1 (some 7 years ago),
and has been enabled by default for almost all that time.
Given that newer systems that are VHE capable are finally becoming
available, and that some systems are even incapable of not running VHE,
drop the configuration altogether.
Anyone willing to stick to non-VHE on VHE hardware for obscure
reasons should use the 'kvm-arm.mode=nvhe' command-line option.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210408131010.1109027-4-maz@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
It seems that the CPUs part of the SoC known as Apple M1 have the
terrible habit of being stuck with HCR_EL2.E2H==1, in violation
of the architecture.
Try and work around this deplorable state of affairs by detecting
the stuck bit early and short-circuit the nVHE dance. Additional
filtering code ensures that attempts at switching to nVHE from
the command-line are also ignored.
It is still unknown whether there are many more such nuggets
to be found...
Reported-by: Hector Martin <marcan@marcan.st>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210408131010.1109027-3-maz@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Some CPUs are broken enough that some overrides need to be rejected
at the earliest opportunity. In some cases, that's right at cpu
feature override time.
Provide the necessary infrastructure to filter out overrides,
and to report such filtered out overrides to the core cpufeature code.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210408131010.1109027-2-maz@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses
to small sets of registers and instructions from EL1 and EL0. Currently
Linux makes no use of this feature, ensure that it is not active at boot by
disabling the traps during EL2 setup.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210401180942.35815-3-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
mte_assign_mem_tag_range() was added in commit 85f49cae4d
("arm64: mte: add in-kernel MTE helpers") in 5.11 but moved out of
mte.S by commit 2cb3427642 ("arm64: kasan: simplify and inline
MTE functions") in 5.12 and renamed to mte_set_mem_tag_range().
2cb3427642 did not delete the old function prototypes in mte.h.
Remove the unused prototype from mte.h.
Cc: Will Deacon <will@kernel.org>
Reported-by: Derrick McKee <derrick.mckee@gmail.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210407133817.23053-1-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
They are not needed after booting, so mark them as __init to move them
to the .init section.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20210330135449.4dcffd7f@xhacker.debian
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
When we enable SVE usage in userspace after taking a SVE access trap we
need to ensure that the portions of the register state that are not
shared with the FPSIMD registers are zeroed. Currently we do this by
forcing the FPSIMD registers to be saved to the task struct and converting
them there. This is wasteful in the common case where the task state is
loaded into the registers and we will immediately return to userspace
since we can initialise the SVE state directly in registers instead of
accessing multiple copies of the register state in memory.
Instead in that common case do the conversion in the registers and
update the task metadata so that we can return to userspace without
spilling the register state to memory unless there is some other reason
to do so.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210312190313.24598-1-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
MAINTAINERS maintainance, and a clk / reset switch to our headers.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYG2bAQAKCRDj7w1vZxhR
xW/cAQDpP3oAyk00M6ZMKIMefm/DQI3qbf9cA0P9JsPa1inNbAEA0WlHJt2zdGRT
ISRW7PI1TyHxMcVteyiw7gE5BvU7kAQ=
=Jgu5
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
One 32kHz clock fix for the beelink gs1, a CD polarity fix for the SoPine, some
MAINTAINERS maintainance, and a clk / reset switch to our headers.
* tag 'sunxi-fixes-for-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h6: beelink-gs1: Remove ext. 32 kHz osc reference
MAINTAINERS: Match on allwinner keyword
MAINTAINERS: Add our new mailing-list
arm64: dts: allwinner: Fix SD card CD GPIO for SOPine systems
arm64: dts: allwinner: h6: Switch to macros for RSB clock/reset indices
Link: https://lore.kernel.org/r/9972a85e-60b7-49f4-a246-db3396dd4764.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The top-level node doesn't provide any clocks, the subnode provides a
single clock with of_clk_hw_simple_get.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20201123143705.14277-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The ARM Cortex-A53 CPU cores and QGIC2 interrupt controller
(an implementation of the ARM GIC 2.0 specification) used in MSM8916
support virtualization, e.g. for KVM on Linux. However, so far it was
not possible to make use of this functionality, because Qualcomm's
proprietary "hyp" firmware blocks the EL2 mode of the CPU and only
allows booting Linux in EL1.
However, on devices without (firmware) secure boot there is no need
to rely on all of Qualcomm's firmware. The "hyp" firmware on MSM8916
seems simple enough that it can be replaced with an open-source
alternative created only based on trial and error - with some similar
EL2/EL1 initialization code adapted from Linux and U-Boot.
qhypstub [1] is such an open-source firmware for MSM8916 that
can be used as drop-in replacement for Qualcomm's "hyp" firmware.
It does not implement any hypervisor functionality.
Instead, it allows booting Linux/KVM (or other hypervisors) in EL2.
With Linux booting in EL2, KVM seems to be working just fine on MSM8916.
However, so far it is not possible to make use of the virtualization
features in the GICv2. To use KVM's VGICv2 code, the QGIC2 device tree
node needs additional resources (according to binding documentation):
- The CPU interface region (second reg) must be at least 8 KiB large
to access the GICC_DIR register (mapped at 0x1000 offset)
- Virtual control/CPU interface register base and size
- Hypervisor maintenance interrupt
Fortunately, the public APQ8016E TRM [2] provides the required information:
- The CPU interface region (at 0x0B002000) actually has a size of 8 KiB
- Virtual control/CPU interface register is at 0x0B001000/0x0B004000
- Hypervisor maintenance interrupt is "PPI #0"
Note: This is a bit strange since almost all other ARM SoCs use
GIC_PPI 9 for this. However, I have verified that this is
indeed the interrupt that fires when bits are set in GICH_HCR.
Add the additional resources to the QGIC2 device tree node in msm8916.dtsi.
There is no functional difference when Linux is started in EL1 since the
additional resources are ignored in that case.
With these changes (and qhypstub), KVM seems to be fully working on
the DragonBoard 410c (apq8016-sbc) and BQ Aquaris X5 (longcheer-l8910).
[1]: https://github.com/msm8916-mainline/qhypstub
[2]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210407163648.4708-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Allow for a randomized stack offset on a per-syscall basis, with roughly
5 bits of entropy. (And include AAPCS rationale AAPCS thanks to Mark
Rutland.)
In order to avoid unconditional stack canaries on syscall entry (due to
the use of alloca()), also disable stack protector to avoid triggering
needless checks and slowing down the entry path. As there is no general
way to control stack protector coverage with a function attribute[1],
this must be disabled at the compilation unit level. This isn't a problem
here, though, since stack protector was not triggered before: examining
the resulting syscall.o, there are no changes in canary coverage (none
before, none now).
[1] a working __attribute__((no_stack_protector)) has been added to GCC
and Clang but has not been released in any version yet:
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=346b302d09c1e6db56d9fe69048acb32fbb97845https://reviews.llvm.org/rG4fbf84c1732fca596ad1d6e96015e19760eb8a9b
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210401232347.2791257-6-keescook@chromium.org
This currently supports:
* SMP (via spin-tables)
* AIC IRQs
* Serial (with earlycon)
* Framebuffer
A number of properties are dynamic, and based on system firmware
decisions that vary from version to version. These are expected
to be filled in by the loader.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This adds a Kconfig option to toggle support for Apple ARM SoCs.
At this time this targets the M1 and later "Apple Silicon" Mac SoCs.
Signed-off-by: Hector Martin <marcan@marcan.st>
These definitions are in arm-gic-v3.h for historical reasons which no
longer apply. Move them to sysreg.h so the AIC driver can use them, as
it needs to peek into vGIC registers to deal with the GIC maintentance
interrupt.
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Now that we have ioremap_np(), we can make pci_remap_cfgspace() default
to it, falling back to ioremap() on platforms where it is not available.
Remove the arm64 implementation, since that is now redundant. Future
cleanups should be able to do the same for other arches, and eventually
make the generic pci_remap_cfgspace() unconditional.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This is used on Apple ARM platforms, which require most MMIO
(except PCI devices) to be mapped as nGnRnE.
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
The implementor will be used to condition the FIQ support quirk.
The specific CPU types are not used at the moment, but let's add them
for documentation purposes.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Most of the changes again are devicetree fixes, but there are also five
trivial build fixes for issues I found when test building with gcc-11 or
when running 'make W=1', and some OMAP platform specific code fixups.
Broadcom
- One revert for a Raspberry pi interrupt controller change that
caused a regression.
TI OMAP:
- Remove unused duplicate sha2md5_fck clock node that can race with the
OMAP4_SHA2MD5_CLKCTRL clock node for disable for unused clocks
- Add aliases for omap4/5 mmc to put the slots back into the right
order again
- Fix typo for bionic voltage controllers that accidentally use mpu
for all instances instead of mpu, core and iva
- Fix random hangs for droid4 caused by missing fix from TI Android
kernel tree to do a dummy smc call on cpuidle wakeup path
NXP i.MX:
- Fix a system failure on imx6qdl-phytec-pfla02 board when booting from
SD, by adding missing vmmc supply for SD interfaces.
- Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2 definition.
Marvell mvebu:
- Fix storm interrupt on Turris Omnia
- Enable hardware buffer management as it should be
Build fixes for PXA, Freescale, Marvell, OMAP1 an Keystone.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmBs0OgACgkQYKtH/8kJ
UifdEBAAiD3JebS8a1jsgL+/va/ptOuBZP2l4sCH3P/bczsNKeAn+BvwAy4jNJ4b
C55ZFnz6tX37CGY7e1Pe7LC8WhVd1LGfCm/gSreKUTkETZd/87PoR1xM4GxbhmBQ
8HNJOVDBSes6tHgWTAgQ7rHGQQ71JoRYc9FJPOH2JDsk8SaeL8Z+Bjay3O3nlBQw
RU0zoWv/khkdRvzt4oDTmW6pPDQh5c9twv2ORZM92+tXhSeF2AAY08GdAAmiZL5W
Lq30YozGSJHPcIYSN+jSWPJNtzmrF3oZVTqDzqTN/aIVoH+8MFZHSmCd3iM1RWkT
wkanNiqF7CRYAdLmC00YTToJUQxsbOYugfUMWYC04VocVbeEDAhnITFVF1zrJLZ4
q4E/S5WSZjLPUsiDhSK+d0S2bFVrEyQUaDaFWrC6Aet5wA6pI/8X0Q3ZSMV7jzq+
NkZYuA2oKoW0vwnH+7432/1g33CpCxKRVr/zBhesjCpB3Ymj0OWfqGeHA2fyjFQq
fNvUnG6LyXE+NBgIfgZTGbBr1gCT/XHqd0GcYrBy4v0L3x8qJSh1ClA0qlpWr+Zl
mY5jMC6MrGGuHXEhqIoS38mO0RTyx9i2iDjge2CrAMmRxdVR453Z4VIbDnSwGDAe
K8lASQKHEyvRzdmJDVhaesHqwU9BDtWULY8Q2+3jKqv3wwf6d0I=
=YY35
-----END PGP SIGNATURE-----
Merge tag 'arm-fixes-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"Most of the changes again are devicetree fixes, but there are also
five trivial build fixes for issues I found when test building with
gcc-11 or when running 'make W=1', and some OMAP platform specific
code fixups.
Broadcom:
- One revert for a Raspberry pi interrupt controller change that
caused a regression.
TI OMAP:
- Remove unused duplicate sha2md5_fck clock node that can race with
the OMAP4_SHA2MD5_CLKCTRL clock node for disable for unused clocks
- Add aliases for omap4/5 mmc to put the slots back into the right
order again
- Fix typo for bionic voltage controllers that accidentally use mpu
for all instances instead of mpu, core and iva
- Fix random hangs for droid4 caused by missing fix from TI Android
kernel tree to do a dummy smc call on cpuidle wakeup path
NXP i.MX:
- Fix a system failure on imx6qdl-phytec-pfla02 board when booting
from SD, by adding missing vmmc supply for SD interfaces.
- Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2
definition.
Marvell mvebu:
- Fix storm interrupt on Turris Omnia
- Enable hardware buffer management as it should be
... and build fixes for PXA, Freescale, Marvell, OMAP1 and Keystone"
* tag 'arm-fixes-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin
ARM: dts: turris-omnia: fix hardware buffer management
Revert "arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts"
ARM: mvebu: avoid clang -Wtautological-constant warning
ARM: pxa: mainstone: avoid -Woverride-init warning
ARM: omap1: fix building with clang IAS
soc/fsl: qbman: fix conflicting alignment attributes
ARM: keystone: fix integer overflow warning
ARM: dts: imx6: pbab01: Set vmmc supply for both SD interfaces
arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
ARM: OMAP4: PM: update ROM return address for OSWR and OFF
ARM: OMAP4: Fix PMIC voltage domains for bionic
ARM: dts: Fix moving mmc devices with aliases for omap4 & 5
ARM: dts: Drop duplicate sha2md5_fck to fix clk_disable race
Revert "ARM: dts: bcm2711: Add the BSC interrupt controller"
Add GPIO line-name identifiers to the ODROID N2/N2+ common dtsi.
Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210407042609.9736-4-christianshewitt@gmail.com
Add the meson saradc node to the ODROID N2/N2+ common dtsi.
Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210407042609.9736-3-christianshewitt@gmail.com
Remove an extra tab from the ext_mdio node in the ODROID N2/N2+ common
dtsi file.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210407042609.9736-2-christianshewitt@gmail.com
When a VCPU is created, the kvm_vcpu struct is initialized to zero in
kvm_vm_ioctl_create_vcpu(). On VHE systems, the first time
vcpu.arch.mdcr_el2 is loaded on hardware is in vcpu_load(), before it is
set to a sensible value in kvm_arm_setup_debug() later in the run loop. The
result is that KVM executes for a short time with MDCR_EL2 set to zero.
This has several unintended consequences:
* Setting MDCR_EL2.HPMN to 0 is constrained unpredictable according to ARM
DDI 0487G.a, page D13-3820. The behavior specified by the architecture
in this case is for the PE to behave as if MDCR_EL2.HPMN is set to a
value less than or equal to PMCR_EL0.N, which means that an unknown
number of counters are now disabled by MDCR_EL2.HPME, which is zero.
* The host configuration for the other debug features controlled by
MDCR_EL2 is temporarily lost. This has been harmless so far, as Linux
doesn't use the other fields, but that might change in the future.
Let's avoid both issues by initializing the VCPU's mdcr_el2 field in
kvm_vcpu_vcpu_first_run_init(), thus making sure that the MDCR_EL2 register
has a consistent value after each vcpu_load().
Fixes: d5a21bcc29 ("KVM: arm64: Move common VHE/non-VHE trap config in separate functions")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210407144857.199746-3-alexandru.elisei@arm.com
Implement the hypervisor side of the KVM PTP interface.
The service offers wall time and cycle count from host to guest.
The caller must specify whether they want the host's view of
either the virtual or physical counter.
Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201209060932.212364-7-jianyong.wu@arm.com
We needn't retrieve the memory slot again in user_mem_abort() because
the corresponding memory slot has been passed from the caller. This
would save some CPU cycles. For example, the time used to write 1GB
memory, which is backed by 2MB hugetlb pages and write-protected, is
dropped by 6.8% from 928ms to 864ms.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210316041126.81860-4-gshan@redhat.com
find_vma_intersection() has been existing to search the intersected
vma. This uses the function where it's applicable, to simplify the
code.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210316041126.81860-3-gshan@redhat.com
We needn't expose the function as it's only used by mmu.c since it
was introduced by commit c64735554c ("KVM: arm: Add initial dirty
page locking support").
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210316041126.81860-2-gshan@redhat.com
This extends the initial SM8350 description merged in v5.12 with
CPUfreq, SMMU, UFS, RPMHPD, SPMI, USB and remoteproc support. It adds
initial PMIC definitions for the 6 PMICs found on the MTP and it
introduces the new SM8350 Hardware Development Kit (HDK).
SC7180 is further polished, the DisplayPort portion of the QMP phy is
defined and several new SKUs of the Trogdor devices are introduced.
The new SC7280 platform is introduced, with RPMH, RPMHPD, RPMCC, SPMI,
CPU idle, SMMU and watchdog defined.
SDM845 gains the camera related nodes and some cleanups.
For SM8250 it brings some cleanups and migrates SPI0 to use GPIO for
chip select.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmBp7RwbHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FQJsP/RI7bv+1TtFlzxUSnhxy
AOhvA7siJLIOxsfoeUZPsG4bxsuRL0mkDeu/NyuZfmpp0CUcYs4/fZUascmYGT1J
bRiBUWq9Iscfd9GIO3IRS9YOteUJu8NQi1GCHjlfxiet+cqG/enKa5Xdqh7qgtpw
E+tIM5NOe+06u1gU5h+6hbJTlZgK3s74JQ4ui5aO9VBVi8VyPwxIxZS5/li1M7pg
AEVJZ3zVhQfmxiEjO1ljTYf4HdD4K4f4e3qiBabhlFaHjly0FIDxtl9GT3vjee3Z
nMVNG3LZauNcw2MRwGWRB8t1gheUJG4M3e3XgTazPIbyNx1zpyypMGzF7w/je6cR
YVtlKorQ7HEqx3Pd8nc0oMXeRS4ZrzDeHWz0kJoa9eOr67fdDpz/3HJEgTp+VgUI
D8KcLeWxg5LfJe53rXLg+Vga0AFYLu62hQC91RaH2ksS6AV3A9b7W7puRSJHiFhU
ncsCOiFb2yNHP9v9JIvP8Dek0cx99rIX0BzvCb2GqAke+9JZhsAteua8eN0otMoq
XRiRJP3mgL9F+MKwrgbWIKrethrM6UGKEzB5Afv/yitRLDUAKcTSTYIRr8Du51qH
vmT2FKk9iJ7X1LKm32SPh40ScxuHAv1DG6xxHGEPtcuG6c/Af7wnyytXiuDPwBLj
ZkOThaE7Yh2mMvhZGBrW+/VC
=a6Po
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DT updates for 5.13
This extends the initial SM8350 description merged in v5.12 with
CPUfreq, SMMU, UFS, RPMHPD, SPMI, USB and remoteproc support. It adds
initial PMIC definitions for the 6 PMICs found on the MTP and it
introduces the new SM8350 Hardware Development Kit (HDK).
SC7180 is further polished, the DisplayPort portion of the QMP phy is
defined and several new SKUs of the Trogdor devices are introduced.
The new SC7280 platform is introduced, with RPMH, RPMHPD, RPMCC, SPMI,
CPU idle, SMMU and watchdog defined.
SDM845 gains the camera related nodes and some cleanups.
For SM8250 it brings some cleanups and migrates SPI0 to use GPIO for
chip select.
* tag 'qcom-arm64-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (79 commits)
arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS
arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS
arm64: dts: qcom: sm8250: further split of spi pinctrl config
arm64: dts: qcom: sm8250: split spi pinctrl config
arm64: dts: qcom: sdm845-db845c: Enable ov8856 sensor and connect to ISP
arm64: dts: qcom: sdm845-db845c: Configure regulators for camss node
arm64: dts: qcom: sdm845: Add CAMSS ISP node
arm64: dts: qcom: pm8150: Enable RTC
arm64: dts: qcom: sm8350-mtp: Add PMICs
arm64: dts: qcom: pmr735B: Add base dts file
arm64: dts: qcom: pmr735a: Add base dts file
arm64: dts: qcom: pm8350c: Add base dts file
arm64: dts: qcom: pm8350b: Add base dts file
arm64: dts: qcom: pm8350: Add base dts file
arm64: dts: qcom: pmk8350: Add base dts file
arm64: dts: qcom: sm8350: Add spmi node
arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881x
dt-bindings: arm: qcom: Add SM8350 HDK
arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdor
arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'
...
Link: https://lore.kernel.org/r/20210404164914.712946-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add DT for fan control on SolidRun Clearfog GT8k platform
Add syscon compatible to NB clk node allowing improving cpufreq
support on Armada 37xx
Add support for UTMI PHY allowing removing kernel dependency from the
boot loader for UBS port connected to this PHY (Armada 7K, 8K and
CN91xx)
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCYGeE7AAKCRALBhiOFHI7
1RLbAJ9PYflp+wQ8QZRza75fOOsvfY9m2ACfRe+U9StkSx9+wD6lxiTcUiYbjfc=
=OYlz
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt
mvebu dt64 for 5.13 (part 1)
Add DT for fan control on SolidRun Clearfog GT8k platform
Add syscon compatible to NB clk node allowing improving cpufreq
support on Armada 37xx
Add support for UTMI PHY allowing removing kernel dependency from the
boot loader for UBS port connected to this PHY (Armada 7K, 8K and
CN91xx)
* tag 'mvebu-dt64-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: enable CP110 UTMI PHY usage
arm64: dts: marvell: add support for Marvell CP110 UTMI PHY
arm64: dts: marvell: armada-37xx: add syscon compatible to NB clk node
arm64: dts: marvell: clearfog-gt-8k: add cooling maps
arm64: dts: marvell: clearfog-gt-8k: add pwm-fan
Link: https://lore.kernel.org/r/874kgocs7t.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
adding:
- New secondary interrupt controller binding to support the wake-up
- Use the RSB bus instead of I2C for the PMIC on the H6
- HDMI support for the BananaPi M2-Zero
- New board: Topwise A721
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYGchiwAKCRDj7w1vZxhR
xW1/APsFH9bywTduCrsuJui1LdD3mVbhkN75tKfBw7Ce8rmloAD/U5dth8PKA4h6
yPCdc2k0XaK7ItcD3eveN2uwiNq89gU=
=Ktsz
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual bunch of patches to support the Allwinner SoCs, this time
adding:
- New secondary interrupt controller binding to support the wake-up
- Use the RSB bus instead of I2C for the PMIC on the H6
- HDMI support for the BananaPi M2-Zero
- New board: Topwise A721
* tag 'sunxi-dt-for-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: h3: beelink-x2: Add power button
arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection
ARM: dts: sunxi: h2-plus-bananapi-m2-zero: Add HDMI out
ARM: dts: sun4i: Add support for Topwise A721 tablet
dt-bindings: arm: Add Topwise A721
arm64: dts: allwinner: Move wakeup-capable IRQs to r_intc
arm64: dts: allwinner: Use the new r_intc binding
ARM: dts: sunxi: Move wakeup-capable IRQs to r_intc
ARM: dts: sunxi: h3/h5: Add r_intc node
ARM: dts: sunxi: Use the new r_intc binding
Link: https://lore.kernel.org/r/8a3e3271-bebe-4d27-a9e7-7b7a6311a38d.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Video IN (VIN) and Camera (CSI-2) support for the R-Car M3-W+ SoC,
- LED support for the Falcon development board,
- Preparatory display pipeline support for the R-Car V3U SoC,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYGbVawAKCRCKwlD9ZEnx
cEgrAP9eZ3MAYaiATSSPB4KvErvRYc9dqMgHWfHX7Su+LpyPZAD/ViFlg1drXMNV
HNo3oZUWTChPek4zbe7EUcjpLhWzawk=
=fkRt
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.13 (take two)
- Video IN (VIN) and Camera (CSI-2) support for the R-Car M3-W+ SoC,
- LED support for the Falcon development board,
- Preparatory display pipeline support for the R-Car V3U SoC,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: ulcb: Add cpu-supply property to a57_0 node
arm64: dts: renesas: salvator-common: Add cpu-supply property to a57_0 node
arm64: dts: renesas: r8a77950: Drop operating points above 1.5 GHz
arm64: dts: renesas: r8a779a0: Fix PMU interrupt
arm64: dts: renesas: r8a779a0: Add VSPD support
arm64: dts: renesas: r8a779a0: Add FCPVD support
arm64: dts: renesas: falcon-cpu: Add GP LEDs
arm64: dts: renesas: r8a77961: Add VIN and CSI-2 device nodes
ARM: dts: koelsch: Configure pull-up for SOFT_SW GPIO keys
arm64: dts: renesas: falcon: Move AVB0 to main DTS
arm64: dts: renesas: falcon: Move watchdog config to CPU board DTS
arm64: dts: renesas: falcon: Move console config to CPU board DTS
Link: https://lore.kernel.org/r/cover.1617359678.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Although every Beelink GS1 seems to have external 32768 Hz oscillator,
it works only on one from four tested. There are more reports of RTC
issues elsewhere, like Armbian forum.
One Beelink GS1 owner read RTC osc status register on Android which
shipped with the box. Reported value indicated problems with external
oscillator.
In order to fix RTC and related issues (HDMI-CEC and suspend/resume with
Crust) on all boards, switch to internal oscillator.
Fixes: 32507b8681 ("arm64: dts: allwinner: h6: Move ext. oscillator to board DTs")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210330184218.279738-1-jernej.skrabec@siol.net
Commit 941432d007 ("arm64: dts: allwinner: Drop non-removable from
SoPine/LTS SD card") enabled the card detect GPIO for the SOPine module,
along the way with the Pine64-LTS, which share the same base .dtsi.
However while both boards indeed have a working CD GPIO on PF6, the
polarity is different: the SOPine modules uses a "push-pull" socket,
which has an active-high switch, while the Pine64-LTS use the more
traditional push-push socket and the common active-low switch.
Fix the polarity in the sopine.dtsi, and overwrite it in the LTS
board .dts, to make the SD card work again on systems using SOPine
modules.
Fixes: 941432d007 ("arm64: dts: allwinner: Drop non-removable from SoPine/LTS SD card")
Reported-by: Ashley <contact@victorianfox.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210316144219.5973-1-andre.przywara@arm.com
The macros for the clock and reset indices for the RSB hardware block
were replaced with raw numbers when the RSB controller node was added.
This was done to avoid cross-tree dependencies.
Now that both the clk and DT changes have been merged, we can switch
back to using the macros.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
For a nvhe host, the EL2 must allow the EL1&0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the guest. Also, before
entering the guest, we must flush any trace data if the
TRBE was enabled. And we must prohibit the generation
of trace while we are in EL1 by clearing the TRFCR_EL1.
For vhe, the EL2 must prevent the EL1 access to the Trace
Buffer.
The MDCR_EL2 bit definitions for TRBE are available here :
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405164307.1720226-8-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
At the moment, we check the availability of SPE on the given
CPU (i.e, SPE is implemented and is allowed at the host) during
every guest entry. This can be optimized a bit by moving the
check to vcpu_load time and recording the availability of the
feature on the current CPU via a new flag. This will also be useful
for adding the TRBE support.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Alexandru Elisei <Alexandru.Elisei@arm.com>
Cc: James Morse <james.morse@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405164307.1720226-7-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Rather than falling to an "unhandled access", inject add an explicit
"undefined access" for TRFCR_EL1 access from the guest.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405164307.1720226-6-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
mvebu fixes for 5.12 (part 1)
2 fixes on on turris-omnia (Armada 38x based:)
- Fix storm interrupt
- Enable hardware buffer management as it should be
Unbreak AHCI on all Marvell Armada 7k8k / CN913x platforms
* tag 'mvebu-fixes-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin
ARM: dts: turris-omnia: fix hardware buffer management
Revert "arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts"
Link: https://lore.kernel.org/r/87a6qgctit.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit 23bde34771 ("KVM: arm64: vgic-v3: Drop the
reporting of GICR_TYPER.Last for userspace") temporarily fixed
a bug identified when attempting to access the GICR_TYPER
register before the redistributor region setting, but dropped
the support of the LAST bit.
Emulating the GICR_TYPER.Last bit still makes sense for
architecture compliance though. This patch restores its support
(if the redistributor region was set) while keeping the code safe.
We introduce a new helper, vgic_mmio_vcpu_rdist_is_last() which
computes whether a redistributor is the highest one of a series
of redistributor contributor pages.
With this new implementation we do not need to have a uaccess
read accessor anymore.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-9-eric.auger@redhat.com
To improve the readability, we introduce the new
vgic_v3_free_redist_region helper and also rename
vgic_v3_insert_redist_region into vgic_v3_alloc_redist_region
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-8-eric.auger@redhat.com
vgic_uaccess() takes a struct vgic_io_device argument, converts it
to a struct kvm_io_device and passes it to the read/write accessor
functions, which convert it back to a struct vgic_io_device.
Avoid the indirection by passing the struct vgic_io_device argument
directly to vgic_uaccess_{read,write}.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-7-eric.auger@redhat.com
On vgic_dist_destroy(), the addresses are not reset. However for
kvm selftest purpose this would allow to continue the test execution
even after a failure when running KVM_RUN. So let's reset the
base addresses.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-5-eric.auger@redhat.com
vgic_v3_insert_redist_region() may succeed while
vgic_register_all_redist_iodevs fails. For example this happens
while adding a redistributor region overlapping a dist region. The
failure only is detected on vgic_register_all_redist_iodevs when
vgic_v3_check_base() gets called in vgic_register_redist_iodev().
In such a case, remove the newly added redistributor region and free
it.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-4-eric.auger@redhat.com
The doc says:
"The characteristics of a specific redistributor region can
be read by presetting the index field in the attr data.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3"
Unfortunately the existing code fails to read the input attr data.
Fixes: 04c1109322 ("KVM: arm/arm64: Implement KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION")
Cc: stable@vger.kernel.org#v4.17+
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-3-eric.auger@redhat.com
KVM_DEV_ARM_VGIC_GRP_ADDR group doc says we should return
-EEXIST in case the base address of the redist is already set.
We currently return -EINVAL.
However we need to return -EINVAL in case a legacy REDIST address
is attempted to be set while REDIST_REGIONS were set. This case
is discriminated by looking at the count field.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405163941.510258-2-eric.auger@redhat.com
Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.
Fixes: eeeee7193d ("KVM: arm64: Bootstrap PSCI SMC handler in nVHE EL2")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210406121759.5407-1-wangwensheng4@huawei.com
Enabling the Display panel for beryllium requires DSI
labibb regulators and panel dts nodes to be added.
It is also required to keep some of the regulators as
always-on.
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210404194437.537011-1-amit.pundir@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add coresight components found on SC7280 SoC.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/de07324628f88900b72357f4ef7f0c7db7e3409d.1615832893.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the IPCC DT node which is used to send and receive IPC
signals with remoteprocs for SC7280 SoC.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/8374f407386209d2e7891763de3fa2450a14ad60.1615832893.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add device trees for OnePlus 5 (cheeseburger) and 5T (dumpling)
MSM8998 SoC smartphones with initial support included for:
- UFS internal storage
- USB peripheral mode
- Display
- Touch
- Bluetooth
- Hall effect sensor
- Power and volume buttons
- Capacitive keypad button backlight (on cheeseburger)
Signed-off-by: Jami Kettunen <jamipkettunen@gmail.com>
Link: https://lore.kernel.org/r/20210406010708.2376807-2-jamipkettunen@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This was already the case for ADSP and SLPI remoteprocs & doesn't affect
existing boards where it has been re-enabled.
Signed-off-by: Jami Kettunen <jamipkettunen@gmail.com>
Link: https://lore.kernel.org/r/20210406010708.2376807-3-jamipkettunen@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Move rmtfs memory region so that it does not overlap with system
RAM (kernel data) when KAsan is enabled. This puts rmtfs right
after mba_mem which is not supposed to increase beyond 0x94600000
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sujit Kautkar <sujitka@chromium.org>
Link: https://lore.kernel.org/r/20210330014610.1451198-1-sujitka@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is a trgodor variant, required to have sound node variable
for coachz specific platform.
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210314061054.19451-3-srivasam@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add dai link for supporting lpass I2S driver, which is used
for audio capture and playback.
Add lpass-cpu node with pin controls and i2s primary
and secondary dai-links.
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Ajit Pandey <ajitp@codeaurora.org>
Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org>
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Link: https://lore.kernel.org/r/20210314061054.19451-2-srivasam@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
RNG (Random Number Generator) in SM8350 features PRNG EE (Execution
Environment), hence add devicetree support for it.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210401101536.1014560-1-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add regulator devices for SC7280 as RPMh regulators. This ensures
that consumers are able to modify the physical state of PMIC
regulators.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1617192339-3760-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Enable support for CP110 UTMI PHY in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add support for Marvell CP110 UTMI PHY in a CP11x DTSI
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The driver part of this support was not merged which leads to break
AHCI on all Marvell Armada 7k8k / CN913x platforms as it was reported
by Marcin Wojtas.
So for now let's remove it in order to fix the issue waiting for the
driver part really be merged.
This reverts commit 53e950d597.
Fixes: 53e950d597 ("arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts")
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add "syscon" compatible to the North Bridge clocks node to allow the
cpufreq driver to access these registers via syscon API.
This is needed for a fix of cpufreq driver.
Signed-off-by: Marek Behún <kabel@kernel.org>
Fixes: e8d66e7927 ("arm64: dts: marvell: armada-37xx: add nodes...")
Cc: stable@vger.kernel.org
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add cooling maps suitable for a Noctua NF-A4/10 fan attached to the
heat sink. The fan will toggle between two speeds in operation which
seems to be normal behaviour. More fine-grained steps may help to
reduce this.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add pwm-fan support for controlling the fan speed.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
After the node name of "snps,dwc3" has been corrected to start with "usb"
in fsl,imx8mp-dwc3.yaml. Its name in dts should be modified accordingly.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20210329072714.2135-3-thunder.leizhen@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
gcc-11 points out a mismatch between the declaration and the definition
of poly1305_core_setkey():
lib/crypto/poly1305-donna32.c:13:67: error: argument 2 of type ‘const u8[16]’ {aka ‘const unsigned char[16]’} with mismatched bound [-Werror=array-parameter=]
13 | void poly1305_core_setkey(struct poly1305_core_key *key, const u8 raw_key[16])
| ~~~~~~~~~^~~~~~~~~~~
In file included from lib/crypto/poly1305-donna32.c:11:
include/crypto/internal/poly1305.h:21:68: note: previously declared as ‘const u8 *’ {aka ‘const unsigned char *’}
21 | void poly1305_core_setkey(struct poly1305_core_key *key, const u8 *raw_key);
This is harmless in principle, as the calling conventions are the same,
but the more specific prototype allows better type checking in the
caller.
Change the declaration to match the actual function definition.
The poly1305_simd_init() is a bit suspicious here, as it previously
had a 32-byte argument type, but looks like it needs to take the
16-byte POLY1305_BLOCK_SIZE array instead.
Fixes: 1c08a10436 ("crypto: poly1305 - add new 32 and 64-bit generic versions")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add the cpu-supply property to the a57_0 node, so Dynamic Voltage and
Frequency Scaling (DVFS) can change the CPU core voltage.
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210326105009.1574424-3-geert+renesas@glider.be
Add the cpu-supply property to the a57_0 node, so Dynamic Voltage and
Frequency Scaling (DVFS) can change the CPU core voltage.
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210326105009.1574424-2-geert+renesas@glider.be
The higher operating frequencies for the Cortex-A57 CPU cores, which
were first documented in the R-Car Gen3 Hardware User's Manual revision
0.54, apply to R-Car H3 ES2.0 (r8a77951).
Play it safe and restrict R-Car H3 ES1.x to 1.5 GHz, by removing the
"turbo-mode" entries from the operating points table inherited from
r8a77951.dtsi.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210311110552.3124180-1-geert+renesas@glider.be
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmBlnlIXHG1hdHRoaWFz
LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH5Nkw/+Mt30yAu6DNJAw6rUT61l7l1a
UEiexX5JC3Vzj8FCGueLJLRfHa/OF+Frk/VQwbGLGIo1N8cgkhn1kzQm87bGQ3rT
6avjCAUqCnoh1jmefkO65+7qFfP4f/3OiQDaBsQ59EWucQ/jPvLmsG/hVUuf1iw8
cXLdryXG/ysAYoAQyhNKMVFSL0VN2OTvz3jUEOGLT7uOIv08parG6lDKfkm3nN3F
kqXQ6tSU2efpLUo59DbJaZbjI6+HOAjWvswMvSIEyVUc7RFacJDqOdOdgtqnIHjE
t4x7Crovgx8yDic702qrfm28bDiHBeSntymuyTG2ooprre/YZgjxqipGu0p00ZCz
SFZ7s8OG9hWfDxyp1i9kh1v1nEX4YCfQGV95mXVaxPTRa/e9j/NeRiQI1IXG75S/
kzLfbHuoMtWz4JtW23Qa7NpgbqBpvV/lfEicdu1jOXJFgW3BOuJabuWvxYl5xx3v
iPNrxGmhPFMLq/3wRtpNRtcx+xulgtXKl3xIe0yxQh3azhRBiJUV2KHMEDj1mDoq
E8I23lp2rPfoU1yIvfPcqMPHHtqRQpvmvnuKjl4gegyT0znkzoy4Z9ExpWpjnbY3
o1QTrYtiIVW/yS8lh+g9hSTuRrE9VaygGgSYALeb8WPWTipH2PMlASPl/G4O9JT4
ChSB66EUEYC4BVWd1Ds=
=g3jG
-----END PGP SIGNATURE-----
Merge tag 'v5.12-next-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/defconfig
Enable option to boot MediaTek based chromebook (mt8173 and mt8183) with defconfig
* tag 'v5.12-next-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: defconfig: Enable options to support panel display for Mediatek Chromebooks
arm64: defconfig: Allow mt8173-based boards to boot from usb
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It includes a number of arm64 defconfig update for i.MX8 devices
support. The following ones might deserve some notes.
- Although Hantro decoder driver are sitting in staging, people already
find it's quite useful on i.MX8M devices.
- i.MX PCIe driver has no option for module build.
- REALTEK_PHY becomes a built-in driver, because it's used on quite some
i.MX8 reference boards where people want to boot via NFS.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmBj9KcUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM5o5wgAhADJ5eUxUD1yrgU7P8aa/WY7QjLD
XluMFtpAaI9cXAXX3cy/4JpCb9tTXMisyvG/Kr9bt+PVQOHK892U1nybdkX+VBAC
CNTfIbHYKxHE3CdkjGqIk4CA+vx+wH151bwZThWrkiBAE5Oaqcb3aVmmcFGLUvfr
MB1JAW8dsTk3+0bmYcpRtMfFxPWoSDtgGtAQANqpROJGlJ5cv/DlDTmqbgsu8Yc4
pyjBeeKkJTc9bXw2LxVHS3H7Ozew4rJ0hEdsYWwU7emYVQzu2di9kwfnMkzDZS7F
Zxifjyen4TVWqFgxUQ3dng8B3d2tQvs6ini3b1Q5fLe5lkHTPWunIuMpAQ==
=FfMm
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig
i.MX defconfig change for 5.13:
It includes a number of arm64 defconfig update for i.MX8 devices
support. The following ones might deserve some notes.
- Although Hantro decoder driver are sitting in staging, people already
find it's quite useful on i.MX8M devices.
- i.MX PCIe driver has no option for module build.
- REALTEK_PHY becomes a built-in driver, because it's used on quite some
i.MX8 reference boards where people want to boot via NFS.
* tag 'imx-defconfig-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: configs: enable FlexTimer alarm timer
arm64: configs: Select REALTEK_PHY as built-in
arm64: configs: Enable PCIe support for imx8mq boards
arm64: defconfig: Enable the Hantro decoder
arm64: defconfig: add imx8qm pinctrl support
arm64: defconfig: Enable wm8960 audio driver.
arm64: defconfig: Enable asoc simple mux
arm64: defconfig: Enable devfreq support for i.MX8MQ
Link: https://lore.kernel.org/r/20210331041019.31345-6-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a couple of device tree fixes for the v5.12 release cycle.
These are needed for proper audio support on Jetson AGX Xavier, to boot
the Jetson Xavier NX from an SD card and to be able to suspend/resume
the Jetson TX2.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmBl/4YTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoXoiD/9ZqkJo8NreyLLUXP4qLvdEMbM2mMYx
5+tevdKqGtlX3Tr9j/t50ti1JhDXf+9TsnIj8CKQaFXOvvdDQCUvybW5bEUmdxeW
AOVOXZP8R4utI/pucOU6kWX8s9uFOdm3DE4HPPQQm66jUMkTVs9ZWCHUAaCFFIZj
ZIW/U/Nwph5PNnBAztAoxzWLs3SqTiTG5isk6Zf5OFpQsSuNzZt7ovSrylZPHvYt
6la6f1QNLAdqU6OnNIoAPUitgBNOMZdAj4EIIHZ/7ALtkZaUSxgLJBcxLJUuav2w
Y2ZQUCe3NCZIu08TcQQYCe5IYzJ6kXNGwKm80XO9poGFZAxRbFOpwNdpHAuq5Cjz
HcUHcfxTrvBU9KxnYLOAee5UWqoR1OgBPmBbzZ6ZIIgboeWyI1pQRn1vjkyWJ+8g
J6GbOBa5vv94Rc4cLBwrU0Wkawoy0G4VrT3t6UjVeJ7BIEEDWwipcDuIEGFxtvTE
e5MoMb5nODjGssiGxIlD5WdRUakSGYOYK2CVhTa9PNKt1wyu3mX+czSfLUlIeY5r
bYUGk4+ujvDXjxNneD5dUOU++laL5I/9AytLopBtD5u47FCKNeXJLYHGI2Jg5EZD
MVgPd99B3gkSI7johWeBniGv6jPRV0l5yx4RLFuk+ucpNC6VCmDtOVdT6SKh95t5
BJmIdqK8MJoo6A==
=4Hys
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.13-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree fixes for v5.12-rc6
This contains a couple of device tree fixes for the v5.12 release cycle.
These are needed for proper audio support on Jetson AGX Xavier, to boot
the Jetson Xavier NX from an SD card and to be able to suspend/resume
the Jetson TX2.
* tag 'tegra-for-5.13-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Move clocks from RT5658 endpoint to device node
arm64: tegra: Fix mmc0 alias for Jetson Xavier NX
arm64: tegra: Set fw_devlink=on for Jetson TX2
arm64: tegra: Add unit-address for ACONNECT on Tegra186
Link: https://lore.kernel.org/r/20210401172622.3352990-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Couple of changes to describe PCI dma-ranges correctly which was
previously removed and to enable the PCIe and DMA SMMU.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmBkOxgACgkQAEG6vDF+
4piaHRAAvBh7VGV/Mzms090+3BCgL7Xgk2GL6hIpROtBETkVmxcFje6FhBtAGQQr
H/fK6IrFFwc0nurOexl+eLuQcL2eQygTwOBa5oJ2oWm5dSxNvpY+3nl/lQqFyYxK
gIUqIfeYKh46aNXlTQupGGCcB6jpgKKXmPWMzdDUj8D3AurVw6K1Y277r2LacGQC
HHC1lMUEBb9aAVbeZLqCdOLj0SGZs51/M8p/viS3aecOivbbt+VxKiUlj5HVRY+T
K97jlKJqjxoZOvqkX6ocCemiQ4VY9DILYwmRoX9H2mepKfmZAde/hd26sDj4bCVd
FWuG8+62ZbGy5zfvcQC1IQcp7DD2F/y7c0yULsbMF5qC64WDiOL3jcKAMvzQz/tT
RneKzkou+Xjjxrb+WBb7PyDI1/rEAeTqsz5aWVIoTP3lUbeaY4ilWMvT+64YO0Fw
ol/ExrqxRAqcvN0wp+sqCLKpeA2j67Ez3s2JdzZn5YMNl2To98GsZMeW9jIUUKWC
6GBfhicCkKnsHgdphOnl833RcCpQBaIg2V1lp+28TxOOibWWBCiAvHc74EkYI8Pj
LbkTdoIYD13uat9XzwZv/JRWomqlbZ38HtsFMi/43o7tIap3YBtUFEWl05xS6CCn
F2GYKim20ss6XX3B6ARVMpxT3ZlINV/pAYRPiaecbG09/9HhQyA=
=b/Gg
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno updates for v5.13
Couple of changes to describe PCI dma-ranges correctly which was
previously removed and to enable the PCIe and DMA SMMU.
* tag 'juno-updates-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Enable more SMMUs
arm64: dts: juno: Describe PCI dma-ranges
Link: https://lore.kernel.org/r/20210331100410.cenuhvpqoumvsk52@bogus
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A series from Dong Aisheng to update i.MX8Q device trees for adopting
SS (SubSystems) based bindings.
- New board support: Kontron pitx-imx8m, Engicam i.Core MX8M Mini.
- A series from Adrien Grassein to add various peripheral support for
imx8mm-nitrogen-r2 board.
- A series from Guido Günther to update librem5-devkit device tree.
- A number of patches from Michael Walle to add Root Complex Event
Collector interrupt, update MTD partitions and add rtc0 alias for
ls1028a-kontron-sl28 board.
- Add EQOS MAC support for phyBOARD-Pollux-i.MX8MP.
- Add 2x2 SFP+ cage support for clearfog-itx boards.
- Small and random update for various boards.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmBj8eYUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7Lygf9EHqZZOU7WA0nmmsBM9qJcEmY32aY
XV+9MAqnCDKGoSWtbsApJBft3/SnzRVa+cUiLfUKt3iGaTGpB6xWnHQjnmmJr4zU
aXbrjnR9C4z+xo2P6DvreVs2t6lIj/OI8S2M3nolROfHFQ05/c25+fcWnE4sbnNQ
4y8PQJ4hWaBkerMZEnFZLY4MDAJbJduQP2rnQ3vW4P1K2Be/4iw9luYEMUnZZ7K6
jVLOa7eaPiWZGi7TnxPm+GYHnoGVoFI4dKMkv1rdfpgSGn77yIXquyYPgCuHvgv2
XuroZCKex2mpE/JIsr+hdGHIAjp/nS+OTbR5tlQtpUFuBb77ZPG8yERIxQ==
=2phP
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree update for 5.13:
- A series from Dong Aisheng to update i.MX8Q device trees for adopting
SS (SubSystems) based bindings.
- New board support: Kontron pitx-imx8m, Engicam i.Core MX8M Mini.
- A series from Adrien Grassein to add various peripheral support for
imx8mm-nitrogen-r2 board.
- A series from Guido Günther to update librem5-devkit device tree.
- A number of patches from Michael Walle to add Root Complex Event
Collector interrupt, update MTD partitions and add rtc0 alias for
ls1028a-kontron-sl28 board.
- Add EQOS MAC support for phyBOARD-Pollux-i.MX8MP.
- Add 2x2 SFP+ cage support for clearfog-itx boards.
- Small and random update for various boards.
* tag 'imx-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (55 commits)
arm64: dts: fsl-ls1028a-kontron-sl28: add rtc0 alias
arm64: dts: ls1028a: move rtc alias to individual boards
arm64: dts: fsl-ls1028a-kontron-sl28: combine unused partitions
arm64: dts: fsl-ls1028a-kontron-sl28: move MTD partitions
arm64: dts: imx8mp-evk: Improve the Ethernet PHY description
arm64: dts: imx8mq-librem5-r3: Mark buck3 as always on
arm64: dts: imx8mq-librem5: Hog the correct gpio
arm64: dts: lx2160a-clearfog-itx: add SFP support
arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART
arm64: dts: imx8mn: Reorder flexspi clock-names entry
arm64: dts: imx8mm: Reorder flexspi clock-names entry
arm64: dts: ls1028a: set up the real link speed for ENETC port 2
arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support
arm64: dts: imx: add imx8qm mek support
arm64: dts: imx: add imx8qm common dts file
arm64: dts: imx8qm: add dma ss support
arm64: dts: imx8: split adma ss into dma and audio ss
arm64: dts: imx8qm: add conn ss support
arm64: dts: imx8qm: add lsio ss support
arm64: dts: imx8: switch to new lpcg clock binding
...
Link: https://lore.kernel.org/r/20210331041019.31345-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.13, please pull the following:
- Rafal continues to add support for the 4908 SoCs and describes the USB
PHY, firmware flash partitions and Ethernet switch and Ethernet
controller. He also adds support for the TP-Link Archer C2300 V1
router and upates the Netgear R8000P and Asus GT-AC5300 routers network
ports description.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmBiINoACgkQh9CWnEQH
BwToUA//WssP2pUzjsNev3kdTiOix/Vs/bkKJ9VlGRkmKLsYQJKtIjM1h7GrxrBS
d4cUIjgt0sBicLnH/+vXWWzWnle51ZnVVjjPxywxT2SEqp/69elOqH/CnELQF6dD
9nvZgH5VnWi+hgE/yBgfkY5uHjzUnXp8unWkWagHncgaEndPJy7DdHRru50fy0CN
bqHbJzHmeJfv/TVdfCAdOFTv1MGi9lcmhIlMerPtxoaf1aX2QZJ99Wc4BoTEfmK6
DP+LLsefewuWeDm/SafZdK3pLg3QyUzMrtrNa7KLNUzNhH69gtUWfjY1tpJn+vUF
azD85U+cP70I1+DdVrZ+grUW2JgE1DmMdj/VtUOR80mjrEZDn7fbMldR6X049fjr
CNanRMlDuCFe3YZbqqblrfVgQB/iEgI6YHoYZJSbzJNccM6dYv1Txv0jJUtUMgAs
TZ7QUFZEJ6BPL6JYb/fIxLvp0gUUihO6qESzxtUFiBnxDB57hL9lZshcsOlRoKTa
eAOwNd0F8VCrIc89po3dDTZsr94qtmHpHzttbm7Hr2xwsF3hCsCODn3J9GSdk7OP
lI004I0cr6vYwJI+CYgEEf4wfDXCE7JvWIB0uvk307gUbnxR/wlI1YWV/+uVDAHu
TRgE7clsR6ZtWxQIMulTSmitm9M5EtZ81E0a1iAnO5wUKmfMDtg=
=MdDK
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.13/devicetre-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 5.13, please pull the following:
- Rafal continues to add support for the 4908 SoCs and describes the USB
PHY, firmware flash partitions and Ethernet switch and Ethernet
controller. He also adds support for the TP-Link Archer C2300 V1
router and upates the Netgear R8000P and Asus GT-AC5300 routers network
ports description.
* tag 'arm-soc/for-5.13/devicetre-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: bcm4908: add Ethernet MAC addr
arm64: dts: broadcom: bcm4908: add Ethernet TX irq
arm64: dts: broadcom: bcm4908: set Asus GT-AC5300 port 7 PHY mode
arm64: dts: broadcom: bcm4908: add TP-Link Archer C2300 V1
dt-bindings: arm: bcm: document TP-Link Archer C2300 binding
arm64: dts: broadcom: bcm4908: fix switch parent node name
arm64: dts: broadcom: bcm4908: describe firmware partitions
arm64: dts: broadcom: bcm4908: add remaining Netgear R8000P LEDs
arm64: dts: broadcom: bcm4908: describe Netgear R8000P switch
arm64: dts: broadcom: bcm4908: describe Ethernet controller
arm64: dts: broadcom: bcm4908: describe USB PHY
Link: https://lore.kernel.org/r/20210330184006.1451315-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Patches from Krzysztof Kozlowski that fixes dtc warnings
and dtbs_check warnings
- Adjust the "cnds,read-delay" value for the Agilex devkit to 2
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAmBjA3gUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPTqrA//QwfKTzUN/ni1ztXIvkaz9vP7MXfy
XsK+7H/kWTL4/hsgoa6SdNi1bRL+flrltqKRkfRFmIBSL1datWT+QAbiyYJ1Jyra
k5jxlYQKJLKp3gobirw6Pgq0usWgWC3v4efnvlj4SWFM8uI8T3XJ4cEdrw4IMGEU
i99pGu1JAj7Mqnef4S2dlzbF68vdeUTzOJlq66mTu12s+d4ncSeY3RGhSTqXswso
4bqop4G5Kv/siHTRYiR3EEm2eHiJmTBBUxmmhIBLROY5mgp8XBtX9mmYg6/pSzI/
VHsdy+mIgCAnYRQueS2OZ7/Q3DROdUhVUxie6XLFlG0hoB6yudGiAxhF7lsIAhET
oexBqX/uWl/ah2x4LirWRz89sYMDi2pR1YTQeOePlqE6amYkgf43JkZ0joAcIhpc
SR+sGhA0a33Q1AcKGgImhIWRqYn+wWD09WAzcuKpH5vmv4Jmroigm4BKwlahhv6x
oYBZZqGc8aSSowXDY3A8meT5/fP/TEbf5HiX5U7Fl220rTljCFPFHELuXooOW8Z4
zr1XRKQxBx7t4HPlvr+t4BWETI6ga90p5sUgTHMlQF0tmbHIqyz1UmJnOMvJalH4
l3w/k7lrZJ75mlpsqOqibGZjf7bRwjzS4Uh+8roc1hocDkoG+iS7qlMaUwFmw7AU
JuFJD7beI1LYZT8=
=JYZq
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_update_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.13
- Patches from Krzysztof Kozlowski that fixes dtc warnings
and dtbs_check warnings
- Adjust the "cnds,read-delay" value for the Agilex devkit to 2
* tag 'socfpga_dts_update_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: intel: adjust qpsi read-delay property
arm64: dts: intel: socfpga_agilex_socdk_nand: align LED node names with dtschema
arm64: dts: intel: socfpga_agilex: align node names with dtschema
arm64: dts: intel: socfpga_agilex: use defined for GIC interrupts
arm64: dts: intel: socfpga_agilex: move usbphy out of soc node
arm64: dts: intel: socfpga_agilex: remove default status=okay
arm64: dts: intel: socfpga_agilex: move timer out of soc node
arm64: dts: intel: socfpga_agilex: move clocks out of soc node
arm64: dts: intel: socfpga: override clocks by label
Link: https://lore.kernel.org/r/20210330110430.558182-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The initialization of value in function armv8pmu_read_hw_counter()
and armv8pmu_read_counter() seem redundant, as they are soon updated.
So, We can remove them.
Signed-off-by: Qi Liu <liuqi115@huawei.com>
Link: https://lore.kernel.org/r/1617275801-1980-1-git-send-email-liuqi115@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210326130034.15231-4-p.yadav@ti.com
The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210326130034.15231-3-p.yadav@ti.com
The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210326130034.15231-2-p.yadav@ti.com
- Fix a system failure on imx6qdl-phytec-pfla02 board when booting from
SD, by adding missing vmmc supply for SD interfaces.
- Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2 definition.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmBi5tIUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM63qQf9H+AmuNEw3Sm9+kW+VH3u+7cBGY0r
gkdV+hc+pabC/lzkvGTJhmncW2Y35BfzuEG6Bd6s6QEEPAqtqZ0fzDZlcS444b9Z
e2hLPraKo/C51SCOoAmCUd5JA3to/ZVC+zg1ZiN92SrqgBm5e3we7xvp+Qa/Rzxs
ZYmzll20U4gt9Dq2HX7dSLc8F/yq6EIGEMkXPKkkDUdWXxM4qbUpN0LlzWCV529f
SNppkfeA1VfB9Kb8MrawvBRldN4j3T0SWhRFZfa6LqzJEP1dy+885u+4YknMdeJc
ibpab/oEAzz/yiOiTBmtNCUBFEh3Xdiwh+0Y4T5nGhRd2kFWi2TBJB7hFg==
=8P0W
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.12, round 2:
- Fix a system failure on imx6qdl-phytec-pfla02 board when booting from
SD, by adding missing vmmc supply for SD interfaces.
- Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2 definition.
* tag 'imx-fixes-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6: pbab01: Set vmmc supply for both SD interfaces
arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
Link: https://lore.kernel.org/r/20210330090236.GQ22955@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The MT8183 Pumpkin board is manufactured by OLogic and includes
a MediaTek MT8183 SoC with 2GB of RAM.
The board provides the following IOs:
* 2 USB Type-A ports
* Ethernet
* Serial UART over micro-USB port
* 1 USB Type-C dual role port
* 1 USB Type-C power only port
* 1 Jack for audio
* RPI compatible header
* MT7668 wiresless chip with Wi-Fi AC and BT 5
* Micro-HDMI port
* 2 connectors for CSI cameras
* 1 connector for DSI display
* 1 JTAG port
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210217205945.830006-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
To aid with debugging, add details of the source of a panic from nVHE
hyp. This is done by having nVHE hyp exit to nvhe_hyp_panic_handler()
rather than directly to panic(). The handler will then add the extra
details for debugging before panicking the kernel.
If the panic was due to a BUG(), look up the metadata to log the file
and line, if available, otherwise log an address that can be looked up
in vmlinux. The hyp offset is also logged to allow other hyp VAs to be
converted, similar to how the kernel offset is logged during a panic.
__hyp_panic_string is now inlined since it no longer needs to be
referenced as a symbol and the message is free to diverge between VHE
and nVHE.
The following is an example of the logs generated by a BUG in nVHE hyp.
[ 46.754840] kvm [307]: nVHE hyp BUG at: arch/arm64/kvm/hyp/nvhe/switch.c:242!
[ 46.755357] kvm [307]: Hyp Offset: 0xfffea6c58e1e0000
[ 46.755824] Kernel panic - not syncing: HYP panic:
[ 46.755824] PS:400003c9 PC:0000d93a82c705ac ESR:f2000800
[ 46.755824] FAR:0000000080080000 HPFAR:0000000000800800 PAR:0000000000000000
[ 46.755824] VCPU:0000d93a880d0000
[ 46.756960] CPU: 3 PID: 307 Comm: kvm-vcpu-0 Not tainted 5.12.0-rc3-00005-gc572b99cf65b-dirty #133
[ 46.757459] Hardware name: QEMU QEMU Virtual Machine, BIOS 0.0.0 02/06/2015
[ 46.758366] Call trace:
[ 46.758601] dump_backtrace+0x0/0x1b0
[ 46.758856] show_stack+0x18/0x70
[ 46.759057] dump_stack+0xd0/0x12c
[ 46.759236] panic+0x16c/0x334
[ 46.759426] arm64_kernel_unmapped_at_el0+0x0/0x30
[ 46.759661] kvm_arch_vcpu_ioctl_run+0x134/0x750
[ 46.759936] kvm_vcpu_ioctl+0x2f0/0x970
[ 46.760156] __arm64_sys_ioctl+0xa8/0xec
[ 46.760379] el0_svc_common.constprop.0+0x60/0x120
[ 46.760627] do_el0_svc+0x24/0x90
[ 46.760766] el0_svc+0x2c/0x54
[ 46.760915] el0_sync_handler+0x1a4/0x1b0
[ 46.761146] el0_sync+0x170/0x180
[ 46.761889] SMP: stopping secondary CPUs
[ 46.762786] Kernel Offset: 0x3e1cd2820000 from 0xffff800010000000
[ 46.763142] PHYS_OFFSET: 0xffffa9f680000000
[ 46.763359] CPU features: 0x00240022,61806008
[ 46.763651] Memory Limit: none
[ 46.813867] ---[ end Kernel panic - not syncing: HYP panic:
[ 46.813867] PS:400003c9 PC:0000d93a82c705ac ESR:f2000800
[ 46.813867] FAR:0000000080080000 HPFAR:0000000000800800 PAR:0000000000000000
[ 46.813867] VCPU:0000d93a880d0000 ]---
Signed-off-by: Andrew Scull <ascull@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210318143311.839894-6-ascull@google.com
hyp_panic() reports the address of the panic by using ELR_EL2, but this
isn't a useful address when hyp_panic() is called directly. Replace such
direct calls with BUG() and BUG_ON() which use BRK to trigger an
exception that then goes to hyp_panic() with the correct address. Also
remove the hyp_panic() declaration from the header file to avoid
accidental misuse.
Signed-off-by: Andrew Scull <ascull@google.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210318143311.839894-5-ascull@google.com
Recently introduced async probe on mmc devices can shuffle block IDs.
Pin them to fixed values to ease booting in environments where UUIDs
are not practical. Use newly introduced aliases for mmcblk devices from [1].
[1]
https://patchwork.kernel.org/patch/11747669/
Commit message taken from commit 0011c6d182 ("arm64: dts: rockchip: Assign a fixed index to mmc devices on rk3399 boards.")
The unconventional order (B, C, A) is due to the fact that sd_emmc_a is
(according to the comments) only used for SDIO.
AFAICS all boards either have both sd_emmc_b and sd_emmc_c or only one of
them enabled. So the alias order should match the previous non-async order
for all of them.
Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210203192824.854491-1-alexander.stein@mailbox.org
