Commit Graph

2727 Commits

Author SHA1 Message Date
Monk Liu
bc1e59b24d drm/amdgpu:insert switch buffer only for VM submit
for non-VM submit which is from kernel side, no need
to switch buffer at all.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:38 -05:00
Monk Liu
79bbbf8bfe drm/amdgpu:Preamble is forbid to be ignored in SRIOV
SR-IOV requires the preamble.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:37 -05:00
Monk Liu
714fbf8039 drm/amdgpu:set cond_exec polling value to 1 in ring_init
no need to set it per ib_schedule(), hw won't override
this polling address.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:37 -05:00
Monk Liu
c2ce92fc79 drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)
to support SRIOV preemption.

v2:
fix emit_frame_size

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:36 -05:00
Monk Liu
7e6bf80f73 drm/amdgpu:introduce new flag to identify VM domain for cntx_ctrl
To determine whether the context uses GPUVM or not.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:35 -05:00
Monk Liu
acad2b2a7b drm/amdgpu:implement CE/DE meta-init routines
those package need to insert into ring buffer for
SRIOV case. they are used to let CP do preemption.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:35 -05:00
Monk Liu
0a8e147369 drm/amdgpu:implement ring_write_multiple
Write multiple dwords to the ring.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:34 -05:00
Monk Liu
ae65a26dd3 drm/amdgpu:add META_DATA struct for CSA/SRIOV v2
META-DATA is used in GFX cmd submit, we have two
format suit for META-DATA-init, one is legacy and another
is for chained-ib preempt, which is used in vulkan
UMD.

v2: drop use CP version number to judge if chain-ib
supports or not, we wait for it mature

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:33 -05:00
Rex Zhu
a1970a6382 drm/amdgpu: refine ci uvd dpm code.
Fix up the powergating logic.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Ack-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:33 -05:00
Nils Wallménius
50261151a1 drm/amdgpu: simplify allocation of scratch regs
The scratch regs are sequential so there's no need to keep
them in an array, we can just return the index of the first
free register + the base register. Also change the array
of bools for keeping track of the free regs to a bitfield.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:32 -05:00
Andrey Grodzovsky
cb341a319f drm/amdgpu: Refactor flip into prepare submit and submit. (v3)
Make pflip atomic friendly. Split the fuinction into
whatever can fail part and the actual flip submit part.
Call the pre-submit function before atomic states
are swapped so in case of error we can fail the
IOCTL.

v2:
Update due to  target_vblank code change.
Fix identetation.
Change return type for amdgpu_crtc_submit_flip to void
v3: agd: fix formatting

Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:31 -05:00
Andrey Grodzovsky
3caf861e98 drm/amdgpu: Switch error code when bo pin fails. (v3)
Switching to -ENOMEM resolves a hang in case the driver
uses this function in atomic code path.

v2: Update commit message.
v3:
Remove forcing -EINVAL in case of amdgpu_bo_pin fail
since there is no apparent reason for not just passing
through the the return value.

Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:31 -05:00
Julia Lawall
f10b478d9e drm/amdgpu/gfx8: fix bugon.cocci warnings
Use BUG_ON instead of a if condition followed by BUG.

Generated by: scripts/coccinelle/misc/bugon.cocci

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewd-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
CC: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:30 -05:00
Alex Deucher
034041f334 drm/amdgpu: use the num_rings variable for checking vce rings
Difference families may have different numbers of rings. Use
the variable rather than a hardcoded number.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:29 -05:00
Nicolai Hähnle
f1543f58cb drm/amd/amdgpu: fix locking in bo creation error path
Unlock the resv lock only if we were the ones to lock it in the first
place.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:29 -05:00
Nicolai Hähnle
36ea83d151 drm/amd/amdgpu: lock reservation object while creating shadow bo
ttm_bo_init checks that the reservation object is locked. This is
the caller's responsibility when resv != NULL. Otherwise, the inline
reservation object of the newly allocated buffer is used and must
explicitly be locked.

Uninterruptible w/w locks without an acquire context are always
successful.

v2: use ww_mutex_lock

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> (v1)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:28 -05:00
Huang Rui
54170226a6 drm/amdgpu: fix typo of CGTS
Fixes: 9e8590861e9 ('drm/amdgpu: add parse clock gating state')
Reported-by: Tom StDenis <Tom.StDenis@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:27 -05:00
Xiangliang Yu
fb140b293b drm/amdgpu: do not reset gpu for virtualization
Current amdgpu reset process only works on bare-metal and for
SRIOV many inside it need re-work to adapt to vf device.

This is a temporary workaround to skip gpu reset.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:27 -05:00
Xiangliang Yu
06465d8ec9 drm/amdgpu/virt: enable virtual display
Virtual display is default setting for virtualization, enable it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:26 -05:00
Xiangliang Yu
99581cc573 drm/amdgpu/vi: add support virtualization
Call VI virtualization functions if device is Vf.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:25 -05:00
Xiangliang Yu
3149d9da12 drm/amdgpu: request/release full gpu access if device is vf
For gpu vf device, first need to request full gpu access before
accessing gpu registers, and release full gpu access after the
access is done.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:25 -05:00
Xiangliang Yu
ab71ac56f6 drm/amdgpu/virt: implement VI virt operation interfaces
VI has asic specific virt support, which including mailbox and
golden registers init.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: shaoyunl <Shaoyun.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:24 -05:00
Xiangliang Yu
1e9f139279 drm/amdgpu/virt: add high level interfaces for virt
Add high level interfaces that is not relate to specific asic. So
asic files just need to implement the interfaces to support
virtualization.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:23 -05:00
Xiangliang Yu
bc992ba5a3 drm/amdgpu/virt: use kiq to access registers (v2)
For virtualization, it is must for driver to use KIQ to access
registers when it is out of GPU full access mode.

v2: agd: rebase

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:23 -05:00
Xiangliang Yu
5ec9f06e10 drm/amdgpu/virt: add runtime flag
Add new flag to define gpu runtime that is out of full gpu access.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:22 -05:00
Xiangliang Yu
880e87e380 drm/amdgpu/gfx8: implement emit_rreg/wreg function
Implement emit_rreg/wreg function for kiq ring.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:21 -05:00
Xiangliang Yu
b6091c1217 drm/amdgpu/ring: add two interfaces to support r/w registers with kiq
During virtual runtime, need to send command to kiq ring to
read/write GPU registers. Add two interface to support the two
actions.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Linu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:21 -05:00
Monk Liu
2493664f05 drm/amdgpu:invoke CSA functions (v2)
Make sure the CSA is mapped.

v2: agd: rebase.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:20 -05:00
Monk Liu
4e4bbe7343 drm/amdgpu:add new file for SRIOV
for SRIOV usage, CSA is only used per device and each
VM will map on it.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:19 -05:00
Monk Liu
bd7de27d81 drm/amdgpu:new field members for SRIOV
and implement CSA functions in this file

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:19 -05:00
Nicolai Hähnle
3e19e69ab0 drm/amd/amdgpu: add check that shadow page tables are GPU-accessible
Skip amdgpu_gem_va_update_vm otherwise. Also clean up the check for the
non-shadow page tables using the new helper function.

This fixes a crash with the stack trace:

amdgpu_gem_va_update_vm
-> amdgpu_vm_update_page_directory
 -> amdgpu_ttm_bind
  -> amdgpu_gtt_mgr_alloc

v2: actually check bo->shadow instead of just checking bo twice

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:18 -05:00
Nicolai Hähnle
d1144b84fc drm/amd/amdgpu: add check that shadow page directory is GPU-accessible
Skip amdgpu_gem_va_update_vm when shadow the page directory is swapped out.
Clean up the check for non-shadow BOs as well using the new helper function.

This fixes a crash with the stack trace:

amdgpu_gem_va_update_vm
-> amdgpu_vm_update_page_directory
 -> amdgpu_ttm_bind
  -> amdgpu_gtt_mgr_alloc

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:17 -05:00
Nicolai Hähnle
b99f31030a drm/amd/amdgpu: add amdgpu_bo_gpu_accessible helper function
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:17 -05:00
Nicolai Hähnle
661a7606c9 drm/amd/amdgpu: move eviction counting to amdgpu_bo_move_notify
This catches evictions of shadow page tables from the GART. Since shadow
page tables are always stored in system memory, amdgpu_bo_move is never
called for them.

This fixes a crash during command submission that occurs when only a shadow
page table and no other BOs were evicted since the last submission.

Fixes: 1baa439fb2 ("drm/amdgpu: allocate shadow for pd/pt bo V2")
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:16 -05:00
Nicolai Hähnle
66257db7a5 drm/ttm: add evict parameter to ttm_bo_driver::move_notify
Ensure that the driver can listen to evictions even when they don't take the
path through ttm_bo_driver::move.

This is crucial for amdgpu, which relies on an eviction counter to skip
re-binding page tables when possible.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:15 -05:00
Rex Zhu
714b1f5371 drm/amdgpu: refine vce3.0 initialize.
1. disable vce cg when vce hw initialize.
2. initizlize vce clock to 10KHz fo dgpu,
   so no need to set bypass clock to vce.

Change-Id: I934c2c4820cc95c1bfa2fa41ff0f40a0d3cd1c40
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:15 -05:00
Rex Zhu
570272d229 drm/amdgpu: extend profiling mode.
in profiling mode, powerplay will fix power state
as stable as possible.and disable gfx cg and LBPW feature.

profile_standard: as a prerequisite, ensure power and thermal
sustainable, set clocks ratio as close to the highest clock
ratio as possible.
profile_min_sclk: fix mclk as profile_normal, set lowest sclk
profile_min_mclk: fix sclk as profile_normal, set lowest mclk
profile_peak: set highest sclk and mclk, power and thermal not
sustainable
profile_exit: exit profile mode. enable gfx cg/lbpw feature.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:14 -05:00
Rex Zhu
7f61bed0c4 drm/amd/powerplay: refine DIDT feature in Powerplay.
Updating SQ DIDT settings and block mask
so SQ uses PCC on Polaris11.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:13 -05:00
Rex Zhu
7ef600e808 drm/amd/powerplay: add new smu message.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:13 -05:00
Rex Zhu
e31e8a226a drm/amd/powerplay: Configuring DIDT blocks only SQ enabled on Polaris11.
following firmware's request.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:12 -05:00
Rex Zhu
8e7afd34fd drm/amdgpu: fix bug return invalid value to sysfs.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:11 -05:00
Huang Rui
c79b55618a drm/amdgpu: add get clockgating_state method for vce v3
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:11 -05:00
Huang Rui
c8781f56c8 drm/amdgpu: add get clockgating_state method for uvd v5&v6
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:10 -05:00
Huang Rui
abd2c2fe12 drm/amdgpu: add get clockgating_state method for vi common
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:09 -05:00
Huang Rui
41c360f6a6 drm/amdgpu: add get clockgating_state method for sdma v3
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:09 -05:00
Huang Rui
8bcab092f8 drm/amdgpu: add get clockgating_state method for gmc v8
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:08 -05:00
Huang Rui
ebd843d6ee drm/amdgpu: add get clockgating_state method for gfx v8
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:07 -05:00
Huang Rui
a8503b15ab drm/amdgpu: add parse clock gating state
Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: William Lewis <minutemaidpark@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:07 -05:00
Huang Rui
6cb2d4e4f3 drm/amdgpu: introduce an interface to get clock gating status dynamically
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:06 -05:00
Xiangliang Yu
c8394f38fa drm/amdgpu: remove detect_hw_virtualization interface
Call detection function driectly, so remove the interface.

V2: ci and si also need to call the detect function.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:05 -05:00
Xiangliang Yu
91caa08137 drm/amdgpu/vi: move virtualization detection forward
Move the detection forward into vi_set_ip_blocks function, then
add ip blocks virtualization need if device is VF.

V2: add ip blocks according to asic type.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:05 -05:00
Xiangliang Yu
5a5099cbf4 drm/amdgpu/virt: rename fieldes of virtualization structure
Use acronym to rename fields to make easy to spell out.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:04 -05:00
Xiangliang Yu
4e638ae9c1 drm/amdgpu/gfx8: add support kernel interface queue(KIQ)
KIQ is queue-memory based initialization method: setup KIQ queue
firstly, then send command to KIQ to setup other queues, without
accessing registers.

For virtualization, need KIQ to access virtual function registers
when running on guest mode.

V2: use amdgpu_bo_create/free_kernel to allocate BO.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:03 -05:00
Amber Lin
b64a18c502 drm/amdgpu: PCI I/O bar can be disabled
PCI I/O bar can be disabled in VBIOS to save the resource. It is often
disabled in large aperture VBIOS. Don't call it an error.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:03 -05:00
Rex Zhu
a5b580e119 drm/amd/powerplay: change function name to make code more readable
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:02 -05:00
Rex Zhu
63b55943b3 drm/amd/powerplay: refine smumgr code
1. delete asic_smum_init functions, export asic private functions
   to smumgr directly, make code more readable.
2. create asic private data in asic_init_func.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:01 -05:00
Rex Zhu
a0aa70463e drm/amd/powerplay: fix memory leak in smu7_hwmgr
add pp_smu7_thermal_fini function to free related
data when smu7_hwmgr_fini.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:01 -05:00
Rex Zhu
cd576e63d2 drm/amd/powerplay: fix memory leak in cz_hwmgr.c
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:13:00 -05:00
Rex Zhu
4c283acf69 drm/amd/powerplay: not free hwmgr/smumgr in asic private functions.
struct smumgr/hwmgr will be freed on amd_powerplay_destory

and if we free them in one of asic private functions, other private
date may not be freed. for example: power state and power table
in hwmgr.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:59 -05:00
Rex Zhu
6f4dc24a88 drm/amd/powerplay: not use module parameter in powerplay.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:59 -05:00
Rex Zhu
1c86380248 drm/amd/powerplay: refine powerplay interface.
v2: add pp_check function to check pp_instance
   valid.

1. powerplay export two new interface to amdgpu,
   amd_powerplay_create/amd_powerplay_destroy.
2. create pp_instance/smumgr/hwmgr/eventmgr in
   early init, destroy them when lata_fini.
3. in sw_init, create and init asic private smumgr
   data, and free them when sw_fini.
4. in hw_init, create and init asic private hwmgr
   data, and free them when hw_fini.
5. export powerplay state: PP_DPM_DISABLED.
   when user disabled powerplay or hwmgr/eventmgr
   init failed, powerplay return this state to amdgpu.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:58 -05:00
Rex Zhu
ae6a58e409 drm/amdgpu: use same enter/exit safe mode for gfx_8.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:57 -05:00
Rex Zhu
3bd5897964 drm/amd/powerplay: add profiling mode in dpm level
In some case, App need to run under max stable clock.
so export profiling mode: GFX CG was disabled.
and user can select the max stable clock of the device.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:57 -05:00
Rex Zhu
9d273495e6 drm/amdgpu: delete dead definitions of dpm_ip_funcs
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:56 -05:00
Rex Zhu
b9bc58140e drm/amdgpu: delete dead module parameter:amdgpu_powerplay.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:55 -05:00
Rex Zhu
23c8ea921d drm/amd/powerplay: fix issue can't load another smu firmware.
need to release failed smu firmware before load another
firmware.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:55 -05:00
Rex Zhu
bcb5487bce drm/amd/powerplay: refine code in cz_smumgr.c
cz_smu_init will be called in sw_init.
so it should not touch other blocks's
firmware as they were not ready.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:54 -05:00
Rex Zhu
0d12570aaf drm/amd/powerplay: fix bug dpm level unexpectly be reset to auto.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:53 -05:00
Rex Zhu
e5d03ac2b8 drm/amd/powerplay: Unify dpm level defines
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:53 -05:00
Rex Zhu
db7da7aa3a drm/amd/powerplay: delete dpm code for Cz/St.
The powerplay implementation has been the default for a
while now.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:52 -05:00
Huang Rui
634a24d8af drm/amd/powerplay: update all printk to pr_* on smumgr
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:51 -05:00
Huang Rui
b5c11b8e37 drm/amd/powerplay: update all printk to pr_* on hwmgr
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:50 -05:00
Huang Rui
19946cfd37 drm/amd/powerplay: update all printk to pr_* on eventmgr
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:50 -05:00
Huang Rui
0fb829def6 drm/amd/powerplay: refine print message for amd_powerplay
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:49 -05:00
Huang Rui
7bd55429fd drm/amd/powerplay: reshuffle headers to make pr_fmt macro before <linux/xxx.h>
This patch reshuffles headers to define pr_fmt before <linux/xxx.h>.
It can avoid pr_fmt redefine warnning from linux/xxx.h like below:

CC [M]  /home/ray/gpu/BUILD/x86_64/linux/drivers/gpu/drm/amd/amdgpu//../powerplay/amd_powerplay.o
/home/ray/gpu/BUILD/x86_64/linux/drivers/gpu/drm/amd/amdgpu//../powerplay/amd_powerplay.c:24:0: warning: "pr_fmt" redefined
 #define pr_fmt(fmt) "[powerplay] " fmt
 ^
In file included from include/linux/kernel.h:13:0,
                 from include/linux/list.h:8,
                 from include/linux/agp_backend.h:33,

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:48 -05:00
Huang Rui
7739b1e7e1 drm/amd/powerplay: add prefix for all powerplay pr_* prints
Powerplay will use them instead of raw printk, and we can dynamic
change the debug level with it.

The prefix is like below:

[  xxx.xxxxxx] amdgpu: [powerplay] ...

Suggested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Cc: Arindam Nath <Arindam.Nath@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:48 -05:00
Rex Zhu
5c96422100 drm/amdgpu: refine gfx_v8 pg code.
move en/disable GFX CP/SMU_HS PG to
function gfx_v8_0_set_powergating_state

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:47 -05:00
Rex Zhu
f6f534e2af drm/amdgpu: add drm light sleep support for Vi
v2: fix copy error.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:46 -05:00
Rex Zhu
e8a95b274d drm/amdgpu: add cgs interface for enter/exit rlc safe mode.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:46 -05:00
Ken Xue
919db4c199 drm/amdgpu: Refine the way to get atom bios
There are several ways to check out a ATOMBIOS. In previous codes, try
a new way to fetch out vbios/rom, until current vbios/rom is started with
0x55aa, then check if this vbios is ATOMBIOS. Now, try a new way to fetch
out vbios until all flags of ATOMBIOS are verified.

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:45 -05:00
Harry Wentland
33503e9e5a drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines
This is required for DP HBR2 test pattern

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:44 -05:00
Harry Wentland
8c27f5c1fd drm/amd/amdgpu: Add HDMI_DATA_SCRAMBLE register definition
This is required by HDMI 2.0

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:43 -05:00
Huang Rui
9e4bd4ca62 drm/amdgpu: cleanup useless extern functions
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:43 -05:00
Huang Rui
35af17b0e5 drm/amdgpu: cleanup useless smu_ucode_xfer_vi.h
This header won't be used at amdgpu, it moved to powerplay.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:42 -05:00
Huang Rui
5c1104b9dc drm/amd/powerplay: fix request smc_sk firmware case
This patch fixes firmware request error on polaris protection mode.
Because we need load smc_sk instead of smc under security protection
mode.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Tested-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:41 -05:00
Huang Rui
e81f749452 drm/amd/powerplay: add request_firmware/release_firmware for smu7
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:41 -05:00
Kees Cook
613e61a025 drm/amdgpu: use designated initializers
Prepare to mark sensitive kernel structures for randomization by making
sure they're using designated initializers. These were identified during
allyesconfig builds of x86, arm, and arm64, with most initializer fixes
extracted from grsecurity.

Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:40 -05:00
Nils Wallménius
f7e9e9feb0 drm/amdgpu: Remove checking for atombios
This is a left over from radeon, amdgpu doesn't support any
non-atombios parts and amdgpu_device_init would bail if the
check for atombios failed anyway.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:39 -05:00
Tom St Denis
e11666eb9b drm/amd/amdgpu: Widen mmio trace register address width
Support wider address spaces, make it 32-bit so we don't have to
revisit this for a while.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:39 -05:00
Arindam Nath
44879b6261 drm/amd/amdgpu: get maximum and used UVD handles (v4)
Change History
--------------

v4: Changes suggested by Emil, Christian
- return -ENODATA for asics with unlimited sessions

v3: changes suggested by Christian
- Add a check for UVD IP block using AMDGPU_HW_IP_UVD
  query type.
- Add a check for asic_type to be less than
  CHIP_POLARIS10 since starting Polaris, we support
  unlimited UVD instances.
- Add kerneldoc style comment for
  amdgpu_uvd_used_handles().

v2: as suggested by Christian
- Add a new query AMDGPU_INFO_NUM_HANDLES
- Create a helper function to return the number
  of currently used UVD handles.
- Modify the logic to count the number of used
  UVD handles since handles can be freed in
  non-linear fashion.

v1:
- User might want to query the maximum number of UVD
  instances supported by firmware. In addition to that,
  if there are multiple applications using UVD handles
  at the same time, he might also want to query the
  currently used number of handles.

  For this we add two variables max_handles and
  used_handles inside drm_amdgpu_info_hw_ip. So now
  an application (or libdrm) can use AMDGPU_INFO IOCTL
  with AMDGPU_INFO_HW_IP_INFO query type to get these
  values.

Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:38 -05:00
Rex Zhu
0ef5b226c4 drm/amd/powerplay: move vi smu firmware declares to powerplay.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:37 -05:00
Tom St Denis
78bbe77117 drm/amd/amdgpu: De-numberify golden SI registers
Where possible replace numeric constants in the table
with their register names.

Compile tested + executed on a Tahiti.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:37 -05:00
Huang Rui
167112bff8 drm/amd/powerplay: add callbacks to move smc firmware request into sw_init phase
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:36 -05:00
Noralf Trønnes
30a1710187 drm/amd/amdgpu: Remove drm_debugfs_remove_files() call
drm_debugfs_cleanup() now removes all minor->debugfs_list entries
automatically, so no need to call drm_debugfs_remove_files().
Also remove empty drm_driver.debugfs_cleanup callback.

Cc: alexander.deucher@amd.com
Cc: christian.koenig@amd.com
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20170126225621.12314-5-noralf@tronnes.org
2017-01-27 15:23:16 +01:00
Dave Airlie
b0df0b251b Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
Backmerge Linus master to get the connector locking revert.

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux: (645 commits)
  sysctl: fix proc_doulongvec_ms_jiffies_minmax()
  Revert "drm/probe-helpers: Drop locking from poll_enable"
  MAINTAINERS: add Dan Streetman to zbud maintainers
  MAINTAINERS: add Dan Streetman to zswap maintainers
  mm: do not export ioremap_page_range symbol for external module
  mn10300: fix build error of missing fpu_save()
  romfs: use different way to generate fsid for BLOCK or MTD
  frv: add missing atomic64 operations
  mm, page_alloc: fix premature OOM when racing with cpuset mems update
  mm, page_alloc: move cpuset seqcount checking to slowpath
  mm, page_alloc: fix fast-path race with cpuset update or removal
  mm, page_alloc: fix check for NULL preferred_zone
  kernel/panic.c: add missing \n
  fbdev: color map copying bounds checking
  frv: add atomic64_add_unless()
  mm/mempolicy.c: do not put mempolicy before using its nodemask
  radix-tree: fix private list warnings
  Documentation/filesystems/proc.txt: add VmPin
  mm, memcg: do not retry precharge charges
  proc: add a schedule point in proc_pid_readdir()
  ...
2017-01-27 11:00:42 +10:00
Daniel Vetter
0683c0ab16 drm/moc: Mark legacy fields in drm_driver as such
No point in documenting these, they only confuse.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170125062657.19270-13-daniel.vetter@ffwll.ch
2017-01-26 10:46:00 +01:00
Alex Deucher
17324b6add drm/amdgpu: add support for new hainan variants
New hainan parts require updated smc firmware.

Cc: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-17 15:25:41 -05:00
Rex Zhu
ca581e4533 drm/amdgpu: change clock gating mode for uvd_v4.
use sw cg when decode. and hw cg when idle.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=99313
https://bugzilla.kernel.org/show_bug.cgi?id=192161

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Ack-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-17 15:25:26 -05:00
Rex Zhu
50a1ebc70a drm/amdgpu: fix program vce instance logic error.
need to clear bit31-29 in GRBM_GFX_INDEX,
then the program can be valid.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-17 15:25:04 -05:00
Rex Zhu
e05208ded1 drm/amdgpu: fix bug set incorrect value to vce register
Set the proper bits for clockgating setup.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-17 15:24:55 -05:00