Given a device which uses arm_coherent_dma_ops and on which
dev_get_cma_area(dev) returns non-NULL, the following usage of the DMA
API with gfp=0 results in memory corruption and a memory leak.
p = dma_alloc_coherent(dev, sz, &dma, 0);
if (p)
dma_free_coherent(dev, sz, p, dma);
The memory leak is because the alloc allocates using
__alloc_simple_buffer() but the free attempts
dma_release_from_contiguous() which does not do free anything since the
page is not in the CMA area.
The memory corruption is because the free calls __dma_remap() on a page
which is backed by only first level page tables. The
apply_to_page_range() + __dma_update_pte() loop ends up interpreting the
section mapping as an addresses to a second level page table and writing
the new PTE to memory which is not used by page tables.
We don't have access to the GFP flags used for allocation in the free
function. Fix this by adding allocator backends and using this
information in the free function so that we always use the correct
release routine.
Fixes: 21caf3a7 ("ARM: 8398/1: arm DMA: Fix allocation from CMA for coherent DMA")
Signed-off-by: Rabin Vincent <rabin.vincent@axis.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Keep a list of allocated DMA buffers so that we can store metadata in
alloc() which we later need in free().
Signed-off-by: Rabin Vincent <rabin.vincent@axis.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Allow zero size updates. This makes set_memory_xx() consistent with x86, s390 and arm64 and makes apply_to_page_range() not to BUG() when loading modules.
Signed-off-by: Mika Penttilä mika.penttila@nextfour.com
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ixp4xx and pxa25x both use this driver and provide a slightly
different set of register definitions for it. Aside from that,
the definition in the ixp4xx-regs.h header conflicts with the
on in the pxa27x device driver when compile-testing that:
In file included from ../drivers/usb/gadget/udc/pxa27x_udc.c:37:0:
../drivers/usb/gadget/udc/pxa27x_udc.h:26:0: warning: "UDCCR" redefined
#define UDCCR 0x0000 /* UDC Control Register */
^
In file included from ../arch/arm/mach-ixp4xx/include/mach/hardware.h:27:0,
from ../arch/arm/mach-ixp4xx/include/mach/io.h:18,
from ../arch/arm/include/asm/io.h:194,
from ../include/linux/io.h:25,
from ../include/linux/irq.h:24,
from ../drivers/usb/gadget/udc/pxa27x_udc.c:23:
../arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h:415:0: note: this is the location of the previous definition
#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
This addresses both issues by moving all the definitions into the
pxa25x_udc driver itself. It turns out the only difference between
them was 'UDCCS_IO_ROF', and that could well be a mistake when it
was incorrectly copied from pxa25x to ixp4xx.
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Drop support for platform data passed via a C-structure and switch to
device properties instead, which should make the driver compatible with all
platforms: OF, ACPI and static boards. Static boards should use property
sets to communicate device parameters to the driver.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
-----------
- Add a new stm32f469 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1rYKAAoJEMo4jShGhw+J6AAP/jho9aHsFYzHCMChp4fP8wiI
w9gLsD0m4Nz5VI16TInSwBTI0/PqiEEQ/MYWVJ/yMMo9De00Wnm48bAtEZ0UHMIP
ycwBrasdakpbtcuptEFjr8TIKIpnwK1wTgg2NFfMvYIs93LPOe/R3bjPg8qCCVoM
1YID1Kf27IHH1sgfqDBy7ZAoElW9z9EQwEaMwxEn7pABXv4Aq8SHZWbU6rW07pnj
h6x6wQL23tK9Afq+KGHi8l+kBHElF2xDQZPCFIKkS1u+y9dqptvdNxezGXxWswDy
R5ixRfype4NDKCibxmsIfPlc2eExoOOvyxqNTwdttUSeP6QdOMBFKQuxeY3nonqv
f0ZXGYz246iSRtN+gwjN69QYC/CtwNdlhn8MwQvvxavDHdx2ALZUC9jIZYJD+5LO
DMwUvya0FmOabs2CfavaS+NXGRwVzjvhyLtWr7Z48BYx3tWRYvYoavkK35U2Fvk/
wJ8IBm5yTT9WWhV3lIa8l7+CGwWi0x5yMZI+BWIZb54AFrdR8IJ52RQJ/exMRrn4
vCF1n7O2gtQSBv65ImFzaB9g1XrwN25G7em3bUc2KIbeCpQ+1kpZSa7pkDMsKZGX
nJ1auB9ght1D8uGxJ2hqjGwwhqE7RtT7tln8hOtykE3qBPNAytUhyAV4t4mFJ1zb
1bcNLvDGfm3chFREEVr6
=bK+a
-----END PGP SIGNATURE-----
Merge tag 'stm32-soc-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/soc
Merge "STM32 SoC updates for v4.6 #2" from Maxime Coquelin:
Highlights:
-----------
- Add a new stm32f469 SoC
* tag 'stm32-soc-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: stm32: Identify a new SoC - STM32F469
- Enable runtime revision detection for dra7 to avoid multiple dts
files for various variants
- Add dma_slave_map for omap1/2/3 legacy mode booting
- Add RTC interconnect target data for ti81xx and am43x
- Add custom reset handler for PCIeSS
- Add eDMA interconnect target data for dra7
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1hq3AAoJEBvUPslcq6Vz/H8QAMHYtBHdsUgNeH8mD0s65K70
7sWyaolm9p9xCjhFMmpgesOwEzkFzJBOXZ2edKa8wt0depk06AOJLZZLvNNYJoFB
AxF0+vRQmy2W+83hDSjnIsntxP4iN6w24jKDMOfXIsiwbFa2tX25xbAvcuCP3V8N
pWyNvSJUZcr1ZoOxRNulCp4+NgkzN90QPrvCKRITMb1mx/HAclVmaaHL+jczNmCE
3YM40+25yuzWqDe3jsvA3vPq/ZZTQmUxSF/gDSPCnNYdnWtVqd0DzRc1lYp5MHJL
e1teA/8wLHKvX+cVgyZSt9lb7RwymdWZreodzhI4rzKuFQvq5ySUQCJpGXD2YFg2
4W49CpqaDcZJjpih/TjXpyz66paArKBheg31NskTfALKEFxUPM8FXRbClmQyOvp+
wJ5ZtJbdYoxMJbqISDyIx8OgA2MkimGhPieTFzCCBelqrD9ovX51Ggy2ta0hSLx5
hZuyUw6oWMRCMQ1uZxuug34tnI2h5kyx2kM9gUBsmrO2/bKD4FfkHr9WJQ8EWavy
+r1NX5IlKoLhtThTzLqfyzqQMRgFq+FDo9Hy8NCXKgMWoURe/lZCtOCDivsf3VrI
eQ1HzJVRCBl1soA5RAow3b0o73nftXRPC78tcsxcAy9eQWLuxTVX0TxhfX1Cc7nO
sKjq/8q7tyjvxc0YHuOc
=tJb7
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "omap soc changes for v4.6 merge window" from Tony Lindgren:
SoC related changes for omaps for v4.6 merge window:
- Enable runtime revision detection for dra7 to avoid multiple dts
files for various variants
- Add dma_slave_map for omap1/2/3 legacy mode booting
- Add RTC interconnect target data for ti81xx and am43x
- Add custom reset handler for PCIeSS
- Add eDMA interconnect target data for dra7
* tag 'omap-for-v4.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
ARM: OMAP2+: Add rtc hwmod configuration for ti81xx
ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
ARM: OMAP2+: DMA: Provide dma_slave_map to omap-dma for legacy boot
ARM: OMAP1: DMA: Provide dma_slave_map to omap-dma
ARM: OMAP: DRA7: Make use of omap_revision information for soc_is* calls
ARM: AM43XX: hwmod: Add rtc hwmod
ARM: DRA7: hwmod: Add reset data for PCIe
ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
ARM: OMAP2+: hwmod data: Add SSI data for omap36xx
- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJW1Z/XAAoJEFBXWFqHsHzOfUEH/1oiBDMBJEKH8/vmipV5cPmw
TAcK4W/1mS0SZo8xSYyi0iGcs5loA7fiypBZv6tKxI2IZS1w3sbJ0eHeeUUkURsG
okMpHCMeuEdjnWH/nTdABKGIlK1nAtwuDuD0BJqlk1VDLY/pIUY5kkoWsrXMlzwO
VkS2ic90HjsijmLH5y38kgo6RvkDDBxMzl8lzTxwfMNO8P5zCn9Wiqeerlbt/+Nw
+n8aDzow4XKuOaHaoh6/C9RSKkobCAs/RVwoYUhv4QCk1zC6rJ1Oq6yuYGJgiIOX
+gtdAIxTVv4RDJfEWEMT+N9SFM4qcFDAGtGPoXZyRKeedC5/xXuD2yNn2RUzShc=
=RoB/
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "i.MX SoC update for 4.6" from Shawn Guo:
- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups
* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: Make reset_control_ops const
ARM: imx: Do L2 errata only if the L2 cache isn't enabled
ARM: imx: select ARM_CPU_SUSPEND only for imx6
ARM: mx25: Add basic suspend/resume support
ARM: imx: Add msl code support for imx6qp
ARM: imx: enable big endian mode
ARM: imx: use endian-safe readl/readw/writel/writew
ARM: imx7d: correct chip version information
ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
ARM: imx6: fix cleanup path in imx6q_suspend_init()
for the v4.5-rc cycle:
- Add back optimized cpuidle parameters for 34xx that were
incorrecly removed earlier with cpuidle cleanup
- Fix SSI for omap36xx to get modem working on N950/N9
- A series of omap hwmod fixes via Paul Walmsley <paul@pwsan.com>
to fix SSI for omap36xx for modem on N950/N9, fix for
OCP2SCP sysconfig idle mode, and reset data for PCIe on
dra7
- Fix out of range register access for omap3 control module
if syscon max_register is initialized like v4.6 will be
doing
- Fix l4_ls interconnect clocks for 81xx, it should always
be sysclk6_ck
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1hi8AAoJEBvUPslcq6Vz2DQP/jGerFh+98FhppQdCiu/xgY7
y+GB97UF8I6y4zoQ2NT4/hm7/RJDtZKLtyZkWQYvZFYfMbKsPyyITF9WSN5m4eIy
Z9F1PMl19AgY4F3K5E0aJ/kTd9hEMEDTMnwSfQy/kToCEJQLX8QZZx49pmV13qgx
vL81Unj7lWb0cWspRN8ShKNK49oFfwzGc+EFudx0aIoIckGEHjBAgJ7WDEN6jdhC
EnQbEhUajC5deCWvP1+SjopMt5tF5kJOSRfhHOfsyGvonOdrXAXZ1IgLKla+T2Zw
twOBmdHzou1LuJo0m5nr6R6cEegtqV+Hi2wLYvQ+Fach6xBUzUAB8xvWvKrGF2Eo
8xmRuPaUWU7raxdHbmsh/VF8dpUw9M+k/X2FMA3axPk6Z1mt9XlJpCTCvJMzg09C
M+yuuPjYRB+Eh/VXjoL33n6LSMYmgKVRy6wyYBPJgtec0uG5HRaP07UiappojrRf
+7kWyxSyhOcUzUa04sbo4IqgRU3vIpucB3z3WsRzGL/d8RoW2Ox2/49WmSKvO4NA
BxRpu2mTT6o8CIoaqaKrhPWjkXFjiWujqzgt/Li9qzzIlsUzJuAnJpeKBgLlBwIy
HrzdYT4+Et1ofbIcaQ7uhQ/Wq+Aw8anJbn2X9M5FDOTLlUs0s0JO5ZC6v8hj271+
hpS6cFLs/bB8cvBELpQd
=pwoK
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
Merge "omap non-urgent fixes for v4.6 merge window" from Tony Lindgren:
Fixes for omaps for v4.6 merge window that are not urgent
for the v4.5-rc cycle:
- Add back optimized cpuidle parameters for 34xx that were
incorrecly removed earlier with cpuidle cleanup
- Fix SSI for omap36xx to get modem working on N950/N9
- A series of omap hwmod fixes via Paul Walmsley <paul@pwsan.com>
to fix SSI for omap36xx for modem on N950/N9, fix for
OCP2SCP sysconfig idle mode, and reset data for PCIe on
dra7
- Fix out of range register access for omap3 control module
if syscon max_register is initialized like v4.6 will be
doing
- Fix l4_ls interconnect clocks for 81xx, it should always
be sysclk6_ck
* tag 'omap-for-v4.6/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix hwmod clock for l4_ls
ARM: OMAP2+: Fix out of range register access with syscon_config.max_register
ARM: OMAP3: Add cpuidle parameters table for omap3430
ARM: DRA7: hwmod: Add reset data for PCIe
ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
ARM: OMAP2+: hwmod data: Add SSI data for omap36xx
-----------
- Enable GPIO led driver in stm32_defconfig
- Introduce a config fragment to override RAM base address
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1rV2AAoJEMo4jShGhw+JXIgP/iTq3X5thCRCnhj9gyVlaZAC
Iv+HE+ZaFmpwDnzHfmtrDVnKhHMc3SFqNcCuD+FFLdfZoqB+Qi/RfK+DHqbFIfwY
COa41koW1pRgjqHTzPmJqVxB2wiETvWOE6KUjZrfT3EUGdvghiy9EAnyN0RppbIp
CNivabvnqKEiVk9rqtbx6veWBw0aQyg2oL0d8ypPsGP8u87FmIqWpDK0vw8c2JyV
MuCEt/sDBMtWNr89ylJqAIUiRlm/pFhQY32BxlkfYfqjz1xBac/5BihhK1cP2cZW
FtDV4Y3IF4Lm+c41EXazYbiduY7OMkKb5XVUGsjFfZKNxTTQbzOvahgpW7cImFPE
kMzdV8mVD0g0eQumXNeg2wSJgfjxx6kxGWwxUVaFAL82FizuRyDLruDnBmfkQ92P
uVnFH6wIs9oiBNmVaBibMun61aexLVjzJqPepI+Ray9tJInwz5QsK+oRUe8hXyAJ
QmExU49z/dY49NYGIyTqE0wQx26gjmyYUqFnUEktsXMkKzuwU99SxUwxhUhgr48H
agr1fpj4g1gBHQdoHPPvCfb1Jp60Hnl0iSmr5Yv5ay5n1xs+r2IOzenZaY0UaTiy
alJLf7yHSyNwmPgxgpO0+Z/Yc3faQgTu5q1FatDxTmD3rDjDd0JMhv75O9+Z/k6e
AGBkwtGMi1040O3LpvMI
=dBNt
-----END PGP SIGNATURE-----
Merge tag 'stm32-defconfig-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/defconfig
Merge "STM32 defconfig updates for v4.6 #1" from Maxime Coquelin:
Highlights:
-----------
- Enable GPIO led driver in stm32_defconfig
- Introduce a config fragment to override RAM base address
* tag 'stm32-defconfig-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: configs: Add new config fragment to change RAM start point
ARM: config: Enable GPIO Led driver in stm32_defconfig
for v4.6 merge window:
- Enable IOMMU and omap3isp so we can enable TVP5150/1 video
decoder
- Enable at24 eeprom for revision detection on beagle-x15
- Enable LP872x regulator for both omap2plus_defconfig and
multi_v7_defconfig as it's needed at least by LG Optimus
Black
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1hwfAAoJEBvUPslcq6Vz9UwQAKKtMT4EsO+oBFYNtwippBF0
o2RhThB0Pwve48H+sQOvdeDz0FAisAYd9kecG033QMLEYrASneXaM0AYkeDIjJCE
5SzwLtNumwhhYbeoQNCIcC+V/rDAplD4KR1WSteeWBPwHweGK3cWfczWN8FRmNqk
iPfDqSb70C8bUpQeHhGc2xRGthVDKpZeeO9gsfAYOBJGHkMfe2bjyaGRUynoN/Az
UyBOmr2gmw+YQTknYtsdHnxXBLlhUz6bDKsoB0wXtP4BSrAeenf+Tm7jmWiDZbeG
wSNmnp7DM/l5kBb8M8BJRfNDpk44ro+OkUYXGUoBmP0Mw3OFeqhXBlj3gugtQR7j
xQ9BJ4wcWwvxP1rukeqTpwobsMydenJCrw57I7iW+bLn5D6YMx/TJIITeq895tcg
6xCGlY++78W20NkGtctQMtqpt9zV/HTxQRkJIPzfSd3b9mfWTLimK+DYKwGxgym+
LgoCQwPJrZAZzvE3/nkyhx0kTEPbyRbCvT33xBRerPIYgGRq+DSZFmsLyFW1OKdT
VT1uOHuChqertqTUONdW6d6QQuwo6PheOmFz7Z3fJbizu5Uuim+YgkxxKBL+5kKg
VKJuEfAs2CqS506yCxtGG/eTrmxWHXkSXu75H1yXPVcnn38vjwH9wqiorcKOO9Em
FNN5I14TW4Lt+DqkNpx8
=JVC1
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/defconfig
Merge "omap defconfig changes for v4.6 merge window" from Tony Lindgren:
Defconfig changes for omap2plus_defconfig and multi_v7_defconfig
for v4.6 merge window:
- Enable IOMMU and omap3isp so we can enable TVP5150/1 video
decoder
- Enable at24 eeprom for revision detection on beagle-x15
- Enable LP872x regulator for both omap2plus_defconfig and
multi_v7_defconfig as it's needed at least by LG Optimus
Black
* tag 'omap-for-v4.6/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: multi_v7_defconfig: Enable LP872x regulator support
ARM: omap2plus_defconfig: Enable LP872x regulator support
ARM: omap2plus_defconfig: Enable AT24 eeprom
ARM: omap2plus_defconfig: Enable TI TVP5150 video decoder support
ARM: omap2plus_defconfig: Enable ISP support and dependencies
ARM: omap2plus_defconfig: Enable OMAP IOMMU support
1. We want thermal for Exynos7 TMU unit to monitor the temperature.
2. Enable the drivers for PMIC used on Exynos7-based Espresso board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1VxBAAoJEME3ZuaGi4PXz/wP/1/mAzScizlcdGi7k1DmP7fZ
9rsAiXYjIjxcI96L0qrEBCZFDdSwBv/pCRTuCg94FClFYBuW+IZmkTeWPHvtsB5O
my4Xk3O5WEQbpFPUTZwl8yTlRSwlRdob7lGBFWuapqiCcws6l5xRffG1n6itqN32
RTzLfeSAAj9zg94EX8UaNYcW9T0aIR/QGOIRXfziorACj5FdSiNvnXNwZBPj39ti
X47h3BuLjCio0LPPSwNf4Z7XqenOX8z77Y8WTOi0WaRcnirdyjlOFTCLMCYvWIVw
oih2xofdkDH+QsPOY1Qj96C6I1cUhqC3Z+fvz0PiPfk4Lit7hts+tdZ/8HBdX4V2
tLodKxL7QowlrwbcRWn7i/MujiOTv6H0+OlJWucrOSFwmYqce8kNdyI/DIp5wNyS
5NpfLX47SzL8sF4KnxdS8dvYrIT+mJUfuNAexNE44orwrm9AHbmTMNs1ZrGJd4Y7
wlHg/q0m2lwhG8hvVUiDUwTwkljP1Z94zjJSGK0JMIlBwVbCEKNmBEJZv54RseMV
47xDisM6RY1SWWx497vXaPcP42AivQn9a/rPJoaeEIsxJgQDTeHmbiCSWJYe43QD
blKjwBb35QORnkc6tkBDOREFahF0uWVYS+7NOHcbDih2efb65rHAURzrnJIUBXTZ
QR9mA4PxcR54BFs9RznS
=T9z9
-----END PGP SIGNATURE-----
Merge tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64
Merge "ARM64 defconfig changes for Exynos based boards for v4.6" from Krzysztof Kozlowski:
1. We want thermal for Exynos7 TMU unit to monitor the temperature.
2. Enable the drivers for PMIC used on Exynos7-based Espresso board.
* tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: Enable Samsung MFD and related configs
arm64: defconfig: Enable exynos thermal config
ARM: multi_v7_defconfig: Remove MAX77802 RTC Kconfig symbol
ARM: exynos_defconfig: Remove MAX77802 RTC Kconfig symbol
rtc: max77686: Cleanup and reduce dmesg output
rtc: Remove Maxim 77802 driver
rtc: max77686: Properly handle regmap_irq_get_virq() error code
rtc: max77686: Fix unsupported year message
rtc: max77686: Add max77802 support
rtc: max77686: Add an indirection level to access RTC registers
rtc: max77686: Use a driver data struct instead hard-coded values
rtc: max77686: Use usleep_range() instead of msleep()
rtc: max77686: Use ARRAY_SIZE() instead of current array length
rtc: max77686: Fix max77686_rtc_read_alarm() return value
ARM: exynos_defconfig: Enable s5p-secss driver
ARM: exynos_defconfig: Enable NEON, accelerated crypto and cpufreq stats
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- addition of the NAND flash node
- addition of the dma properties for UART/USART nodes
- one update of the sama5d2 Xplained phy node
- addition of USB pinmux, button and leds
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJW1w1UAAoJEAf03oE53VmQmkAIALy7FfwfsXwV4EBMjrkyBbHF
6fODom/DihCOaATD1tOaKaW0imyNXRu6qsnV5PZNRU7SCbJffolcY852iAW8I6hL
qmdTumHGQszMJu95Nz+au04l9rqGvzeQ3v136YueMFtn6oQydF/6ttQzjjcCRKPy
0FRTk6IKroKZ2qRl4dbvnMF1QJW+3eSe5U3mULEkTdc2Fup60cfwP9Z8uzzYIYgf
CnMwyakQxqp/Y9tYTIMS/RKj+VuQxI0+nN6f8dWKsWbIKIEk6n8W+RtrKdYl1GZ2
VT0GsCJ/qw+EHqk3dD45tFFIvdiXIc9UElB4p+s7CLqX4GAShN1JNkidkBrTgKw=
=7QLe
-----END PGP SIGNATURE-----
Merge tag 'at91-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/dt
Merge "at91: dt for 4.6 #2" from Nicolas Ferre:
Second 4.6 DT series, all patches for sama5d2 and its Xplained board:
- addition of the NAND flash node
- addition of the dma properties for UART/USART nodes
- one update of the sama5d2 Xplained phy node
- addition of USB pinmux, button and leds
* tag 'at91-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
-----------
- Fix clock references in GPIO nodes
- Add early support to stm32f469 MCU
- Add USB HS support in host mdoe to stm32429-eval board
- Add Ethernet support to stm32429-eval board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1rPwAAoJEMo4jShGhw+JJo0QANKHRLLRxNy/fGCp/eg5mabi
SfGxa+5K3wtFzYCo49bsHBY9e1f9mjck8TnJDqUPhWreF4kyCiDkSi93lHkqjYu0
+vYLtHdzTjWWcYZr9SsBfsMQURqAN9SypTIzgPgAy3ZeX50uhaZZQp9kAL/vn4Nr
8o2wfG5BuNzVdPcZBHTfab9anzsqZHTzUVds2h9o+qgMiHiPtFMJuSaOvMDCu/gK
Jp01NMY77ACE6s5k19EVxU42WE0Q+QmCEFig5xFjm6xUdIQdFSKx1Gal0Ngg9t0Q
CkOdjOVTWWbFtKWP+D80U996FmRY0xT705E97f123KnQJ64wJ7izdZuEDRy/2bgM
GPCdihQmBZLzf9PnXTpypKvrsoMG36CxSnFMbzSYrCHuPBRf3Ii8QyO3lr5s993A
a+VOAhij6TePp/P18mlL+XUCPV1Y+bAUJTDZpVgP4KbhrrdwkioHEV7KZ2fpK+bu
Wa5696DUqIjMsixBIWxc4FxR88t8AffpPIKu3vgMZV+bxFApXQF9b4R+JppAkZtg
mBxj84mt26tkhlnUkeBqLWx0/f8oAuUhDCCgrdmS7/xPOg29uHhkmG0P0Q0D/+5+
ulh3WcHwC6/v94C8NkKWh8z5RfMSlO81DDCGVY0e8gUOeY4F64eFEKGjQlGqCr6j
ePT0lq3OkSs3W0ih4VV+
=SVE6
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/dt
Merge "STM32 DT updates for v4.6 #2" from Maxime Coquelin:
Highlights:
-----------
- Fix clock references in GPIO nodes
- Add early support to stm32f469 MCU
- Add USB HS support in host mdoe to stm32429-eval board
- Add Ethernet support to stm32429-eval board
* tag 'stm32-dt-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: stm32429i-eval: Add USB HS host mode support
ARM: dts: stm32f429: Fix clocks referenced by GPIO banks
ARM: stm32: Supply a DTS file for the STM32F469 Discovery board
- A series of GPMC related interrupt changes from
Rogeq Quadros <rogerq@ti.com> to prepare adding interrupt
support to the NAND driver
- Add RTC support for ti81xx
- Correct LogicPD Torpedo mode description
- Add basic support for LG Optimus Black phone in several
patches by Paul Kocialkowski <contact@paulk.fr>
- Change address-cells for dra7 for LPAE
- Add TBCLK for PWMSS on dra7
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1h3JAAoJEBvUPslcq6Vz3sQQALjoT1HdNXPsS9fxoCBMRvcc
ZLMrntfj7QId/uZ63zhSxUqYRZWAGz9paDl43uS6uwWGL7G+Mml8fcpxKR008co2
gKPmAwTIYtfZDq63/mQ38jIkmr4Nj/qvY6COFDz2s5IIv41m2LMEleX5QBs8k/3X
F0FL5A9DYRaVZ5tYmZ64mVcJM/CIdDwyRjhtlV1QHVJrDQVPqcRyZGLuRzQKgati
HG0rUc8/B4ECEryrDK5ZtNqJ5LmpThfyzrjaUMzA8mOBo5HTAOOAkwFTtAxppba9
mHZQgNrJ+nAOShDmb+1wAanWw9s+UtsjKppbOhNdk2QyP4DCX8WIsRPZtp/aiDN8
6+I9mYspffe+uFKrwOpcWqtUk+Dft4P0rbcWGm5Pp+dbfSa94gYoyzHDByP5Lgtv
DOMpEZfqC/uHuhjS3ZIN4EnT2t3mY2aMupWYIWKxjv06X+Cp80XIdB5NVGzGFsqe
5ksvykF75YxMskdyo6egT+2jr+bgRkEs6H76ZHqkc6qTtGxIu6JHiuolOOen8uGH
gk3QbWY6oN6uzwtpcddQkrZkYxeoxOIH9AobHuNQ2MlCE0HwCXNE7U79/fjAv9Zs
dbwkVo5C0fraNG+f2waFskwni3mkUYiUIs8/YXXPLsXKavs9XvL5Wxxz/u7v5c+/
0hdZB8mJuoEtKvmhNk8Z
=JMzE
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Pull "Part 2 of device tree changes for omaps for v4.6 merge window" from Tony Lindgren:
- A series of GPMC related interrupt changes from
Rogeq Quadros <rogerq@ti.com> to prepare adding interrupt
support to the NAND driver
- Add RTC support for ti81xx
- Correct LogicPD Torpedo mode description
- Add basic support for LG Optimus Black phone in several
patches by Paul Kocialkowski <contact@paulk.fr>
- Change address-cells for dra7 for LPAE
- Add TBCLK for PWMSS on dra7
* tag 'omap-for-v4.6/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: DRA7: Add dt nodes for PWMSS
ARM: dts: DRA7: Add TBCLK for PWMSS
ARM: dts: DRA7: change address-cells and size-cells
ARM: dts: omap3-sniper: USB OTG support
ARM: dts: LG Optimus Black codename sniper basic support
ARM: dts: dm3730-torpedo-devkit: Add "Wireless" to model
ARM: dts: Add RTC entry for dm816x
ARM: dts: Add RTC entry for dm814x and dra62x
ARM: dts: omap3: Fix NAND device nodes
ARM: dts: dm8168-evm: ARM: dts: Disable wait pin monitoring for NAND
ARM: dts: dm816x: Fix NAND device nodes
ARM: dts: am335x: Disable wait pin monitoring for NAND
ARM: dts: am335x: Fix NAND device nodes
ARM: dts: am437x: Disable wait pin monitoring for NAND
ARM: dts: am437x: Fix NAND device nodes
ARM: dts: dra7: Remove redundant nand property
...
- New i.MX6 board support: NXP/Freescale imx6qp boards, Advantech/GE,
Uniwest evi, Engicam IMX6 Q7, Toradex Apalis SoM and Ixora carrier
boards
- Relicense vf610 dts files under GPLv2/X11
- A patch series from Stefan updating Vybrid Colibri board support with
PMU, regulators and other devices enabled
- Correct PWM pinmux for Ventana boards and add more pinmux for GW54xx
- Clean up imx6q-tbs2910 dts file and add SATA PHY configuration
- A series from Russell cleaning up hummingboard dts files
- A series from Lothar updating Ka-Ro i.MX28, i.MX53 and i.MX6 boards
to use better audio codec frequency and display configurations
- Clean up whitespaces in i.MX6UL pinctrl header and add more devices
support for the SoC
- Other random dts updates to enable various devices
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJW1aZfAAoJEFBXWFqHsHzOWvwH/1ieekZ5VYnGyO4CT39DaNxU
LMkywkPtp8oUfdVHOfGEMj43knYHsaVFakGS2w8iMNzg+YonWXG/mkR3HUJmoS1L
HzFEnapLzACSSCbn8yZzWzzNvAlg2arqFErQUlhXe9/CNz64uZSigsO3Ib/JNOlX
GWDRa8szryEkEyk2cJo/wyWWSkLGGRai4uNBR6BmUq/MltVjVHOvTV5NeyKpinHZ
mQQFGEbvVk1hJ0sfceX/rmdxgvV0H3Axq8C0JyzbevUTcvS45A85tEXHkrHbYb/f
mJCNXxmmt+NrH8x79YxnuhKTRQ8lNn8fBu9wOtMaBJjRNB3ie3HBh2QabXBs/MA=
=FKmy
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt2
Merge "i.MX device tree updates for 4.6" from Shawn Guo:
- New i.MX6 board support: NXP/Freescale imx6qp boards, Advantech/GE,
Uniwest evi, Engicam IMX6 Q7, Toradex Apalis SoM and Ixora carrier
boards
- Relicense vf610 dts files under GPLv2/X11
- A patch series from Stefan updating Vybrid Colibri board support with
PMU, regulators and other devices enabled
- Correct PWM pinmux for Ventana boards and add more pinmux for GW54xx
- Clean up imx6q-tbs2910 dts file and add SATA PHY configuration
- A series from Russell cleaning up hummingboard dts files
- A series from Lothar updating Ka-Ro i.MX28, i.MX53 and i.MX6 boards
to use better audio codec frequency and display configurations
- Clean up whitespaces in i.MX6UL pinctrl header and add more devices
support for the SoC
- Other random dts updates to enable various devices
* tag 'imx-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (75 commits)
ARM: dts: imx53-qsb: Fix gpio button polarity
ARM: dts: vfxxx: Add DAC node for Vybrid SoC
ARM: dts: imx6q: add missing links between ipu2 and mipi dsi
ARM: dts: imx: Add support for Advantech/GE B850v3
ARM: dts: imx: Add support for Advantech/GE B650v3
ARM: dts: imx: Add support for Advantech/GE B450v3
ARM: dts: imx: Add support for Advantech/GE Bx50v3
ARM: dts: imx: Add Advantech BA-16 Qseven module
of: Add vendor prefix for General Electric Company
of: Add vendor prefix for Advantech Corporation
ARM: dts: imx35.dtsi: change the clock information for usb
ARM: dts: imx25.dtsi: change the clock information for usb
ARM: dts: imx6ul: add kpp support
ARM: dts: imx6ul: add gpmi support
ARM: dts: imx6ul: add lcdif support
ARM: dts: imx6ul: add sai support
ARM: dts: imx6ul: add flexcan support
ARM: dts: imx6ul: add sdma support
ARM: dts: imx6ul: add pwm[1-4] nodes
ARM: dts: imx6ul: disable PWMs by default
...
1. Split common reboot/poweroff node to separate DTSI.
2. Don't overheat Odroid XU3 by cooling CPU with cpufreq.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1VvJAAoJEME3ZuaGi4PX0IoP/24addMWJyve/UVCh28cNV0l
gNWhCuVq1bXJIPRNSw+ZOln/XZSjcyuwqU1JNfjz2SsgaaVffPGIioJbKk55qnW7
gUO6vtwO3hxMe1kmAp7cehOep3zSr7YjxvckCmTZVZm/S0skNtsY1YM5M1hqBqi5
yoiozpoUk7LE+4VEYlDhjArwW4qaiQ1PzwD7w+G91zpuRefPiKslWdiOJw0h7BD/
yA0X6rbXC2zjRfKI5kF6dq/bKpWAqweW1FshA4EWG5Tx6jrip2q9qlH5bCl423lc
55mbJYg0YYMBt4I/GQ2oVRnqQulraj2Id2txrXlVbyji9fq7rvJdoMkVjH3CXyod
P7s7FqCgLxd/VVZw9n/Yz8XFlMRvhFMBQ/9ZXm2rpJoRcW3IekIXib23h8kX1I5l
Dd8PCAwmjCRzWCGIaGh1M7JfGDKTXyCrohK+iu78PCJQd0PYkF79Bzc7Ckcsyj/k
P7wzjpwZb83RkSU/VhgpqWxBFICTEyHruLLVCIiTFLyC0CUYOtff9aUYAiWNCQRZ
moLTJr7bqMwuDd0kz/poJ8wdQ+FRZEQfnY64Lxy73L6/lHg9tbHw3tDC7OP3RyWX
QzR3kKrDQdkUp7O+i8YPmQ+AdfnA1cqqds4RlFm+/m6Rm3/7V6d9I1bLy3hgrYcJ
87Zu00PFeuDrDORDhRCY
=P/fL
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Merge "ARM: EXYNOS: dts for 4.6, 2nd pull" from Krzysztof Kozlowski:
Samsung DeviceTree updates and improvements for v4.6, second round:
1. Split common reboot/poweroff node to separate DTSI.
2. Don't overheat Odroid XU3 by cooling CPU with cpufreq.
* tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
ARM: dts: exynos: Add cooling levels for Exynos5420 CPUs
ARM: dts: exynos: Move syscon reboot/poweroff to common dtsi
All PCI mmio ranges are dynamically mapped now, so we
can remove the fixed virtual address definitions.
Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Instead of using old GPIO API, let's switch to GPIOD API, which
automatically handles polarity.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
In an invalid randconfig build (fixed by another patch),
I ran across this warning:
arch/arm/include/debug/at91.S:18:0: error: "CONFIG_DEBUG_UART_VIRT" redefined [-Werror]
#define CONFIG_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)
As Russell pointed out, we should never #define a macro starting
with CONFIG_ in a source file, as that is rather confusing.
This renames the macro to avoid the symbol clash.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Suggested-by: Russell King <linux@arm.linux.org.uk>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add the three leds on the sama5d2 Xplained board with their pinctrl node.
The blue led is positioned with the "heartbeat" trigger.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: add commit message and adapt to newer kernel]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add the push button named "PB USER" with code 0x104. Associated pinctrl node is
also added.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
For USB gadget on port A (device mode):
- pin PA31 is configured as an input GPIO which triggers an interrupt when
vbus is detected on USB port A.
- pin PB9 is configured as an output GPIO and set to low level so the
board doesn't supply vbus to USB port A.
For USB host:
- pin PB10 is configured as an output GPIO and is active at high level.
The ohci driver will activate this pin so the board supplies vbus to USB
port B.
- pin PB9 should be configured as an output GPIO and active at high level
to use to USB port A in host mode (conflicts with USB gadget).
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
MAC is connected to a PHY in MII mode.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@gmail.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Now that the AT24 uses the NVMEM framework, replace the
memory_accessor in the setup() callback with nvmem API calls.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Detailed description for patchset:
1. Add new EXTCON_CHG_USB_SDP type
- SDP (Standard Downstream Port) USB Charging Port
means the charging connector.a
2. Add the VBUS detection by using GPIO on extcon-palmas
- Beaglex15 board uses the extcon-palmas driver
But, beaglex15 board need the GPIO support for VBUS
detection.
3. Fix the minor issue of extcon drivers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW063aAAoJEJzN3yze689ThbEQAJbn/pHDRlw7u8NUiNfRbQWd
uf//IiF2tbJ8eGpCvYIh+dLSlFbFzn3qIETAXJjZ7NfqYpgZsDAwFoMnVF6FfcMG
o2GAVGnUaXge+s+r5PkIwaCRh9LWO5iHJTHjykonhXaKKO4NrHxtsspo/We6Kth4
kmsrmovWd1CvnsvNZJXFSFf37z2eZFG+RYyrveKhFiTlliqyX/DT/RgOqPPPa0UC
9FBXrQ67ibKymX2qYLb5USQnppNFrnzDCacJBiFc2z/kpFFkII7XDrJVogn2JJfZ
M4uQ8JWqBhjrh2yU1FtQ7vuBfk8/Ssbvbp7J+roHJZGwe6AjVY2d3WCRGMLy/fFh
rCfsVvCrwupPVsVj50yTVyEJ0kiDZ9tz3rboWxfuTv/AtRxpUm9gMZ6yE/g2cBl4
RnkYp9dE/Kmu5BaaJZm9yIlHOEgQD/nhXGWm+BdgJBPB2+qAA0D7VPav0Fazjr8O
fN/kyaFHZ5jxSynGVCTsbfD8cJiVWdRzyxwoeXllvGqxwcdgHzX7LrTXrDkRtgC3
5r1B6qgm0kpPxYotrfPI+vAQnR5PGYBa0L4mwXha1rnonwI39QIgg76ZsHyy6k2u
rwGpT3zQmxFs9puf6pFAGmFCaLd1nb5r7FrslkZsn4gG100Gi0ONRRyN6Jx7f7W2
x/EvDnRYTM/pNpNp04Yb
=Zxas
-----END PGP SIGNATURE-----
Merge tag 'extcon-next-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-testing
Chanwoo writes:
Update extcon for 4.6
Detailed description for patchset:
1. Add new EXTCON_CHG_USB_SDP type
- SDP (Standard Downstream Port) USB Charging Port
means the charging connector.a
2. Add the VBUS detection by using GPIO on extcon-palmas
- Beaglex15 board uses the extcon-palmas driver
But, beaglex15 board need the GPIO support for VBUS
detection.
3. Fix the minor issue of extcon drivers
In the final versions of the Porter board (called "PORTER_C") Renesas
decided to get rid of the Maxim Integrated MAX3355 OTG chip and didn't
add any other provision to differ the host/gadget mode, so we'll have to
remove no longer valid "renesas,enable-gpio" property from the HS-USB
device node. Hopefully, the earlier revisions of the board were never
seen in the wild...
Fixes: c794f6a09a ("ARM: shmobile: porter: add HS-USB DT support")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds support for the volume and gesture keys, using TWL4030 keypad.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This reverts commit 5fcc673067.
The binding may need to change pending related hwmod comments,
so reverting as requested by Paul Walmsley <paul@pwsan.com>.
Let the non boot cpus call into idle with the corresponding hotplug state, so
the hotplug core can handle the further bringup. That's a first step to
convert the boot side of the hotplugged cpus to do all the synchronization
with the other side through the state machine. For now it'll only start the
hotplug thread and kick the full bringup of the cpu.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arch@vger.kernel.org
Cc: Rik van Riel <riel@redhat.com>
Cc: Rafael Wysocki <rafael.j.wysocki@intel.com>
Cc: "Srivatsa S. Bhat" <srivatsa@mit.edu>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Sebastian Siewior <bigeasy@linutronix.de>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Turner <pjt@google.com>
Link: http://lkml.kernel.org/r/20160226182341.614102639@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
These patches add RTC support for the AM43xx, and add support for
the DRA7xx eDMA controller's TPCC, TPTC0, and TPTC1 IP blocks.
Also included is a workaround for PRCM hardreset control of the DRA7xx
PCIe subsystem.
Note that I do not have a DRA7xx board, and therefore cannot
test any patches for that SoC family.
Basic build, boot, and PM test logs can be found here:
http://www.pwsan.com/omap/testlogs/omap-hwmod-b-for-v4.6/20160301021258/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1WdKAAoJEMePsQ0LvSpLoO8P/A05egqdZtbWCte8tK4/E+d1
fdzaev9dC8I6rWlxV6PTFZL8Hw28XtQZDYqV2voRE5nxma1L05Uang2c2tNmO7oH
Qa7pvD/m6vy3A2ZIKgTJeV7Elc5SNEmPQq6/1z1viWni4oUFWrsP1cKPTmUOhTNu
cx6Q2oxkoGlLRmonygJ49da6XShPMIOolDUNfOKFuSmt80RUor2j1Wpu+3wlVZvr
53jSLG8C+RgiUeBT90PUOvI7dAfocOV+G8CnH7/Fnss9+L2skiKwOOUNudGBz3JZ
elAwjyiCkBlo3VGSRk4UarXuzAdCqZqvLSemYZ1JbYT3SbbIWovJ9nX17y7Gl7RT
4KnGW0P+yeYYj9iEwUOs1Yj4DgFTbgkmHqkF2zWPGawjj3AMUKquvYVR1d+Oz3NR
77wdAPIKWWRJ5V8QiQhKiZjpj4TkR7KT1fAF78Kf4eMXwy5tbXUkXyKpj0Izi1Z2
Oe2NHcGOMXbSBYSBK0N9sYXFWKhE3CRkEZ3yoYwTwoDYpDuMWffnRX1a0TGseUb3
xX9j+818/FyKhwEdL4rIHwOYW/iITLUOSUAOt2lnM2xWx3G1aNX7RjreOdobVm7Z
8ZVbX2zFBrP8Fe964ZutoG7FjBqurrOtoJUrZPEPWOcjDMPBi9JfRfwtLzglAnXh
IUglDUxMXscaQulEez3J
=ospe
-----END PGP SIGNATURE-----
Merge tag 'for-v4.6/omap-hwmod-b' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.6/soc
ARM: OMAP2+: second set of hwmod changes for v4.6
These patches add RTC support for the AM43xx, and add support for
the DRA7xx eDMA controller's TPCC, TPTC0, and TPTC1 IP blocks.
Also included is a workaround for PRCM hardreset control of the DRA7xx
PCIe subsystem.
Note that I do not have a DRA7xx board, and therefore cannot
test any patches for that SoC family.
Basic build, boot, and PM test logs can be found here:
http://www.pwsan.com/omap/testlogs/omap-hwmod-b-for-v4.6/20160301021258/
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].
[1] dm814x TRM: SPRUGZ8F: 11.2.4.12.2 NAND Device-Ready Pin
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add Ethernet support (Synopsys MAC IP 3.50a) on stm32f429 SOC.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@gmail.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
The polarity of the gpio buttons is defined to '0' which is
active high. The buttons are active low though which has been verified by
testing it and by looking into the schematics. While at it use
defines rathers than numbers for the key codes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This makes it possible to automatically boot-test this defconfig with
kernelci.org.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Regenerate imx_v4_v5_defconfig by running:
make imx_v4_v5_defconfig
- Manually disable EXT2_FS and EXT3_FS
make savedefconfig
mv defconfig arch/arm/configs/imx_v4_v5_defconfig
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Both nodes are required to access NAND Flash memory. Additional
settings will be necessary at the board level to use it.
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The dmas/dma-names properties are added to the UART nodes. Note that additional
properties are needed to enable them at the board level: check bindings for
details.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
All pinctrl nodes for the Atmel pinctrl controller need to have their
bias configuration explicitly defined. Otherwise, the pinctrl mapping
is not valid.
It works for now as the pinctrl driver proceeds even with invalid
mappings, but this can become an issue, if the pinctrl driver starts
to require valid mappings. Additionally, the pin is not protected from
being remapped later by an other driver.
There is an external 1kOhms pull-up to 3.3V, so no bias is required on
the Ethernet PHY's interrupt line.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
After adding cpufreq-dt support to Exynos542x, the Odroid XU3-Lite can
be easily overheated when launching eight CPU-intensive tasks:
thermal thermal_zone3: critical temperature reached(121 C),shutting down
This seems to be specific to Odroid XU3-Lite board which officially
supports lower frequencies than regular XU3 or XU4. When working at
maximum CPU speed (1800 MHz big and 1300 MHz LITTLE) in warmer place for
longer time, the fan fails to cool down the board and it reaches
critical temperature.
Add CPU cooling to Exynos5422/5800 to fix this issue. When reaching last
interrupt-driven trip-point (70 degrees of Celsius) start passive
cooling in polling mode (slowing CPU by 2 steps). When reaching 85
degrees of Celsius, start slowing even more, down to 600 MHz.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE
and 18 steps for big core (200-1700 MHz). Add respective cooling cells.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and
12 steps for big core (700-1800 MHz). Add respective cooling cells.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Add hwmod data for the eDMA blocks:
- TPCC: Third-party channel controller
- TPTC0: Third-party transfer controller 0
- TPTC1: Third-party transfer controller 1
The TPCC's clock gating status follows the status of its clock and
power domain. This means that the hwmod code can not directly control
the TPCC enable/disable status.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[paul@pwsan.com: rephrased last two sentences of the patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This is a minor cycle with :
- cleanup fixes from Arnd, mainly build oriented and sparse type ones
- dma fixes for requestors above 32 (impacting mainly camera driver)
- some minor cleanup on pxa3xx device-tree side
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0Y3SAAoJEAP2et0duMsSfesQAIGKccj/WRWtlCxje+8Aj3UW
eu6vV9xGVBZu0RJxCchwCBP5ZO8WSvXBYvX5MIaBH2TFdJqJEjie6ES4mRlGVuup
XMUZybcFOu9N5j0WMddj2OHhEeYGgMsSZwSOgK4nsQ/eyhrcI5fjykdafmPKywjW
+/USV90ucVp+38C+yg4yXSuI8FOEABIn6VoX//+YpDZetvIoJCUQne1g+uPE2YoF
dcPqVbY2OeAvuABkI3Wqdrc3Ico9i8Ns8erg8EuDe5xv2TvJXhn/mIeoVNZ2s4So
5aCD87RQu3rwDfqAv6FzW06k9AYAE/p/VKh0smI12D8MCxhSD0EZP+jBfDvuwx/n
IICMH7YuunRSRe7VDFgWyIz7wduHQu3xctF9scSYZD+kBpvAD274sZs9WYs4fGd6
hXxxV4iXrP8af6A+sddDeo0Gq25jC7JoL43YlQTUzBMqbrzK4W3c0dXCib6hh/eN
W/YVdPERGs9cTG/IZFbn3cn1QIYdA4exNoE38txWkKpeiVxu0tZKSsg6m9xCPu7+
vMQj1m8E8mkgiMq0BJnei02QC8Xw5ekf4wNUsLOOou29c7CTt3zicM8YtnDmANV2
fIIT4BK0izIZj4N0RZp9KT6h/IkF1VHRz3pcw3vYXJLbaKqHk/6doDUW30E/Ol1f
PzJedKaWujhOV1DG1SLb
=lBYC
-----END PGP SIGNATURE-----
Merge tag 'pxa-for-4.6' of https://github.com/rjarzmik/linux into next/soc
Merge "pxa changes for v4.6 cycle" from Robert Jarzmik:
This is a minor cycle with :
- cleanup fixes from Arnd, mainly build oriented and sparse type ones
- dma fixes for requestors above 32 (impacting mainly camera driver)
- some minor cleanup on pxa3xx device-tree side
* tag 'pxa-for-4.6' of https://github.com/rjarzmik/linux:
dmaengine: pxa_dma: fix the maximum requestor line
ARM: pxa: add the number of DMA requestor lines
dmaengine: mmp-pdma: add number of requestors
dma: mmp_pdma: Add the #dma-requests DT property documentation
ARM: pxa: pxa3xx device-tree support cleanup
ARM: pxa: don't select RFKILL if CONFIG_NET is disabled
ARM: pxa: fix building without IWMMXT
ARM: pxa: move extern declarations to pm.h
ARM: pxa: always select one of the two CPU types
ARM: pxa: don't select GPIO_SYSFS for MIOA701
ARM: pxa: mark unused eseries code as __maybe_unused
ARM: pxa: mark spitz_card_pwr_ctrl as __maybe_unused
ARM: pxa: define clock registers as __iomem
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
ehrpwm functional clock derived from the gateable interface and
functional clock of PWMSS(l4_root_clk_div).
Refer AM57x TRM SPRUHZ6[1], October 2014, Table 29-4 and Section 29.2.2.1,
Table 29-19 and the NOTE at the end of the table.
[1] www.ti.com/lit/ug/spruhz6/spruhz6.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- a single fix for nand dmaengine node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0aHhAAoJEAP2et0duMsS3scP/R9XbJvMbMEXNw3gODLHFGHa
65GBlWTx4cB0zkOdOt3nO/NAKqwTyB9q1+7Pz7D0ujy9ASlomVU+GNbX/J78pBDD
2uOS6PcHfgUMQ6/FjfwIe8FS3jIAcZMXcVyyuzV4x2uWPCBlL5tisQles8kcPo+d
WRYiizsBuh0wH+qfav0jdUUiKSHhI/MPhxoRg16YqNK01zcTz7GA18HerjnNLk91
Ak2NDFBy9PN8fukrGcTqSE6Aree0wdWPOYi4PPDvNmujoEKz8S2ayoVw2yYp6Sn1
OmyMy8JOoB2I3BCG2LdKw6b3ZnBhBEPUOFbHf7c/E8bQXJlhZXwB2pYAAydnUmgm
GBKt6y/gn50NqR5X2ikn9+NNlzW9QLxd5x2gsky1QYy/akeNqR8eg1+OULv2p2pW
HgsolSTpOOGM7YtH6ihngs8xYUira6kQ41MRfhkE6Tx4t+vua4MQUV3gn+bMXzRN
9j46zgmqkKO33NCbKSXcH5pz36J/kONFT5zExH2q2MJocuN9KZw30mmngkxJiwtq
lddZxDYGQ6fTDvi3dL0YoR8X3tns4xUrM9FsONFUBH5r7dhROpMtKfQTxzYaFLgW
S0kpXjItvGCqhQOT1an/lKW0I6+Y0oJglQnobsrxJHte2RRGwwUtI/A1vgvUGB9o
9dPX01NV+7wFsOVyuKbi
=4uk1
-----END PGP SIGNATURE-----
Merge tag 'pxa-dt-4.6' of https://github.com/rjarzmik/linux into next/dt
Merge pxa dt for v4.6 from Robert Jarzmik:
This device-tree pxa update brings :
- a single fix for nand dmaengine node
* tag 'pxa-dt-4.6' of https://github.com/rjarzmik/linux:
ARM: dts: pxa: fix dma engine node to pxa3xx-nand
Quite a few changes, among which:
- Support for the A83t
- Support for the eMMC DDR on a few boards
- Support for the OTG controller on a few boards
- New boards: Itead Ibox, Cubietruck plus, Homlet v2, Lamobo R1
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0KoYAAoJEBx+YmzsjxAgV9UP/1VVx1sWS1CgZ3tPdHMlznM+
l5ehkZXHg3rATh3bM+j9HXv5j158Jiq5Hhx+XQ2/xM+dM3iuNRsszhG9RwN9uWMg
LnYbxSQ65kdf2rSysQNn+7FQjZU4d5Lt6nkAuLyLH/1g6Vqz8CERhEhFOV63q+i2
s5W7yaLe5QyqlCBQ9wXCC9ZbPBzUPAggrHSuQlSkIK5GAVBcgzCuZFEwj+NCgCSt
VXOF9tPU64CREsKcMKhC8TIltc91d2A9xEVQuLxHDk7ywD81fOnjNfmiFbklQHr+
AfzKR0REJLP3T8hKBkbAxNbiKhiHDJ6xDSb/a7DbVELMf03U4VtUH17CnCE4ZNdb
fEIcddLoTJc76tlePlBFVNblC8+/Feefw5SrkwYjhd/gP46uy8MP+3RS+8MluXih
uNucj+Ge03qztYR4RatG154qeAkuolzLNXxDOtp45d6KhqG8E1lVVOSXr+d1dSiU
GF0sl84ZtlWqIKs7Vo1Oss1W7vdUAOLrzUOQt8077uGHo/EatPRwoUQ7nKAy2rne
evCDJl0f3VknxG+BSdky0I7NVvmJy/mWHRLXdxV9AOx1RPfNWxgUZNVKhJLLqNhv
2fut4C31t/CHwrD8XsxaCAHfcwXLIOaJBak/9QGh9pJK4+RkQ2JaTvbgnAEsCth/
+vt04W2rK4secDExX21A
=CJtp
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt
Merge "Allwinner DT Additions for 4.6" from Maxime Ripard:
Quite a few changes, among which:
- Support for the A83t
- Support for the eMMC DDR on a few boards
- Support for the OTG controller on a few boards
- New boards: Itead Ibox, Cubietruck plus, Homlet v2, Lamobo R1
* tag 'sunxi-dt-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (34 commits)
ARM: dts: sun8i: Add leds and switch on Orangepi Plus boards
ARM: dts: sun8i: Add ir receiver nodes to H3 dtsi
ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
dts: sun8i-h3: Add APB0 related clocks and resets
ARM: dts: sun7i: Add dts file for the lamobo-r1 board
ARM: dts: sun4i: Enable USB DRC on Hyundai-a7hd
ARM: dts: sun4i: Enable USB DRC on the MK802
ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes
ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes
ARM: dts: sun7i: Enable USB DRC on Olimex A20 EVB
ARM: dts: sun7i: Enable USB DRC on MK808C
ARM: dts: sunxi: Fix #interrupt-cells for PIO in H3
ARM: dts: sun8i-a83t: Correct low speed oscillator clocks
ARM: dts: sun9i: a80-optimus: Remove i2c3 and uart4
ARM: dts: sun4i: Itead Iteaduino to use common code
ARM: dts: sun7i: Add Itead Ibox support
ARM: dts: sunxi: Add sunxi-itead-core-common.dtsi
ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC
ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC
ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins
...
A bunch of changes to add new drivers to the sunxi and multi_v7 defconfigs,
most notably the USB OTG that is finally enabled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0J8dAAoJEBx+YmzsjxAgqlMP/1a2IaPeM5bYb/Enu2Creqod
+mc03J1xYBVTLqXnELX6j7ydxVa0ZknQlbMQV7FiQ6icdaS+KwK6vx7kGTogEXtr
ZxwNsTlW/n948ewr6snZlkXzdPORp2t6UKfgjJwo2UtITcPTBTUxItUZpssqNZ8B
T79S0v1YJkdHb5ulcii8SzgwyE8Gs55KnCddbCE3h59sqb0mNEOz7sdOg94JlR9Q
nM+JtoKPSiG9yHUaC+/Rpad02Ahr0735acD58nSUIteNHMdqAqFB7UKGkYp5NoT0
B1A9+5nSysDi/kynP7luHhBwNGieXfN+1z6Kfl1nl2kvJAOSDZM32b0pLMZ9FaXq
Oo2kykr5OLwNiZdPWpuU80a8lfH9zyVK61wJdnxn7Fdwy7fToHMgXdEZxDXnTI6K
FZHab6diaKb+Ob+ke14ZVqNZL6bLc0Ffjbha5jWpxOsroFNHMjzmY8Wn2x74BEDv
X7e8jxkyzUPy3MrIQ5NuT7fIhmj6NurBpcJ9+6URBUbkXpJ7zK50H1eyLiJh+6yk
uRIVYq0unLF27zcn/zrnePSLQkq6/pfdT3DS7qNZaAXnx0y8+Ij7UjvM+65BIe9s
uW+NnkGBchRbWFGXxvkLldFrUEsQrouSqdpEgGmOVub2evlnwnEVqeyJ3ar1QC4B
Odw0PD0tB9xYI/YQ/flR
=6Cse
-----END PGP SIGNATURE-----
Merge tag 'sunxi-defconfig-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/defconfig
Merge "Allwinner defconfig changes for 4.6" from Maxime Ripard:
A bunch of changes to add new drivers to the sunxi and multi_v7 defconfigs,
most notably the USB OTG that is finally enabled.
* tag 'sunxi-defconfig-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi_defconfig: Enable MUSB HDRC driver with Allwinner glue
ARM: multi_v7_defconfig: Enable A10 audio codec driver as module
ARM: multi_v7_defconfig: Enable MUSB HDRC driver with Allwinner glue
ARM: sunxi_defconfig: Enable INPUT_EVDEV so axp20x-pek can be used
ARM: sunxi_defconfig: Enable A10 audio codec driver
ARM: sunxi_defconfig: Enable sunxi IR driver
Just introduce the A83T support.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0J4RAAoJEBx+YmzsjxAglusP/AzXzEt4riBOkm9lj+bfBWGq
oP+Mnws/ySwqeLuEIeWRyICBm4BUvOgJKNBhE8ZOw3BnRFyUPyklw6B8NFSoWdZq
rBXtZ8sozfo3ru265PiftJxq7ZDTEk4N5Q3VhBqsv3iC0vCqdXNZipPW0bb/1LUW
thTvwuQnihnflLzsCRrRUcUEpyhbtX6vyu4DIGYdDtzRHyU/eo0rN2B+Mjs/9zA2
KqpWslopnk+hwaLSr5kF+7hSnmraQPhXHM+KlaMHkr6zxLpk4VA7bhNZ/DpzVRY9
w9uIoKDwFp8ErEiVyL3ID8Ce/NfWRVnjxKNKKDinxuzzc5gTHiji8dfjxi19BMYP
yeXfLwHw/stqwTpA7bii20F8VN/GwM7/wxNXdf0aDZRi2guM8S28Zqh0DiqnYwRU
lpszXBe3+4xjZs32fze/R2CPAlaF5LGYYj7z4n/EVHhuvV70IrTmNj8xcOi6Zhx3
BBSCp9SV9YX+f+xKpLJjcrSqE/RX5mJxfrwSGb4Kp75ISQQL4r1gijbExP+/O/sy
1ow3jfImCEB1owD9cjwPoEy0Ajt7GSkO1iryp0C0VZkeSNUqLHZIO/qYpZfVqRN0
Ukprvi45ly0ieojmcrbbWjq/kMiVoH6mye5tQ34Gfd3RJsSS1FNTF6AO2k8dg4xm
28VetJwcSY1lrttURUw0
=7u3U
-----END PGP SIGNATURE-----
Merge tag 'sunxi-core-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc
Merge "Allwinner core changes for 4.6" from Maxime Ripard:
Just introduce the A83T support.
* tag 'sunxi-core-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Introduce Allwinner for A83T support
DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
represent this in memory dt node, the address-cells and size cells
should be 2. So, changing the address-cells and size-cells to 2 and
updating the memory nodes accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
enable SRAM support in mvebu_v7_defconfig
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQXRoACgkQCwYYjhRyO9XuDwCggDihNDvg28PdaATDslAWggt0
uJoAoIZioUyUwXZ2a0artKxtvxgBXme0
=+WFN
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig-4.6-2' of git://git.infradead.org/linux-mvebu into next/defconfig
Merge "mvebu defconfig for 4.6 (part 2)" from Gregory CLEMENT:
enable SRAM support in mvebu_v7_defconfig
* tag 'mvebu-defconfig-4.6-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: enable SRAM support in mvebu_v7_defconfig
The LP872x regulator is used in the LG Optimus Black codename sniper to supply
the external mmc card.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- Reorder Ethernet node on Armada 38x SoCs
- Add device tree for buffalo linkstation ls-gl
- Use the more accurate armada-370-sata string for SATA on Armada 375
- Add NAND description to Armada 370 DB and Armada XP DB
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQXKwACgkQCwYYjhRyO9VVYwCgpjGDDOuqbNWtj5NI3TS9gHsI
FLkAn1kS66eVLwf+0ptrOtu8nsu9mLql
=O+/a
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.6-2' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu dt for 4.6 (part 2)" from Gregory CLEMENT:
- Reorder Ethernet node on Armada 38x SoCs
- Add device tree for buffalo linkstation ls-gl
- Use the more accurate armada-370-sata string for SATA on Armada 375
- Add NAND description to Armada 370 DB and Armada XP DB
* tag 'mvebu-dt-4.6-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: mvebu: add NAND description to Armada 370 DB and Armada XP DB
ARM: dts: armada-375: use armada-370-sata for SATA
ARM: dts: orion5x: add device tree for buffalo linkstation ls-gl
ARM: dts: orion5x: split linkstation lswtgl into common and device parts
ARM: dts: armada-38x: add reference to ETH connectors for A385-AP
ARM: dts: armada-38x: change order of ethernet DT nodes on Armada 38x
ARM: dts: orion5x: fix the missing mtd flash on linkstation lswtgl
ARM: dts: kirkwood: use unique machine name for ds112
randconfig warning fixes for mvebu SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQWXIACgkQCwYYjhRyO9WZUACgp08rrriNCYNTuR0KWkcus/T2
nX8AnRkwtcKvFO3dYGw6plWxMUFIyk5E
=n4KR
-----END PGP SIGNATURE-----
Merge tag 'mvebu-soc-4.6-1' of git://git.infradead.org/linux-mvebu into next/fixes-non-critical
Merge "mvebu soc for 4.6 (part 1)" from Gregory CLEMENT:
randconfig warning fixes for mvebu SoCs
* tag 'mvebu-soc-4.6-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: mark mvebu_hwcc_pci_nb as __maybe_unused
ARM: mv78xx0: avoid unused function warning
ARM: orion: only select I2C_BOARDINFO when using I2C
Add a missing call to of_node_put() armada_xp_smp_prepare_cpus()
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQWGcACgkQCwYYjhRyO9XC3QCfQRlD4Is9IhQPmFnQ7d48TixY
k2IAn3OX5cNsG0dUzUJ8EOOTDEOLqBvV
=8cY9
-----END PGP SIGNATURE-----
Merge tag 'mvebu-cleanup-4.6-2' of git://git.infradead.org/linux-mvebu into next/cleanup
Merge "mvebu cleanup for 4.6 (part 2)" from Gregory CLEMENT:
Add a missing call to of_node_put() armada_xp_smp_prepare_cpus()
* tag 'mvebu-cleanup-4.6-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add missing of_node_put()
The LP872x regulator is used in the LG Optimus Black codename sniper to supply
the external mmc card.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds support for USB OTG on the Optimus Black.
The HSUSB0 interface is connected to the TWL4030 USB PHY.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The LG Optimus Black codename sniper is a smartphone that was designed and
manufactured by LG Electronics (LGE) and released back in 2011.
It is using an OMAP3630 SoC, GP version.
This adds devicetree support for the device, with only a few basic features
supported, such as debug uart, i2c, internal emmc and external mmc.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Programming the active state in the (re)distributor can be an
expensive operation so it makes some sense to try and reduce
the number of accesses as much as possible. So far, we
program the active state on each VM entry, but there is some
opportunity to do less.
An obvious solution is to cache the active state in memory,
and only program it in the HW when conditions change. But
because the HW can also change things under our feet (the active
state can transition from 1 to 0 when the guest does an EOI),
some precautions have to be taken, which amount to only caching
an "inactive" state, and always programing it otherwise.
With this in place, we observe a reduction of around 700 cycles
on a 2GHz GICv2 platform for a NULL hypercall.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Doing a linear search is a bit silly when we can do a binary search.
Not that we trap that so many things that it has become a burden yet,
but it makes sense to align it with the arm64 code.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
As we're going to play some tricks on the struct coproc_reg,
make sure its 64bit indicator field matches that of coproc_params.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Since we're obviously terrible at sorting the CP tables, make sure
we're going to do it properly (or fail to boot). arm64 has had the
same mechanism for a while, and nobody ever broke it...
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Not having the invariant table properly sorted is an oddity, and
may get in the way of future optimisations. Let's fix it.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
To configure the virtual PMUv3 overflow interrupt number, we use the
vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ
attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group.
After configuring the PMUv3, call the vcpu ioctl with attribute
KVM_ARM_VCPU_PMU_V3_INIT to initialize the PMUv3.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In some cases it needs to get/set attributes specific to a vcpu and so
needs something else than ONE_REG.
Let's copy the KVM_DEVICE approach, and define the respective ioctls
for the vcpu file descriptor.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
interrupt.
On VM entry, if there is counter overflowed and interrupt level is
changed, inject the interrupt with corresponding level. On VM exit, sync
the interrupt level as well if it has been changed.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Using the common HYP timer code is a bit more tricky, since we
use system register names. Nothing a set of macros cannot
work around...
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
No need to keep our own private version, the common one is
strictly identical.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In order to be able to use the code located in virt/kvm/arm/hyp,
we need to make the global hyp.h file accessible from include/asm,
similar to what we did for arm64.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
With the kernel running at EL2, there is no point trying to
configure page tables for HYP, as the kernel is already mapped.
Take this opportunity to refactor the whole init a bit, allowing
the various parts of the hypervisor bringup to be split across
multiple functions.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
With ARMv8.1 VHE extension, it will be possible to run the kernel
at EL2 (aka HYP mode). In order for the kernel to easily find out
where it is running, add a new predicate that returns whether or
not the kernel is in HYP mode.
For completeness, the 32bit code also get such a predicate (always
returning false) so that code common to both architecture (timers,
KVM) can use it transparently.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
So far, our handling of cache maintenance by VA has been pretty
simple: Either the access is in the guest RAM and generates a S2
fault, which results in the page being mapped RW, or we go down
the io_mem_abort() path, and nuke the guest.
The first one is fine, but the second one is extremely weird.
Treating the CM as an I/O is wrong, and nothing in the ARM ARM
indicates that we should generate a fault for something that
cannot end-up in the cache anyway (even if the guest maps it,
it will keep on faulting at stage-2 for emulation).
So let's just skip this instruction, and let the guest get away
with it.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
I have no idea what these were for - probably a leftover from an
early implementation. Good bye!
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
These are now handled as a panic, so there is little point in
keeping them around.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This field was never populated, and the panic code already
does something similar. Delete the related code.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Since we don't have much assembler left, most of the KVM stuff
in asm-offsets.c is now superfluous. Let's get rid of it.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Just like on arm64, having the CP15 registers expressed as a set
of #defines has been very conflict-prone. Let's turn it into an
enum, which should make it more manageable.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Now that the old code is long gone, we can remove all the weak
attributes, as there is only one version of the code.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
As we now have hooks to setup VTCR from C code, let's drop the
original VTCR setup and reimplement it as part of the HYP code.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
As we now have a full reimplementation of the world switch, it is
time to kiss the old stuff goodbye. I'm not sure we'll miss it.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Having u64 as the kvm_call_hyp return type is problematic, as
it forces all kind of tricks for the return values from HYP
to be promoted to 64bit (LE has the LSB in r0, and BE has them
in r1).
Since the only user of the return value is perfectly happy with
a 32bit value, let's make kvm_call_hyp return an unsigned long,
which is 32bit on ARM.
This solves yet another headache.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Instead of spinning forever, let's "properly" handle any unexpected
exception ("properly" meaning "print a spat on the console and die").
This has proved useful quite a few times...
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This part is almost entierely borrowed from the existing code, just
slightly simplifying the HYP function call (as we now save SPSR_hyp
in the world switch).
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
On guest exit, we must take care of populating our fault data
structure so that the host code can handle it. This includes
resolving the IPA for permission faults, which can result in
restarting the guest.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The new world switch implementation is modeled after the arm64 one,
calling the various save/restore functions in turn, and having as
little state as possible.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Similar to the arm64 version, add the code that deals with VFP traps,
re-enabling VFP, save/restoring the registers and resuming the guest.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Add the very minimal piece of code that is now required to jump
into the guest (and return from it). This code is only concerned
with save/restoring the USR registers (r0-r12+lr for the guest,
r4-r12+lr for the host), as everything else is dealt with in C
(VFP is another matter though).
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Banked registers are one of the many perks of the 32bit architecture,
and the world switch needs to cope with it.
This requires some "special" accessors, as these are not accessed
using a standard coprocessor instruction.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This is almost a copy/paste of the existing version, with a couple
of subtle differences:
- Only write to FPEXC once on the save path
- Add an isb when enabling VFP access
The patch also defines a few sysreg accessors and a __vfp_enabled
predicate that test the VFP trapping state.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This patch shouldn't exist, as we should be able to reuse the
arm64 version for free. I'll get there eventually, but in the
meantime I need an interrupt controller.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This patch shouldn't exist, as we should be able to reuse the
arm64 version for free. I'll get there eventually, but in the
meantime I need a timer ticking.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Concert the CP15 save/restore code to C.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In order to move system register (CP15, mostly) access to C code,
add a few macros to facilitate this, and minimize the difference
between 32 and 64bit CP15 registers.
This will get heavily used in the following patches.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In order to expose the various HYP services that are private to
the hypervisor, add a new hyp.h file.
So far, it only contains mundane things such as section annotation
and VA manipulation.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Continuing our rework of the CPU context, we now move the GP
registers into the CPU context structure.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Continuing our rework of the CPU context, we now move the CP15
array into the CPU context structure. As this causes quite a bit
of churn, we introduce the vcpu_cp15() macro that abstract the
location of the actual array. This will probably help next time
we have to revisit that code.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In order to turn the WS code into something that looks a bit
more like the arm64 version, move the VFP registers into a
CPU context container for both the host and the guest.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Now that we've unified the way we refer to the HYP text between
arm and arm64, drop __kvm_hyp_code_start/end, and just use the
__hyp_text_start/end symbols.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In order to be able to spread the HYP code into multiple compilation
units, adopt a layout similar to that of arm64:
- the HYP text is emited in its own section (.hyp.text)
- two linker generated symbols are use to identify the boundaries
of that section
No functionnal change.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
As we're about to move the stage2 init to C code, introduce some
C hooks that will later be populated with arch-specific implementations.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Calling return copy_to_user(...) in an ioctl will not
do the right thing if there's a pagefault:
copy_to_user returns the number of bytes not copied
in this case.
Fix up kvm to do
return copy_to_user(...)) ? -EFAULT : 0;
everywhere.
Cc: stable@vger.kernel.org
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Add a device tree node entry for DAC peripheral on Vybrid SoC.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The backlinks are already there since commit 4520e69238 ("ARM: dts:
imx6qdl: Add IPU DI ports and endpoints, move imx-drm node to dtsi")
and were moved by commit 70c2652c6c ("ARM: dts: imx6qdl: Move existing
MIPI DSI ports into a new 'ports' node"), but the links from IPU2 DI0/1
to the MIPI DSI mux are missing. Fix this.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Advantech has 3 carrier boards (B450v3, B650v3, B850v3) which use
the Advantech BA-16 module (based on iMX6D). This file has the
devicetree entries that are common to all 3 boards.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
For imx35, it needs three clocks to let the controller work,
the old code is wrong, and the usbmisc does not include
clock handling code any more.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
For imx25, it needs three clocks to let the controller work,
the old code is wrong, and usbmisc has not included clock
handling code any more.
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds the device node for the i.MX6UL keypad controller.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the device node for the i.MX6UL GPMI interface and the related
APBH DMA which is necessary for the GPMI to work properly.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add device nodes for the PWM uinits 1..4 which were missing in the
original commit for i.MX6UL support.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Since PWMs are only useful if they are actually connected to an output pin,
let users enable them explicitly in their device trees where they should
also set up the pin configuration. This is in sync with a recent change
(commit e2675266b3 "ARM: dts: imx6qdl: disable PWMs by default")
to other i.MX SoCs.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX6UL GPT unit requires real clocks. Define the appropriate
clocks to make it work.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx6ul.dtsi references the macro 'KEY_POWER' from
dt-bindings/input/input.h. Thus, move the include statement for this
file from imx6ul-14x14-evk.dts to imx6ul.dtsi itself.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Move the tsc node to keep the nodes sorted in ascending order by unit
address.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Pad DISPB2_SER_RS has no function DISP1_EXT_CLK.
The definition is obviusly a copy/paste error from
MX51_PAD_DISPB2_SER_RS__DISP1_PIN16.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Various pads are missing the input_sel offset and value. Fix this.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
All Freescale Vybrid SoC include a Cortex-A5 core which supports
ARM's standard PMU (performance monitoring unit). Include the
monitoring unit into the Cortex-A5 base device tree vf500.dtsi.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Colibri standard does not define a pin for SD-Card write-
protection. Use the disable-wp property to indicate that there
is no physical WP line present.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to the reference manual the shp_2_mcu / mcu_2_shp
scripts must be used for devices connected through the SPBA.
This fixes an issue we saw with DMA transfers from SPI NOR Flashes.
Sometimes the SPI controller RX FIFO was not empty after a DMA
transfer and the driver got stuck in the next PIO transfer when
it read one word more than expected.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the carrier boards 3.3V supply as fixed regulator. This allows
to specify the power supply for nodes like backlight.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Colibri modules need to be powered using the power pins 3V3 and
AVDD_AUDIO. Add fixed regulators which represent this power rails.
Potentially, those power rails could be switched on a carrier
board. A carrier board device tree could add a own regulator with
a GPIO, and reference that regulator in a vin-supply property of
those new module level system regulators.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Drop the fake simple-bus container 'regulators' and put the
regulators directly under the root node. This also makes the
artificial 'reg' properties superfluous. While at it, remove
the unnecessary regulator-always-on property and name the
regulators according to schematics.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Assign Ethernet clock parents explicitly. The Colibri VF61
uses the 50MHz Ethernet clock provided by PLL5.
The Vybrid SoC has two ethernet interfaces (fec0 and fec1) which
use the same clock source (VF610_CLK_ENET). Therefore this parent
configuration affects multiple consumer devices and need to be
specified in the clock provider node.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Assign Ethernet clock parents explicitly. The VF610 Tower Board
uses the external Ethernet clock input which is connected to
a 50MHz clock.
The Vybrid SoC has two ethernet interfaces (fec0 and fec1) which
use the same clock source (VF610_CLK_ENET). Therefore this parent
configuration affects multiple consumer devices and need to be
specified in the clock provider node.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
