We should be able to talk to the PMIC at 400kHz. No need to talk at
the slow 100kHz.
As measured by ftrace (with a bunch of extra patches, since cpufreq
for rk808 hasn't landed yet):
before this change: cpu0_set_target() => ~500us
after this change: cpu0_set_target() => ~300us
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by Addy Ke <addy.ke@rock-chips.com>
Tested-by Addy Ke <addy.ke@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
All the current support of mach-mxt_td60 board can be converted to devicetree.
Remove the board file.
Cc: Alan Carvalho de Assis <acassis@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Currently there is a wild mixture of isl, isil, and intersil
compatibles in the kernel. At this point, changing the vendor
symbol to the most often used variant, which is equal to the
NASDAQ symbol, isil, should not hurt.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lkml.kernel.org/r/1410167960-554-4-git-send-email-p.zabel@pengutronix.de
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Switch the Armada SoC SPI port device tree binding to use the new improved
armada-370-spi compatible name. This allows for a wider range of baud rates
to be used.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1410147029-30067-1-git-send-email-gerg@uclinux.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 SoC has a Spread Spectrum Clock Generator. This commit
adds the description of this generator to the Device Tree describing
this SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-4-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJUCIKhAAoJEBmUBAuBoyj0MJUQAIPVfnuSzBlNru29jf0qJ4wp
XKcHm/TWm17/ZFTpA/m2UwTpvPSztK+JSYWH2xM6Ks6bQhbhyLKe6SZHaYbeHVRr
xPuUU2idHjSXKg/MqlKWZIABj+jyoP3f7xvHvXalmj48ZAZtJoCrXdmMjG1lTA69
jbS1FM6EcNORXxPVc8KdGeFvlj47LOFVXv0Em4huWb1U6tqurgs4RVwkhYdTCmfj
DG59pf4SK+4P3r4GZSBtm47CKbIFfNEzdz7wy5Iq+RvJ5/hBmhbDp6TB9EgWL1Mo
xnsMuvASE4FQq5aefWDR4+d/Arrhovp8DNiRmPNWA/tWlx0AfMJ7rnaPvk3/RnkY
YqHoE5CGWbbtK7L+9NQt6ENW0fJDSc6006k0Uzyfty4mIi4YAEhqQ7rvxLWfH+TK
6iyZUOfWT+0hLPX8XhCvIQYUqvkq9EYm5DrENxYW2U6ePU5jjYuZ1mdoTkiKMFTe
9SQCTYrdGsRMJ+I7qyiHFR931cJoWe8hA7HSZ3iYGvjFReWwfNQ8e9J1rVu++J5Y
qopDz/E6jptlx6/aDPI4wtU/5P3NDH/olVmhrahy9XJITJ22474AlhzVMOp8pIrY
jnypiuX36z5sai2U/2eD4ltZh8hChDEZEM7bMsH+wlP4jnLxcep4oSlzh6HsOMu1
nPxXHMfUOsnfuZwUuzmm
=/AYx
-----END PGP SIGNATURE-----
Merge tag 'socfpga_update_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next into next/dt
Pull "arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries" From Dinh Nguyen:
5 of the 6 patches are DTS updates and the 1 patch is updating
the MAINTAINERS entry with my new email address.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'socfpga_update_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next:
arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.
ARM: dts: socfpga: memreserve first 4KB for future system use
ARM: dts: socfpga: Add SD card detect
ARM: dts: socfpga: remove extra alias in the ArriaV devkit
ARM: dts: socfpga: unuse the slot-node and deprecate the supports-highspeed for dw-mmc
MAINTAINERS: update entries for ARM/SOCFPGA platform
Mark rxd as wakeupcapable for 115200n8 no hardware-flow control
configuration. If h/w flow control is being used, then rts/cts
appropriately should be used.
Signed-off-by: Nishanth Menon <nm@ti.com>
We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee1786 ("pinctrl: single: Add support for wake-up interrupts")
that recently got merged. In addition to that we also needed
commit 79d9701559 ("of/irq: create interrupts-extended property")
that's now also merged.
Note that there's no longer need to specify the wake-up bit in
the pinctrl settings, the request_irq on the wake-up pin takes
care of that.
Signed-off-by: Nishanth Menon <nm@ti.com>
Now that ti,am437-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark the pinctrl as interrupt controller so that it can
be used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon <nm@ti.com>
Now that ti,dra7-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be used
with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon <nm@ti.com>
Now that ti,omap5-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be
used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon <nm@ti.com>
This adds initial support. For now, regulators are always on and we
don't specify the input supply for all of the regulators.
Signed-off-by: huang lin <hl@rock-chips.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
It's convenient (and less confusing to people reading logs) if the
eMMC port on rk3288 is consistenly marked with mmc0 and the sdmmc port
on rk3288 is consistently marked with mmc1. Add the appropriate
aliases.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds basic SPI nodes to the base rk3288 device tree file.
A few notes:
* It's assumed that most users of the SPI ports are using chip select
0. Thus the default pinctrl for the ports enables chip select 0
(but not chip select 1 on ports that have it). If a board wants to
use chip select 1 or wants a GPIO chip select the board should
override the pinctrl (just like boards can override UART pinctrl if
they have hardware flow control).
* Since SPI DMA support appears broken and the SPI works fine without
DMA we don't include the DMA references. That can come in a later
change.
Signed-off-by: huang lin <hl@rock-chips.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add regulator-name properties for the regulators that don't have them,
allowing the kernel to display the name from the schematic rather than
the name of the regulator on the PMIC in order to improve diagnostics.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
CM-T54 CoM can be used with various custom baseboards, other
than SB-T54 (supplied with SBC-T54 single board computer).
Update model property of SBC-T54 DT to clarify this.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The RFBI node for OMAP DSS was left out when adding the rest of the DSS
nodes, because it was not clear how to set up the clocks for the RFBI.
However, it seems that if there is a HWMOD for a device, we also need a
DT node for it. Otherwise, at boot, we get:
WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2542 _init+0x464/0x4e0()
omap_hwmod: dss_rfbi: doesn't have mpu register target base
Now that v3.17-rc3 contains a fix 8fd46439e1 ("ARM: dts:
omap54xx-clocks: Fix the l3 and l4 clock rates") for the L3 ICLK
required by the RFBI, let's add the RFBI node to get rid of the
warning.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
[tony@atomide.com: updated description per comments from Nishant]
Signed-off-by: Tony Lindgren <tony@atomide.com>
These baseboards are equipped with the Technexion TAO35030 SOM. So
they include this dtsi. The common parts are extracted into an "common"
dtsi file. The main difference between both boards is, that the *lcd
has DSS support enabled for the LCD.
Some HEAD acoustics specific features are:
- LED handling
- Special FPGA/DSP audio driver (not included in this series)
- powerdown GPIO
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This baseboard is equipped with the Technexion TAO35030 SOM. So
includes this dtsi. Some Thunder specific features are:
- LCD panel
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Technexion TAO3530 is a OMAP3530 based SOM. This patch adds the
basic support for it as an dtsi file which can be included by
baseboard equipped with this SOM. E.g. the Technexion Thunder
baseboard.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Set internal clock source for MMC2 on tao3530.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM57xx processor family are variants of DRA7 family of processors and
targetted at industrial and non-automotive applications.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA72x-evm uses TPS65917 PMIC. Add the node.
NOTE: LDO2 is actually unused, but the usage if any is expected to be
between 1.8 to 3.3v IO voltage. So define the node.
NOTE: Interrupt used is crossbar number based.
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I2C1 bus is used for the following peripherals
P8 connector (MLB)
TLV320AIC3106 Audio codec
J15 LCD header
24WC256 eeprom
TMP102AIDRLT temperature sensor
PCF8575 GPIO expander
PCA9306 i2c voltage translator -> Goes to P9 for comm interface
P2 expansion connector
TPS65917 PMIC
The slowest speed of all the peripherals seems to be 400KHz.
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Alexander Bersenev <bay@hackerdom.ru>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Oliver Schinagl <oliver@schinagl.nl>
Acked-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
- 2 little fixes for at91sam9x5 and at91sam9n12ek
- removal of a board specific hook for sama5d3xek about phy fixup
replaced with proper DT property definition.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJUBK3XAAoJEAf03oE53VmQl3cIAIbJ4yIfyRXrhTpLcPdt1BBi
n1WEKIMcZ8VuNt7oksbGwbJk4wOXDb1N9JDJ0UhQ9N7Kt7kCQentK6Zsx0aBwP0P
CQDKk5w8MF8n/WPDbrEe4ibzEJKzJtmnXL1GeE8vKJxj66XwRNzT/V3LROfFBbrg
eK64HX1NBVzpro5K6hfOZ7B2V0RM1sKEtgE1vLA+j3xcSpkjp2czqj7t7rehCL+d
x+iGU1Fn6VXv1KVziiVcKZs0Q+SuvH3rfKOFMFXY2judobCyVwwvI7XGZERAadhB
pDXoRzS0vMzXKx4/TaxN8lRrprzGgh0k6TWTaXD4MOKNgLD5NUfDLgw3WrpFQo0=
=fuGI
-----END PGP SIGNATURE-----
Merge tag 'at91-dt2' of git://github.com/at91linux/linux-at91 into next/dt
Pull "Second batch of AT91 DT patches for 3.18" from Nicolas Ferre:
- 2 little fixes for at91sam9x5 and at91sam9n12ek
- removal of a board specific hook for sama5d3xek about phy fixup
replaced with proper DT property definition.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-dt2' of git://github.com/at91linux/linux-at91:
ARM: at91: remove phy fixup for sama5d3xek boards
ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards
ARM: at91/dt: sam9n12ek: ohci: add port and vbus property
ARM: at91/dt: sam9x5: fix ADC compatible string
The defined mechanism for programming the Tegra pinmux is to perform all
of the following at once in order, before using any I/O controller that
is affected by the pinmux:
- Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit.
- Set up any GPIO pins to their "initial" state.
- Program all pinmux settings in one go.
Other methods such as:
- Not setting CLAMP_INPUTS_WHEN_TRISTATED.
- Not setting GPIOs to their "initial" state before programming the
pinmux settings of the related pin, in particular the mux function.
- Not programming the entire pinmux at once, in order to avoid
possible conflicting settings.
... are not qualified or supported by NVIDIA ASIC/syseng. They could
cause glitches or undesired output levels on some pins, or controller
malfunction.
While we've been getting away with doing something different on many
Tegra boards without issue, I believe we've just been getting lucky.
I'd like to switch all Tegra124 systems to the correct scheme now so
they provide the right example to follow, and require that any new
boards we support upstream work in the same fashion.
While it would be nice to update boards containing older SoCs for
consistency, I don't anticipate doing so. It's too much churn to change
at this time. At least with all Tegra124 boards converted, the most
recent boards provide the correct example.
Since the bootloader needs to reprogram the pinmux to access certain
peripherals, it must program the entire pinmux due to the supported
rules above. As such, there is no need to program any part of the pinmux
from the kernel, unless dynamic pinmuxing is used. Given this, we couuld
simply remove the pinmux "default" state from the DT entirely. However,
some bootloaders parse the DT to perform their initial pinmux setup, so
it's useful to keep the pinmux data in DT. To allow this while avoiding
redundant work in the kernel, rename the "default" state to "boot". The
kernel won't apply this, but bootloaders can still look for this state
name and apply it. Note however that the DT provides zero information
about the required initial GPIO setup, so bootloaders using this approach
are not likely to operate correctly without an additional GPIO
initialization table somewhere. Previous discussions on the DT mailing
list have rejected adding such a table to DT...
The following U-Boot commits fully initialize the pinmux:
Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1
Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates
Both are part of U-Boot v2014.07 and later.
Without those commits, the only fallout I see from this change is that
HDMI on Venice2 no longer works. Given the very small user-base of this
platform, I feel that requiring a bootloader update is reasonable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
processor and is similar to the Venice2 reference platform.
The keyboard, USB 2, audio, sdcard and emmc have been tested
and work on the 1366x768 models. The Full HD models haven't been
tested yet.
WiFi does not yet work, it needs at least some PMIC changes to enable
the 32k clock.
The elan trackpad is not yet functional but hopefully will be soon as
there are patches under review.
There is also an issue on reboot because the TPM isn't reset. It will
cause the stock firmware to enter recovery mode. This can be worked
around by an EC-reset, press the refresh and power keys at the same
time.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
These labels will be used by other boards in addition to Venice2, move
them to tegra124.dtsi so they are defined in a common place.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]
[1] https://lkml.org/lkml/2014/7/30/514
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This patch adds a /memreserve/ section to reserve the first 4K for future
use by the system. One possible use-case is trampoline code used to bring
secondary cores online.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
---
v3: Update commit message based on Mark Rutland's comment
v2: Add a comment in the dts files
Revision D of the SOCFGPA devkit has a GPIO line used for SD/MMC card detect.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
commit [2755e187 dts: socfpga: Add DTS entry for adding the stmmac glue
layer for stmmac.] added an extra ethernet alias in the ArriaV devkit
board file. This patch removes it.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
dw-mmc
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And "supports-highspeed" property in dw-mmc is deprecated.
"supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tushar Behera <trblinux@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The base address of the second memory region on the lager
board is 0x140000000. Update the tag used in the dts file accordingly.
This is a documentation fix and should have no run-time affect.
This problem was introduced when the second memory region
was added to the lager dts file by 62bc32a257
("ARM: shmobile: Include all 4 GiB of memory on Lager)"
in v3.14.
Reported-by: NAOYA SHIIBA <naoya.shiiba.nx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Venice2 contains an Atmel MXT touchpad. Add an I2C node for it to DT.
The Linux driver doesn't quite work on this platform yet, but adding
the DT node causes no issues, and will allow the device to work once
the driver is fixed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add both the cpu and peripheral pl330 dma controllers present in rk3188 socs.
The first dma controller can change between secure and non-secure mode. Both
instances are added but the non-secure variant is left disabled by default,
as on the majority of boards the bootloader leaves it in secure mode.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add both the bus and peripheral pl330 dma controllers present in rk3288 socs.
The first dma controller can change between secure and non-secure mode. Both
instances are added but the non-secure variant is left disabled by default,
as on the majority of boards the bootloader leaves it in secure mode.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
This is needed to access the pl330 dma controllers on Rockchip SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Add the DMA configuration for USARTs mainly because it is not obvious to
add the FIFO flag which is needed for rx.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Checkpatch says:
ERROR: code indent should use tabs where possible
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Checkpatch says:
ERROR: code indent should use tabs where possible
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
These board specific delays are now configured through micrel's specific
DT bindings (see Documentation/devicetree/bindings/net/micrel-ksz9021.txt).
Remove this phy fixup registration from sama5 DT machine file to keep it
as generic as possible.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
and board specific timing configs.
Atmel has two different HW designs for its CPU modules: the first one
(produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up
resistor and PHYAD[1-2] to pull down resistors.
As a result, Ronetix design will have its PHY available at address 0x1 and
Embest design at 0x7.
By defining both phys we're letting the phy core detect the one actually
available on the MDIO bus.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
mx1ads.c can be replaced with devicetree equivalent: imx1-ads.dts,
so remove the board file.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This was added by:
Commit 8128c4f36 ("ARM: dts: vf610-twr: Add simple-card support.")
This useless property may cause some confusions for users.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
With commit c716483c3d ("ARM: 8122/1: smp_scu: enable SCU standby
support"), the STANDBY bit of SCU is handled by core function
scu_enable(). So imx_scu_standby_enable() can be removed now.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
pcm970-baseboard.c and mach-pcm038.c can be replaced with their
devicetree equivalents: imx27-phytec-phycore-rdk.dts and
imx27-phytec-phycore-som.dtsi respectively, so remove the board files.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
eukrea_mbimx27-baseboard.c and mach-cpuimx27.c can be replaced with their
devicetree equivalents: imx27-eukrea-mbimxsd27-baseboard.dts and
imx27-eukrea-cpuimx27.dtsi respectively, so remove the board files.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The iomux function declarations are in headers only accessible in this
directory. Thus those can't be used in any module. None of the
objects in this directory is tristate. Neither can the header be included
in out-of-tree modules.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Move the GEM's size and address cells properties to the common
dtsi file.
Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The used PHYs should be qualified as 'rgmii-id' instead of just 'rgmii'.
For the Zed board this seems to make a difference between working and
broken Ethernet.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Adds LEDs to the zc702 devicetree for use with the leds-gpio driver.
Signed-off-by: Ezra Savard <ezra.savard@xilinx.com>
Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the port number and vbus property for ohci port, or else if
bootloader won't configure the vbus pin, the 5v supply is not
power on, so can not work with usb devices.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Use the correct compatible string for the ADC of the at91sam9x5 family of SoCs.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The thermal node used the generic compatible property only.
Add the SoC-specific one, to make it future proof.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The thermal node used the generic compatible property only.
Add the SoC-specific one, to make it future proof.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Pull ARM fixes from Russell King:
"Various assorted fixes:
- a couple of patches from Mark Rutland to resolve an errata with
Cortex-A15 CPUs.
- fix cpuidle for the CPU part ID changes in the last merge window
- add support for a relocation which ARM binutils is generating in
some circumstances"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8130/1: cpuidle/cpuidle-big_little: fix reading cpu id part number
ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex
ARM: 8128/1: abort: don't clear the exclusive monitors
ARM: 8127/1: module: add support for R_ARM_TARGET1 relocations
Here's the weekly batch of fixes from arm-soc.
The delta is a largeish negative delta, due to revert of SMP support for Broadcom's
STB SoC -- it was accidentally merged before some issues had been addressed, so they
will make a new attempt for 3.18. I didn't see a need for a full revert of the whole
platform due to this, we're keeping the rest enabled.
The rest is mostly:
* A handful of DT fixes for i.MX (Hummingboard/Cubox-i in particular)
* Some MTD/NAND fixes for OMAP
* Minor DT fixes for shmobile
* Warning fix for UP builds on vexpress/spc
There's also a couple of patches that wires up hwmod on TI's DRA7 SoC
so it can boot. Drivers and the rest had landed for 3.17, and it's small
and isolated so it made sense to pick up now even if it's not a bugfix.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJUA1uwAAoJEIwa5zzehBx3dV8QAJv/6OcFofqWPqSapCdcCTkU
o9o+QxzTY4Fo4GDyTboLwvY2EE7aFKohiekKGoHHT+fXXR4n+/Xe5Dq58DijdZ0q
xUksd1h1ZuqzbWqT+1fyrlgJt3jOmQ1vzbBVpWA4tN1RUKJekU+ZF0oCAAdDwbaf
O925etd77+ij0euJ/l06fR9YUYIY23mufG+SELke5S7xS9T1sVFWcluf/z+y57qc
hxF6Uc5r4LOY4pFKYgjvsu3R7KPD4DANCiSYUvjS5sIWrJ3xenkyHVMxFEyQ5Tz+
TCrT8rXx3Ue7AlNMztY5P1dTmYftwJhWy6p/8J8UqPJ6ip633FWrhTfKHmLIR3lC
VkMYroFeg4Fp/YvFENeBe9QUbg0Xb920oZoDQA4SwkZJkQlWafYsOy4bLKSyMQGQ
nKcnyxeP2q5YaStTZMSNQ4xwT9yo3dwBllYGSbXUiTk0VJ3TX9jEMg6StvRM0YHG
sT8XKufqIAJugNZZsGtGyBLO6f8BbPVgFICvEVetgjMWHl9iGNVDbeqbYvQ6A8NL
TTqJUK7CXkNgQGX2rB7txSgR3XoaWU0rWjSnSXy2Xgtb/pd/jZYLicEY8Wd4Q1qp
Ww2misiX4viMxcD6AWiDUj1mcciSh915h1po5zZbLMTRp4qfuqh1BfSvPY/fh5DD
LKXAwm3PyL9+QrknP3//
=/AD8
-----END PGP SIGNATURE-----
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Here's the weekly batch of fixes from arm-soc.
The delta is a largeish negative delta, due to revert of SMP support
for Broadcom's STB SoC -- it was accidentally merged before some
issues had been addressed, so they will make a new attempt for 3.18.
I didn't see a need for a full revert of the whole platform due to
this, we're keeping the rest enabled.
The rest is mostly:
- a handful of DT fixes for i.MX (Hummingboard/Cubox-i in particular)
- some MTD/NAND fixes for OMAP
- minor DT fixes for shmobile
- warning fix for UP builds on vexpress/spc
There's also a couple of patches that wires up hwmod on TI's DRA7 SoC
so it can boot. Drivers and the rest had landed for 3.17, and it's
small and isolated so it made sense to pick up now even if it's not a
bugfix"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
vexpress/spc: fix a build warning on array bounds
ARM: DRA7: hwmod: Add dra74x and dra72x specific ocp interface lists
ARM: DRA7: Add support for soc_is_dra74x() and soc_is_dra72x() variants
MAINTAINERS: catch special Rockchip code locations
ARM: dts: microsom-ar8035: MDIO pad must be set open drain
ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
ARM: brcmstb: revert SMP support
ARM: OMAP2+: hwmod: Rearm wake-up interrupts for DT when MUSB is idled
ARM: dts: Enable UART wake-up events for beagleboard
ARM: dts: Remove twl6030 clk32g "regulator"
ARM: OMAP2+: omap_device: remove warning that clk alias already exists
ARM: OMAP: fix %d confusingly prefixed with 0x in format string
ARM: dts: DRA7: fix interrupt-cells for GPIO
mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc()
ARM: dts: omap3430-sdp: Revert to using software ECC for NAND
ARM: OMAP2+: GPMC: Support Software ECC scheme via DT
mtd: nand: omap: Revert to using software ECC by default
ARM: dts: hummingboard/cubox-i: change SPDIF output to be more descriptive
ARM: dts: hummingboard/cubox-i: add USB OC pinctrl configuration
ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
...
With ARCH_VEXPRESS_SPC option, kernel build has the following
warning:
arch/arm/mach-vexpress/spc.c: In function ‘ve_spc_clk_init’:
arch/arm/mach-vexpress/spc.c:431:38: warning: array subscript is below array bounds [-Warray-bounds]
struct ve_spc_opp *opps = info->opps[cluster];
^
since 'cluster' maybe '-1' in UP system. This patch does a active
checking to fix this issue.
Signed-off-by: Alex Shi <alex.shi@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
are OMAP2+ derivative SoCs. This should be low-risk to existing OMAP
platforms.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/hwmod-a-early-v3.17-rc/20140827194314/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT/saeAAoJEMePsQ0LvSpLKzgP+gK9LdsoYrsyVqDp7ZbSSzSy
scrlTlTa6iO+Et82TLDPEoWgsNb7BXSJDHWF6j5GxzSsZIM8hm2LEjvhvkf0BuHt
n8J1+uZduIZLEipBb2gLCY2td2hYrM8UUwNgLk3oFHf6uhLKrdK0WUzdBr6Aznlb
J+l42Pds2AI37tf7Fa3d1ZVEQhMrZb61g6SD77S2KdifL0rlWpE+rDaGBr71qBi5
CXibrKi2NikNGKHKdusLPCCcvo/tfpf3o32olO1W72kFbC8eTy2nZLj1qaxnLvbr
DfOzZDWEdS4I2AXrhh/EYiL298FecOtty3FX++/W2XWiM9VYq/wKYthBM/qrGous
tpnsbTEt7BhIaCwJte0xpwTeCLnke9se1aD+GptyPCOI7jQxG0CCWtd5gKeIIiEO
YrNZjjIXDOL6HZgVuETGuVf6NJYfjThZ8yglvnX6hr5awdcBao5yhb/AkdM629mB
ackueKLS0zysQo9p9LlwnqvUVU4PJHBmkyzBtUKDbv2FD/IFuvZm4ZaPR28eim+1
N17qTIdQPog2+4sxKQA96uj7n38K0UPFkgIbi7B25YFpSTPLAu4COiJeS45K8tWv
yWocbzPQPd5KVWXWxD/HfaQjKGUHbQQpNeJHn6CyQSqXTpPwzkVembC8gCL3gxed
CQaowzZfGWl0oDoLVXCy
=5ZS8
-----END PGP SIGNATURE-----
Merge tag 'for-v3.17-rc/omap-dra72x-d74x-support-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes
Pull "ARM: OMAP2+: DRA72x/DRA74x basic support" from Tony Lindgren:
Add basic subarchitecture support for the DRA72x and DRA74x. These
are OMAP2+ derivative SoCs. This should be low-risk to existing OMAP
platforms.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/hwmod-a-early-v3.17-rc/20140827194314/
* tag 'for-v3.17-rc/omap-dra72x-d74x-support-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending:
ARM: DRA7: hwmod: Add dra74x and dra72x specific ocp interface lists
ARM: DRA7: Add support for soc_is_dra74x() and soc_is_dra72x() variants
Signed-off-by: Olof Johansson <olof@lixom.net>
New system call depends on crypto. As it did not have a separate config
option, CONFIG_KEXEC was modified to select CRYPTO and CRYPTO_SHA256.
But now previous patch introduced a new config option for new syscall.
So CONFIG_KEXEC does not require crypto. Remove that dependency.
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Cc: Eric Biederman <ebiederm@xmission.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Shaun Ruffell <sruffell@digium.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This patch series updates the device tree vendor prefix for
Dialog Semiconductor.
Various methods are currently used throughout the kernel: 'diasemi',
'dialog' and 'dlg'. Others have also been suggested.
This patch set aims to consolidate the usage of the vendor prefix to
use a common standard. The prefix 'dlg' is used.
Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(and a sneaky document addition that slipped from the previous pull-request)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT/0s6AAoJEFGvii+H/HdhNiEP/R+zAKkTCmJyw2aeJR9RrNaO
Qu2rzavdCsM/DKJiEKsF0QNvyMFM3S1Tx16pnOWcsCdJI9LVgeCRv7Fpn2mJKNRI
UlmRHuG+SRu2nzr0gc+hyEOuz5VhpGemKo4tntUEPKrj5eXD25e3QgYHFIdTI32k
c/bG7eKV7LbPSrybzLNw6FNRuH0YyN667PEck1HVFerCv/921LwO4seOVPAwecgu
tELpaY7oxDTxoPe8QmxzmPWvCri1OjGaQTEfHoCWXfUaeYcOksI4mJ1zoIBZ0aHb
uSY+wVnXfkAbmz7kzcJJvVYuf4PhI0mRh2uEhpvzJxMaetAA3JVf0/JXOhTGbATK
itWgSqCVXooMf+8DIEsMkmXgqV0+Nvy0vZxv+viIdQ4ea9nUrWVT+KJmYsKp8lk9
SAXsDv+4sr3POCN4QwvAsEKmujtngkOws2YSRRZqiPw8DAiNVpjgF/bZ6jZXVvQs
wpOqGFJhwS3etyBica1hEZorhGoQzLEWgXDa+D+9jPs1TWVBJVYKeGaRFPGVZxgN
6mAObpbv0/Uc6SUUlv55qfF3A1KUE2n7001SoD7zYEcTQ9jIcqw8CgKlb4kgrROv
VeFb4wIxF6kGuijiKMZvwoH0x+QL/fXrvIVK6x8UN2Zy3+QMva+x8pu8tZQvTYun
CibJKkoCwT2dth7D9pWS
=DaB2
-----END PGP SIGNATURE-----
Merge tag 'mfd-fixes-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull mfd fixes from Lee Jones:
"Couple of simple fixes due for the 3.17 rcs
(and a sneaky document addition that slipped from the previous
pull-request)"
* tag 'mfd-fixes-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd:
mfd: twl4030-power: Fix PM idle pin configuration to not conflict with regulators
mfd: tc3589x: Add device tree bindings
mfd: ab8500-core: Use 'ifdef' for config options
mfd: htc-i2cpld: Fix %d confusingly prefixed with 0x in format string
mfd: omap-usb-host: Fix %d confusingly prefixed with 0x in format string
Commit 43fef47f94 (mfd: twl4030-power: Add a configuration to turn
off oscillator during off-idle) added support for configuring the PMIC
to cut off resources during deeper idle states to save power.
This however caused regression for n900 display power that needed the
PMIC configuration to be disabled with commit d937678ab6 (ARM: dts:
Revert enabling of twl configuration for n900).
Turns out the root cause of the problem is that we must use
TWL4030_RESCONFIG_UNDEF instead of DEV_GRP_NULL to avoid disabling
regulators that may have been enabled before the init function
for twl4030-power.c runs. With TWL4030_RESCONFIG_UNDEF we let the
regulator framework control the regulators like it should. Here we
need to only configure the sys_clken and sys_off_mode triggers for
the regulators that cannot be done by the regulator framework as
it's not running at that point.
This allows us to enable the PMIC configuration for n900.
Fixes: 43fef47f94 (mfd: twl4030-power: Add a configuration to turn off oscillator during off-idle)
Cc: stable@vger.kernel.org # v3.16
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
To deal with IPs which are specific to dra74x and dra72x, maintain seperate
ocp interface lists, while keeping the common list for all common IPs.
Move USB OTG SS4 to dra74x only list since its unavailable in
dra72x and is giving an abort during boot. The dra72x only list
is empty for now and a placeholder for future hwmod additions which
are specific to dra72x.
Fixes: d904b38df0 ("ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss")
Reported-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
[paul@pwsan.com: fixed comment style to conform with CodingStyle]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
This resolves a problem introduced by 4bfb358b1d
("ARM: shmobile: Add r8a7791 legacy SDHI clocks")
which was included in v3.15.
This fix does not have any run-time affect at this time.
* ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
This resolves a problem introduced by 9f13ee6f83
("ARM: shmobile: r8a7790: add div4 clocks")
which was included in v3.11.
This fix does not have any run-time affect at this time.
* ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name
This resolves a problem introduced by a0f7e7496d
("ARM: shmobile: sh73a0: add CMT1 clock support for DT")
which was included in v3.17-rc1.
This fix does not have any run-time affect at this time as the clock in
question is used by a SCIF device that is not enabled by default.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT+oE/AAoJENfPZGlqN0++6eYQAK8LStttSbAjBHONrCQpj1/n
fBu+S9RjzYOKLtG4L7pVXOJSFuIiPB03y4IeiFRflIS6TQyopl7DmTZvN/AztIjE
dOamQ+Z2ePrLcNUG1ZNfpEUSxfImOqtcm38R58HRDOnMYTszLOaVxtU0Dre9Y3Me
cYHEN/17PUQWdQ7j5tcaDwXtl4oVjS+1RmzkODKpP2N+1w4l0rcXHEXuNJC6NpW8
1i2CWnlb64hQ0L1tOBVabmUXmlwbasV5dBnysupn3IZHOMO+liNSb9T2RHpvtKSw
U4hu4cZXSGNWoFlWzrs7SoJf1uFF0h5GlrgUm5TGPA1oUPsRzJKRS6D70daElmpi
e5OszD89bs/LftHY4wpcwQ3ic/PSCqMGdF4aFAzVtfseND9tzrK+8aa8GX18bb9R
hGfEeiXzp2EnIEtBMUmrrk0cV9thx1zuwaGoai0P2E82SXbMglrKYVAm0xN3yxRc
77u47S479o7xGSdT2/EBX+EIWnFrGZheT10iPc+aEWRRTxWFf5e10j1i3F1Lw7cL
5P3PNrMUv3s1Vf82gHKfdtlaYZZoMuF3r03ezt2EScg9MDxhytBDHxiokfw7NRdA
OA8IaXuoU4MSXArgkdJ89kzV1AnK8aMGlQY/BXfjPqgPUGRQ8TK/sEDp2I5poMeZ
t2xCtxUvCA39NM/xBDyS
=jurT
-----END PGP SIGNATURE-----
Merge tag 'renesas-clock-fixes-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Merge "Renesas ARM Based SoC Clock Fixes For v3.17" from Simon Horman:
* ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
This resolves a problem introduced by 4bfb358b1d
("ARM: shmobile: Add r8a7791 legacy SDHI clocks")
which was included in v3.15.
This fix does not have any run-time affect at this time.
* ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
This resolves a problem introduced by 9f13ee6f83
("ARM: shmobile: r8a7790: add div4 clocks")
which was included in v3.11.
This fix does not have any run-time affect at this time.
* ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name
This resolves a problem introduced by a0f7e7496d
("ARM: shmobile: sh73a0: add CMT1 clock support for DT")
which was included in v3.17-rc1.
This fix does not have any run-time affect at this time as the clock in
question is used by a SCIF device that is not enabled by default.
* tag 'renesas-clock-fixes-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name
Signed-off-by: Olof Johansson <olof@lixom.net>
- Fixes suspend/resume issue on imx53-qsrb due to PMIC IRQ pin
configuration missing
- A couple small SolidRun board fixes/correction from Rabeeh
and Russell
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJT/XBJAAoJEFBXWFqHsHzOuqgH/3XqY4n0kL7lZQGRl8sBA/1m
bLtlKYaGjtn5ITXYONuWyxk9MrkCUaVUEEkcM3Gty6kHbCZ9F8nqSa5NiYs4MyGR
FiBX1GANmz96t61i90jlNNxHdPfnmgj3ZXEDTEj9g2brwGceUgQZv4/D59qSy41H
VlyIIOREQbrIoFlln1cEaKf2UXOpmSpB835QHROwy9K4aK0kZKAR4v5eqM2aQaIl
9VpvR5Xfsmr5vH/srlkY+Vc2ODVF1nQZsa3ikleAh2rzFQ4thwSKqpSxF7HL6EAo
zafJuI67ctyzIFk1PlsUuqCM2NimzACnpgrNG6Vn2KDq/JavNIsuyna0KgzzXqE=
=jOFz
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
Merge "ARM: imx: fixes for 3.17, 2nd take" from Shawn Guo:
i.MX fixes for 3.17, 2nd take:
- Fixes suspend/resume issue on imx53-qsrb due to PMIC IRQ pin
configuration missing
- A couple small SolidRun board fixes/correction from Rabeeh
and Russell
* tag 'imx-fixes-3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: microsom-ar8035: MDIO pad must be set open drain
ARM: dts: hummingboard/cubox-i: change SPDIF output to be more descriptive
ARM: dts: hummingboard/cubox-i: add USB OC pinctrl configuration
ARM: dts: imx53-qsrb: Fix suspend/resume
Signed-off-by: Olof Johansson <olof@lixom.net>
by default as that's what many boards expect. Also fixes for omap5
clocks, PM wake-up events, GPIO interrupt cells for dra7, and few
other minor fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT/PNtAAoJEBvUPslcq6VzQsoP/0a2WXN51/oqrhviMGURLDFy
57Mc6Yz4annJPeyzmD7myPEoppOAzC+Ysp04gC2Ig5ygj94KPJb5Mc2o28lZT4wr
OTNjQA2W+5CpefXHTRSRaoqcfOD9qUmcnb+rGTiTIxSu8DYxWaf8seAxL2Q2YJ7u
+DPREfhs0YZyA1kxiZy1xssR2pM1lsPthf0hBDxPyxaTnBxvWFlZAw+06xWVlA+G
Lk5NZZOFXKTKGV6Cq28q+FQvveUqW3An87pfFZZsSyBQfCIZdNDtCQ7OXCgjA+E2
OZ7fYh+phbFkr8W+0fJGu3b3t8ehFm74tvQ1qQlb0R0GrqRMaYXooO4Wk73sgJmc
MbaBGZ7CzkLC7IgvfitbdDRlFmrQeVHoBoH+UtwkNh4CyWtBzdrvxxgj8BvtJSYs
rWfppeEZrsWKdESNdjV4YFqkrMEHfyOlTjAqDUVd8CjtF1fOyQ/WkfpgqcpsYfj5
7YhW5qMjtYYmNoklU62sQyJx2HhpYpjdI83qmKT6zUM2OlrJYmco3FFXFRHRfNv2
o6M61iO+dwYuEjfZ1NhlCep41/MJ2El1oYMnNNvXy/DBveh9887TuX4S5WYIcF2M
ofhv4y3JDGPfXvvdpE/M1FiqHoJ0Epl+IUbaeNR61mbBmZZG3ExvPiqvYgdrhbnk
2kr7x8fPRfgsc41z1ajH
=i+aY
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.17/fixes-against-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "omap fixes against v3.17-rc2" from Tony Lindgren:
Fixes for omaps, mostly to revert NAND back to using software ECC
by default as that's what many boards expect. Also fixes for omap5
clocks, PM wake-up events, GPIO interrupt cells for dra7, and few
other minor fixes.
* tag 'omap-for-v3.17/fixes-against-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
ARM: OMAP2+: hwmod: Rearm wake-up interrupts for DT when MUSB is idled
ARM: dts: Enable UART wake-up events for beagleboard
ARM: dts: Remove twl6030 clk32g "regulator"
ARM: OMAP2+: omap_device: remove warning that clk alias already exists
ARM: OMAP: fix %d confusingly prefixed with 0x in format string
ARM: dts: DRA7: fix interrupt-cells for GPIO
mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc()
ARM: dts: omap3430-sdp: Revert to using software ECC for NAND
ARM: OMAP2+: GPMC: Support Software ECC scheme via DT
mtd: nand: omap: Revert to using software ECC by default
Add the core device nodes for the SARADC found on both the Cortex-A9 series
(rk3066 and rk3188) as well as the newer rk3288.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Radxa Rock uses a hym8563 as rtc. Add the i2c device and necessary
pinconfig for the interrupt pin - labeled rtc_int in the schematics.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
PWM0 is the PWM associated with the LCD backlight. Enable it.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds the PWM info (other than the VOP PWM) to the main rk3288
dtsi file.
Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds support for Olimex A20-OLinuXino-LIME board.
Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Commit af040ffc9b ("ARM: make it easier to check the CPU part number
correctly") changed ARM_CPU_PART_X masks, and the way they are returned and
checked against. Usage of read_cpuid_part_number() is now deprecated, and
calling places updated accordingly. This actually broke cpuidle-big_little
initialization, as bl_idle_driver_init() performs a check using an hardcoded
mask on cpu_id.
Create an interface to perform the check (that is now even easier to read).
Define also a proper mask (ARM_CPU_PART_MASK) that makes this kind of checks
cleaner and helps preventing bugs in the future. Update usage accordingly.
Signed-off-by: Juri Lelli <juri.lelli@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may
falsely trigger a watchpoint exception, leading to potential data aborts
during exception return and/or livelock.
This patch resolves the issue in the following ways:
- Replacing our uses of CLREX with a dummy STREX sequence instead (as
we did for v6 CPUs).
- Removing the clrex code from v7_exit_coherency_flush and derivatives,
since this only exists as a minor performance improvement when
non-cached exclusives are in use (Linux doesn't use these).
Benchmarking on a variety of ARM cores revealed no measurable
performance difference with this change applied, so the change is
performed unconditionally and no new Kconfig entry is added.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ARMv6 and ARMv7 early abort handlers clear the exclusive monitors
upon entry to the kernel, but this is redundant:
- We clear the monitors on every exception return since commit
200b812d00 ("Clear the exclusive monitor when returning from an
exception"), so this is not necessary to ensure the monitors are
cleared before returning from a fault handler.
- Any dummy STREX will target a temporary scratch area in memory, and
may succeed or fail without corrupting useful data. Its status value
will not be used.
- Any other STREX in the kernel must be preceded by an LDREX, which
will initialise the monitors consistently and will not depend on the
earlier state of the monitors.
Therefore we have no reason to care about the initial state of the
exclusive monitors when a data abort is taken, and clearing the monitors
prior to exception return (as we already do) is sufficient.
This patch removes the redundant clearing of the exclusive monitors from
the early abort handlers.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Kernel module build with GCOV profiling fails to load with the
following error:
$ insmod test_module.ko
test_module: unknown relocation: 38
insmod: can't insert 'test_module.ko': invalid module format
This happens because constructor pointers in the .init_array section
have not supported R_ARM_TARGET1 relocation type.
Documentation (ELF for the ARM Architecture) says:
"The relocation must be processed either in the same way as R_ARM_REL32 or
as R_ARM_ABS32: a virtual platform must specify which method is used."
Since kernel expects to see absolute addresses in .init_array R_ARM_TARGET1
relocation type should be treated the same way as R_ARM_ABS32.
Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is important for the MicroSOM implementation due to the
following details -
1. VIH of the Atheros phy is 1.7V.
2. NVCC_ENET which is the power domain of the MDIO pad is driven by the
PHY's LDO (i.e. either 1.8v or 2.5v).
3. The MicroSOM implements an onbouard 1.6kohm pull up to 3.3v (R3000).
In the case the PHY's LDO was 1.8v then there would be only a 100mV
margin for the signal to be acknowledged as high (1.8v-1.7v).
Due to that setting the pad as an open drain will let the 1.6kohm pull
that signal high to 3.3 that assures enough margins to the PHY to be
acked as '1' logic.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated.
Fixed by using proper divider clock types for the clock nodes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
These nodes are required so that the flow controller driver can obtain
the I/O memory region from device tree rather than hard-coding it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This pinmux tables currently omit any configuration for PCIe clk_req,
wake, and rst pins, which in turn causes intermittent failures in
U-Boot's PCIe support. Import an updated version of the pinmux tables
which rectifies this.
(While I'm still hoping to remove the pinmux tables from DTs for
Tegra124+ devices, while they're still here, they may as well be
complete and correct).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This enables the integrated SATA controller on the Tegra124 system-on-chip
on the Jetson TK1 board and adds regulators for the onboard Molex connector
commonly used to power SATA devices. The regulators are marked always-on
since they can be used for other purposes than powering SATA devices.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
[swarren, fixed node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
[swarren, fixed node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The audio on the board is using McASP <-> tlv320aic3106 codec and we have
LineIn and LineOut jacks.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add pinctrl nodes for the McASP0 pins and configure McASP to the desired
mode for the board.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add OF_DEV_AUXDATA for mcasp to be able to use clocks.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
There were several issues (of varying degree of importance) pointed out
with this code late in the review cycle, yet the code was still merged.
Let's rip it out for now and look at resubmitting at a later time.
This reverts most of commit 4fbe66d990.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Looks like MUSB cable removal can cause wake-up interrupts to
stop working for device tree based booting at least for UART3
even as nothing is dynamically remuxed. This can be fixed by
calling reconfigure_io_chain() for device tree based booting
in hwmod code. Note that we already do that for legacy booting
if the legacy mux is configured.
My guess is that this is related to UART3 and MUSB ULPI
hsusb0_data0 and hsusb0_data1 support for Carkit mode that
somehow affect the configured IO chain for UART3 and require
rearming the wake-up interrupts.
In general, for device tree based booting, pinctrl-single
calls the rearm hook that in turn calls reconfigure_io_chain
so calling reconfigure_io_chain should not be needed from the
hwmod code for other events.
So let's limit the hwmod rearming of iochain only to
HWMOD_FORCE_MSTANDBY where MUSB is currently the only user
of it. If we see other devices needing similar changes we can
add more checks for it.
Cc: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.16
Signed-off-by: Tony Lindgren <tony@atomide.com>
For device tree based booting, we need to use wake-up
interrupts like we already do for some omaps. This fixes
a PM regression on beagleboard compared to legacy booting.
Tested-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The kernel has never supported clk32g as a regulator since it is a clock
and not a regulator. Fortunately nothing actually references this node so
we can just remove it.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When an alias for a clock already exists the warning is printed. For
every module with a main_clk defined, a clk alias for fck is added.
There are some components that have the same main_clk defined, so this
is a really normal situation.
For example the am33xx edma device has 4 components using the same main
clock. So there are three warnings in the boot log for this already
existing clock alias:
platform 49000000.edma: alias fck already exists
platform 49000000.edma: alias fck already exists
platform 49000000.edma: alias fck already exists
As this is only interesting for developers, this patch changes the
message to a debug message.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPIO modules are also interrupt sources. However, they require both the
GPIO number and IRQ type to function properly.
By declaring that GPIO uses interrupt-cells=<1>, we essentially do not
allow users of the nodes to use the interrupt property appropritely.
With this change, the following now works:
interrupt-parent = <&gpio6>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
Fixes: 6e58b8f1da ('ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board')
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For v3.14 and prior, 1-bit Hamming code ECC via software was used
for NAND on this board.
Commit c06c527016 in v3.15 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.
This ECC layout change causes NAND filesystems created in v3.14
and prior to be unusable in v3.15 and later. So revert back to
using software ECC scheme.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For v3.14 and prior, 1-bit Hamming code ECC via software was the
default choice for some boards e.g. 3430sdp.
Commit ac65caf514 in v3.15 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.
This ECC layout change causes NAND filesystems created in v3.14
and prior to be unusable in v3.15 and later. So don't mark "sw" scheme
as deperecated and support it.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For v3.12 and prior, 1-bit Hamming code ECC via software was the
default choice. Commit c66d039197 in v3.13 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.
This ECC layout change causes NAND filesystems created in v3.12
and prior to be unusable in v3.13 and later. So revert back to
using software ECC by default if an ECC scheme is not explicitely
specified.
This defect can be observed on the following boards during legacy boot
-omap3beagle
-omap3touchbook
-overo
-am3517crane
-devkit8000
-ldp
-3430sdp
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
* Confine SH_INTC to platforms that need it
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT+oswAAoJENfPZGlqN0++/A8QAK2yp96zl7gABtddgkunNJiV
xWCm4wcP+7dIrLpwizxtt/6HMPj9ZJHYtcxRRKVlzquwcukeVCIkfZ3Qvn2JilWM
+b4rVRGzQ+z0M7SCpNGjtgFc1IFrVrzuxZpPwgseQ5I6HQsZJKUi3qn5rRJSEax2
w+ANis2eZfmSBdu3Qsx2QBDXvS7ZPlLpimoAE+rjr60dZnljcrvBrVHQvSgpEHxn
4rXPbYrrkIee32J4lxLRDPtn5fvAsrr+vcLXEYqyFr2292U2PAxIrjZgrRzZYNtD
L6xmhZAhdmIpC0gLDLyKQhwj/9pfGFxFErZX9jeGdPT2KTEEYPkSxb75kdTwmxP4
DEtZG9Nuu6CQCBldrMt6kpujn+XCYRl94cSyUffJ5KVhNUiqB+e+JP80Yj9HB7QU
nGUfs2hQ/azY8XEiwvnls0314thkB5gN7KHxmlaFa9Wz7cgYFwWAguHH8qrq839U
+i+7dUg7nlmVoIAvzYIIA+L7x3xX4gEwsf88x3i04DPp0A8/oDAwGrqM5QzsaZpD
ghodnKRG7foc+29RLYka5CxF/MqKzpJu675sSBCVB3uW9NZpoGSwml/NN9yUu1JD
uvU2FECcbxF5OU6RHfq8FFql0fAOVeVWsMCEXgkjpZOXynKU15VTf1K2d+qkUZ/Y
gV45Jj+yCZhYs0wbXUml
=QSyy
-----END PGP SIGNATURE-----
Merge tag 'renesas-sh-drivers-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas
Pull SH driver fix from Simon Horman:
"Confine SH_INTC to platforms that need it"
* tag 'renesas-sh-drivers-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
sh: intc: Confine SH_INTC to platforms that need it
Hummingboard has no over current hardware, so disable the over current
detection for both ports.
Cubox-i has over current hardware, so appropriately configure this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
On r8a7791, i2c6 (aka iic3) doesn't need pinmux, but the koelsch dts
refers to non-existent pinmux configuration data:
pinmux core: sh-pfc does not support function i2c6
sh-pfc e6060000.pfc: invalid function i2c6 in map table
Remove it to fix this.
Fixes: commit 1d41f36a68 ("ARM: shmobile:
koelsch dts: Add VDD MPU regulator for DVFS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Olof Johansson <olof@lixom.net>
Working on Gigabit/PCIe support in U-Boot for Apalis T30 I realised
that the current device tree source includes for our modules only
happen to work due to referencing the on-carrier 5v0 supply from USB
which is not at all available on-module. The modules actually contain
TPS60150 charge pumps to generate the PMIC required 5 volts from the
one and only 3.3 volt module supply. This patch fixes this.
(Note: When back-porting this to v3.16 stable releases, simply drop the
change to tegra30-apalis.dtsi; that file was added in v3.17)
Cc: <stable@vger.kernel.org> #v3.16+
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
dts files and addition of the new Rockchip list to MAINTAINERS.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJT+hwkAAoJEPOmecmc0R2Bda4IAJ7rxypWxi8RtfxULHu1oGxZ
cdmAsaedAkjTn6tye/99lv1WkLzUD+Q3AxLX6Glu8PgTkocbwtkVTP+gMbv7zwfN
Z9bA6kazPL4Rskr6Am8BFKkGhXHCXChGP1J3z9Gyh07Vu2+3zsvRzyM7hySt3TqZ
EA2dL/uODlukw6EPzFaqGWZLn1OuJmkHXDfnZ3lBI/GFZD9qt5DnYswMBlDlIwr6
D08jmcleRA3wpnY1HXYR2cN1sJmcEP6xVE8ApXd71X0MtumEy49ZTR+4T5/Sh/XN
OPheoH3UUVtXVrAa5fsoUE2xsKs3PZgnIHk1kQklpbw+HArbN+aW0Jh6CySb65Q=
=aNJj
-----END PGP SIGNATURE-----
Merge tag 'v3.17-rockchip-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Merge "ARM: rockchip: fix for 3.17" from Heiko Stubner:
Pinctrl that got accidentially dropped when reorganizing the
dts files and addition of the new Rockchip list to MAINTAINERS.
* tag 'v3.17-rockchip-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
MAINTAINERS: add new Rockchip SoC list
ARM: dts: rockchip: readd missing mmc0 pinctrl settings
Signed-off-by: Olof Johansson <olof@lixom.net>
During the restructuring of the Rockchip Cortex-A9 dtsi files it seems
like the pinctrl settings vanished at some point from the mmc0 support.
This of course renders them unusable, so readd the necessary pinctrl
properties.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Only a single patch in here that fixes a DTC warning.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT2hD6AAoJEBx+YmzsjxAgV9YP/1wML2m04CODnLmLhKyx1GyM
VyBoEHb+o7P7TRyK7ePIVkGhGnQjYGMyXAI2KfOiBJpAl23uxXCXSNKc6WY+nBAw
6T6qL6w+tPIPW4B79fAjmoPksqhoVf9sAKAkdu6+ETwKMHRaF0IesPRTg9t21Wcd
yHHDY4z/qaFCMV59zeOIWMxM0V0gvUa46+bXC2flyTcTz5RgyUswCOXKHLvXfK1L
w8B+V34AeBtm2EzG6co1iOJVRKXlrjzUg25+adbRissNfvmVkPwYkQJNoBO6r/PO
Rxf7Mq50oovPl/Oc83e3RZl3tE8ds12t+ScS0qUFq6+tBvyq53IYP+51IhDOGiR3
a6PB1nPEXtvUt09xv5SPJiRsB+BFrh5hx+qWbDvUNQL5FZrqBxa63H6qArybFQXg
GaY8Zv5gdiMvAU0tdk7v4pduJkvvoG2GALGHPrcKmrpg2+qQ4LDKOJxErIEqOUi2
ERp7c0kODDz18F9OmjGYU2R7XT6Ji8h4MS/hbCiLajcboQMe3yClrcVB8ts+AUKJ
NSDWl5Q0/8uHhk40FAaGYEqVLakk8vhXwdg1hpcXzIg3dJg+P09dYK5nIOBzKIok
+eVXZ8xjcRnoBAumljZ3eGbTuysGDO95E56coDPE4IiAe4Esi7kl3fUS/NICoOGs
MC9tjeyMoscy+hoGsP57
=PL45
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Merge "Allwinner DT changes, take 2" from Maxime Ripard:
Only a single patch in here that fixes a DTC warning.
* tag 'sunxi-dt-for-3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Add an "interrupt-parent = <&gic>;" at the top, which is inherited by
all child nodes, so the "interrupt-parent" properties can be removed
from the individual child nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's already an "interrupt-parent = <&gic>;" at the top, which is
inherited by all child nodes, so the "interrupt-parent" property in
the sound node can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's already an "interrupt-parent = <&gic>;" at the top, which is
inherited by all child nodes, so the "interrupt-parent" property in
the sound node can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's already an "interrupt-parent = <&gic>;" at the top, which is
inherited by all child nodes, so the "interrupt-parent" properties in
the serial nodes can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Currently the sh-intc driver is compiled on all SuperH and
non-multiplatform SH-Mobile platforms, while it's only used on a limited
number of platforms:
- SuperH: SH2(A), SH3(A), SH4(A)(L) (all but SH5)
- ARM: sh7372, sh73a0
Drop the "default y" on SH_INTC, make all CPU platforms that use it
select it, and protect all sub-options by "if SH_INTC" to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
4bfb358b1d
(ARM: shmobile: Add r8a7791 legacy SDHI clocks)
added r8a7791 SDHI clock support.
But, it is missing
"0x0100: x 1/8" division ratio.
This patch fixes hidden bug.
It is based on R-Car H2 v0.7, R-Car M2 v0.9.
Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
9f13ee6f83
(ARM: shmobile: r8a7790: add div4 clocks)
added r8a7790 DIV4 clock support.
But, it is missing
"0x0100: x 1/8" division ratio.
This patch fixes hidden bug.
It is based on R-Car H2 v0.7, R-Car M2 v0.9.
Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add basic IPQ8064 SoC include device tree and support for basic booting on
the AP148 Reference board with support for UART, I2C, and SPI.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the necessary DT node to probe the serial driver on
APQ8084 platforms.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the necessary node to probe the global clock
controller on APQ8084 platforms.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Increase max i2c bus frequency beyond the default for faster
data transfers. According to the manual, these faster speeds are
only available when the board is wired up the right way. In this case,
the vendor kernel has run at this speed for a long time.
sda-delay is needed for talking to RTC on PMIC, otherwise the i2c
controller never sees an ACK. Strangely the other PMIC i2c slave (the
main one) works fine even without this delay. I Chose value 100 to
match the vendor kernel.
Signed-off-by: Daniel Drake <drake@endlessm.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The ODROID kernel shows that the PMIC interrupt line is hooked up
to pin GPX3-2.
This is needed for the max77686-irq driver to create the PMIC IRQ
domain, which is needed by max77686-rtc.
Signed-off-by: Daniel Drake <drake@endlessm.com>
Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch gathers a few devicetree patches needed for the reworks found in
the later patches to be sent. More precisely, it holds:
- The addition of ddrck for the sama5d3 and the sam9 SoCs
- The addition of the shutdown controller node in the sama5d3 DTSI
- The slight rework of the ramc bindings for the SoCs that have several RAM
controllers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJTx3pVAAoJEBx+YmzsjxAgMZgP/28I2pynhWU5hK86DOsiggTN
8AgBMkg6Bhg0jASsAPZXUR+sSOnBLhprKwQNTFRzHnRJPktvLzyh4f8s1tXQFxV+
7yVWuPP4X0SI6W88HUX0gEdG1jV6bZUIM4PhOfpkFIU4LDukNsKRb4u80v4UoirZ
V5X0P2GJs3j6iC3zLO17/e2U0l4l0mRnZRr3aRHLMmFm/a2zfsiNIkhLiGDEwcdF
i/N6RMPuZkTLWluowBzMyJGCRNNmO4v9aNGNyWgAKqdqQMvs95pXId6lVqP5OcTV
VrLCRnHqdphmxargv8iL+O+BhwfhDTHVZgB8bmp5TGlh7GDtpULcmJWavxtkRua/
iro9DEzQAsLnek++VkB+VMG5Y/VxZPQIVvebatK2w/s+5KD3rLHHRYwZsDk2b6t9
LIHg296COy2ngT3xyag7VUtKlciKS3wMbYvyRtFHvIGL11fXfObYpkeBI1lVji8M
osxSUYMtiVMnS7/nlmbCscEMyozqo2bnTkFz+3Kt7PZG3sf2QBo+XG+47d7EH5MU
DZ0mc3J6TvBw6+LzuSkV91BuGSUxe5TzHXZIobr09853ziqgR4/oBNPsa9iNriIw
w1MCym5q916iwf5ZphLOd0mK6KcC9rHGPCA/r2xKgoW18hWLKNEuRq4DYeTYOXFm
B9oEa81eX0lpvNHOwke0
=4QeK
-----END PGP SIGNATURE-----
Merge tag 'at91-dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux
Pull AT91 ramc and reset/poweroff related DT patches from Maxim Ripard:
"This branch gathers a few devicetree patches needed for the reworks found in
the later patches to be sent. More precisely, it holds:
- The addition of ddrck for the sama5d3 and the sam9 SoCs
- The addition of the shutdown controller node in the sama5d3 DTSI
- The slight rework of the ramc bindings for the SoCs that have several RAM
controllers"
Conflicts:
arch/arm/boot/dts/at91sam9g45.dtsi
The current pinfunc define all uart CTS_B IO port for DCE uart 'CTS_B'
IP port. Since uart IP port 'CTS_B' is output, and it don't need to
set 'SELECT_INPUT' bit.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This adds support for the A20 Hummingbird:
http://www.merrii.com/en/pla_d.asp?id=171
This patch enable most on-board peripherals supported on current kernel,
such as uart, i2c, spi, pwm, ohci/ehci, gmac and mmc.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch add generic dts node for uart3/4/5, i2c3 and spi2.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The clock-frequency values of the i2c controller nodes match the
defaults of the driver. Remove the properties to use the defaults,
and be consistent with sun8i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
i2c0 is connected to the gsl1680 capacitive touch panel controller.
i2c1 is connected to an mma7660 3-axis accelerometer.
i2c2 is connected to the front and back gc0309 camera sensors.
The camera sensors require additional regulators be enabled before
they are available.
All these peripherals are not supported by the kernel yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add nodes for the 3 i2c controllers found on A23 SoCs to the sun8i DTSI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On i.MX6Q, gpu2d_axi and gpu3d_axi are either from AXI or
AHB clock, but on i.MX6DL, gpu2d_axi and gpu3d_axi are
from mmdc_ch0_axi_podf, and they can NOT be gated by mmdc_ch0_axi
's clock gate, the mux option register field(CCM_CBCMR)
is marked as "Reserved" now on i.MX6DL RM, so correct these
two clks setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Previous version had an extra 'fsl' which made the pins not match
any entry. The console message,
vf610-pinctrl 40048000.iomuxc: no fsl,pins property in node \
/soc/aips-bus@40000000/iomuxc@40048000/vf610-twr/esdhc1grp
is displayed without the fix. The prior version would generally
work as u-boot sets the pins properly for sdhc. This change allows
Linux sdhc use even if u-boot is built without sdhc support.
Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Fixes: 0517fe6aa8 ("ARM: dts: vf610-twr: Add support for sdhc1")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Since ARCH_MXC already selects ARCH_HAS_OPP, it's really unnecessary for
SOC_IMX27 and SOC_IMX5 to select it again.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
After the suspend routine running in OCRAM puts DDR into self-refresh,
it will access IOMUXC block to float DDR IO for power saving. A TLB
missing of IOMUXC base address may happen in this case, and triggers an
access to DDR, and thus hangs the system.
The failure is discovered by running suspend/resume on a Cubox-i board.
Though the issue is not Cubox-i specific, it can be hit the on the board
quite easily with the 3.15 or 3.16 kernel.
Fix the issue with a dummy access to IOMUXC block at the beginning of
suspend routine, so that the address translation can be filled into TLB
before DDR is put into self-refresh.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Cc: <stable@vger.kernel.org>
Acked-by: Anson Huang <Anson.Huang@freescale.com>
My earlier patch 1fc593feaf ("ARM: imx: build i.MX6 functions
only when needed") fixed a problem with building an i.MX5 kernel,
but now the problem has returned for the case where we allow
ARMv6K SMP builds in multiplatform. With CONFIG_CPU_V7 disabled,
but i.MX3 and SMP enabled, we get this build error:
arch/arm/mach-imx/built-in.o: In function `v7_secondary_startup':
:(.text+0x5124): undefined reference to `v7_invalidate_l1'
This puts the code inside of an "ifdef CONFIG_SOC_IMX6" to hopefully
do the right thing in all configurations.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit adds the required pin muxing for the network interfaces and
the MDIO interface to be properly initialized. For instance, this makes
it possible for a bootloader to initialize and access the network interfaces
Only the second network interface is pin muxed. The first network interface is
connected to the PHY using SGMII, which uses a dedicated SerDes lane.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1407759281-11513-7-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the required pin muxing for the network interfaces and
the MDIO interface to be properly initialized. For instance, this makes
it possible for a bootloader to initialize and access the network interfaces
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1407759281-11513-6-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the required pin muxing for the network interfaces and
the MDIO interface to be properly initialized. For instance, this makes
it possible for a bootloader to initialize and access the network interfaces
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1407759281-11513-5-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the required pin muxing for the network interfaces and
the MDIO interface to be properly initialized. For instance, this makes
it possible for a bootloader to initialize and access the network interfaces
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1407759281-11513-4-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the required pin muxing for the network interfaces and
the MDIO interface to be properly initialized. For instance, this makes
it possible for a bootloader to initialize and access the network interfaces.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1407759281-11513-3-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the pin mux configuration for the two network interfaces
and the MDIO interface in the Armada 370 SoC .dtsi file. Only the
configuration for RGMII is added for now.
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1407759281-11513-2-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375 SoC has the same real time clock as the one used in
other Marvell EBU platforms. This patch consequently updates the
Device Tree of the Armada 375 SoC to describe the internal RTC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1406817122-15675-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This adds pin-muxing info for the i2c controller / port combinations
which are known to be used on actual boards.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The card detect pin setting was taken from the original fex file,
and is confirmed to work.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add nodes for the 3 mmc controllers found on A23 SoCs to the sun8i DTSI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds pin-muxing info for the mmc controller / port combinations
which are known to be used on actual boards.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The MMC module clocks on sun8i are the same as those found on
previous Allwinner SoCs, module 0 clocks.
This patch adds the clocks nodes to the dtsi with existing drivers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we have R_PIO controller support and the pinmux for R_UART,
add the correct pinctrl properties to the R_UART node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
R_UART is available on extra pads on certain tablets, which makes it
ideal for use as a console. Here we add the pins for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
uart0 on sun8i is only muxed with mmc0, which makes it a poor choice
for the console. However, some tablets only have pads for uart0
available on the circuit board.
Here we add the uart0 pinmux set for people who need it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we have a driver for the sun8i PIO controller,
add the corresponding device node to the dtsi.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 SoC has a sun4i-compatible DMA controller. Let's add a node to
represent it on the device tree.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A10S and A13 SoCs have sun4i-compatible DMA controllers. Let's add
the corresponding nodes to represent them on the device tree.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Let's add a node to represent the A10 DMA controller on the device tree.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we have a driver for sun6i's rtc hardware, add a device node
for it so we can use it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
sun8i shares the same rtc hardware as sun6i. Now that we have a driver
for it, add a device node to the DTSI for it so we can use it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the Lager board specific device node part for VIN1 (composite video in);
add the device node for Analog Devices ADV7180 video decoder to IIC2 bus.
Add the necessary subnodes to interconnect VIN1 and ADV7180 devices.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[Sergei: rebased, edited changelog and summary]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device nodes for the four video input controllers on the R8A7790.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[Sergei: renamed VIN device nodes, edited changelog]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add register sets used for access by the DMA engine, and DMA properties to
the MSIOF nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a DMA property to the QSPI node
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add register sets used for access by the DMA engine, and DMA properties to
the MSIOF nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a DMA property to the QSPI node
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Instantiate the two system DMA controllers in the r8a7791 device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Instantiate the two system DMA controllers in the r8a7790 device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the SYS-DMAC0 and SYS-DMAC1 clocks to the MSTP2 clock node. They
will be used by the upcoming DMAC DT nodes.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Koelsch board dependent part of the VIN1 device node. Add the device
node for Analog Devices ADV7180 video decoder to I2C2 bus. Add the necessary
subnodes to interconnect VIN1 and ADV7180 devices.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Henninger board dependent part of the VIN0 device node. Add the
device node for Analog Devices ADV7180 video decoder to I2C2 bus. Add the
necessary subnodes to interconnect VIN0 and ADV7180 devices.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the generic R8A7791 parts of the VIN[0-2] device nodes. Add aliases for
the VIN[0-2] device nodes.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The PMIC interrupt pinctrl line was added to the rk3288-evb-act8846,
but it's the same line on both the ACT8846 version and the RK808
version. This makes a lot of sense since they share the same SoC
daugherboard. Move the pinctrl definition to the common file so we
can use it for the RK808 version.
NOTE: The PMIC interrupt doesn't _actually_ go to the PMIC on the
ACT8846 version of the board (it does on the RK808), but our
convention is to label things as they're labelled on the schematics.
In the very least you can argue that this is the interrupt from the
PMIC daughtercard even if it doesn't actually go to the PMIC chip.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This enables basic SD and eMMC support. Things are not yet running at
the fastest speed and we don't have the regulators specified, but we
can at least use the eMMC and SD cards now.
A note:
* Though MMC DDR50 mode is partially supported in the dw_mmc
rk3288-specific code in Addy's patch, Addy's patch doesn't add
tuning support. That means DDR50 mode is not reliable. From the
3288 TRM: "Tuning is required for other speed modes-such as
DDR50-even though the output delay from the card is less than one
cycle." Thus, we don't enable MMC DDR50 mode in this patch.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds support for the sdmmc and emmc ports on the rk3288.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And "supports-highspeed" property in dw-mmc is deprecated.
"supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tushar Behera <trblinux@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
